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ignore not ours code

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This commit is contained in:
Liqing Qin 2024-10-15 11:25:38 +02:00
parent 279df15956
commit f9f09c6fc9
1415 changed files with 489 additions and 681059 deletions
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72
FPGA_firmware/.gitignore vendored
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@ -1,72 +0,0 @@
# Working with Altera Quartus II (Q2) and do proper versioning is not that easy
# but if you follow some rules it can be accomplished. :)
# This file should be placed into the main directory where the .qpf file is
# found. Generally Q2 throws all entities and so on in the main directory, but
# you can place all stuff also in separate folders. This approach is followed
# here. So when you create a new design create one or more folders where your
# entities will be located and put a .gitignore in there that overrides the
# ignores of this file, e.g. one single rule stating "!*" which allows now all
# type of files. When you add a MegaFunction or another entity to your design,
# simply add it to one of your private folders and Q2 will be happy and manage
# everything quite good. When you want to do versioning of your generated
# SOF/POF files, you can do this by redirecting the generated output to an own
# folder. To do this go to:
# "Assignments"
# -> "Settings
# -> "Compilation Process Settings"
# -> "Save project output files in specified directory"
# Now you can either place a .gitignore in the directory and allow the following
# list of types:
!*.sof
!*.pof
# or you create an own submodule in the folder to keep binary files out of your
# design.
# Need to keep all HDL files
!*.vhd
!*.v
!*.sv
# ignore Quartus II generated files
*_generation_script*
*_inst.vhd
*.bak
*.cmp
*.done
*.eqn
#*.hex
*.html
*.jdi
*.jpg
# *.mif
*.pin
*.ptf.*
*.qar
*.qarlog
*.qws
*.rpt
*.smsg
#*.sopc_builder
*.summary
*.tcl
*.txt # Explicitly add any text files used
*~
*example*
# *sopc_*
# *.sdc # I want those timing files
# ignore Quartus II generated folders
*/db/
*/incremental_db/
*/simulation/
**/simulation/
*/timing/
software/
*.o
*.d
#*/testbench/
*/*_sim/
incremental_db/
db/
_output_files/
PLLJ_PLLSPE_INFO.txt

6
FPGA_firmware/README.txt
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@ -1,2 +1,4 @@
The Firmware is developed from:
http://www.alterawiki.com/uploads/7/71/Simple_Socket_Ethernet_guide.pdf
This firmware is generted from Simple Socket Server Example.
M.Dziewiecki created sensor_interface.v in 2019, which controls, collects, and sends ADC data to ethernet.
L.Qin created algo_top_cl_cali_rms.v in 2024, which reconstructs the position and sigma from the ADC data.

71
FPGA_firmware/clkctrl.BAK.qsys
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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element altclkctrl_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10M50DAF484C6GES" />
<parameter name="deviceFamily" value="MAX 10" />
<parameter name="deviceSpeedGrade" value="6" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="m10_rgmii.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="altclkctrl_input"
internal="altclkctrl_0.altclkctrl_input"
type="conduit"
dir="end">
<port name="inclk" internal="inclk" />
</interface>
<interface
name="altclkctrl_output"
internal="altclkctrl_0.altclkctrl_output"
type="conduit"
dir="end">
<port name="outclk" internal="outclk" />
</interface>
<module
name="altclkctrl_0"
kind="altclkctrl"
version="18.0"
enabled="1"
autoexport="1">
<parameter name="CLOCK_TYPE" value="1" />
<parameter name="DEVICE_FAMILY" value="MAX 10" />
<parameter name="ENA_REGISTER_MODE" value="1" />
<parameter name="GUI_USE_ENA" value="false" />
<parameter name="NUMBER_OF_CLOCKS" value="1" />
<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>

257
FPGA_firmware/clkctrl.sopcinfo
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<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="clkctrl" kind="clkctrl" version="1.0" fabric="QSYS">
<!-- Format version 19.1 670 (Future versions may contain additional information.) -->
<!-- 2023.06.07.19:47:52 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1686160072</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>GENERATION_ID</sysinfo_type>
</parameter>
<parameter name="AUTO_UNIQUE_ID">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>UNIQUE_ID</sysinfo_type>
</parameter>
<parameter name="AUTO_DEVICE_FAMILY">
<type>java.lang.String</type>
<value>MAX10FPGA</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
</parameter>
<parameter name="AUTO_DEVICE">
<type>java.lang.String</type>
<value>10M50DAF484C6GES</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE</sysinfo_type>
</parameter>
<parameter name="AUTO_DEVICE_SPEEDGRADE">
<type>java.lang.String</type>
<value>6</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>MAX 10</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<module
name="altclkctrl_0"
kind="altclkctrl"
version="19.1"
path="altclkctrl_0">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<parameter name="DEVICE_FAMILY">
<type>java.lang.String</type>
<value>MAX10FPGA</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
</parameter>
<parameter name="CLOCK_TYPE">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="NUMBER_OF_CLOCKS">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="ENA_REGISTER_MODE">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="GUI_USE_ENA">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="altclkctrl_input" kind="conduit_end" version="19.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>ui.blockdiagram.direction</name>
<value>input</value>
</assignment>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>conduit</type>
<isStart>false</isStart>
<port>
<name>inclk</name>
<direction>Input</direction>
<width>1</width>
<role>inclk</role>
</port>
</interface>
<interface name="altclkctrl_output" kind="conduit_end" version="19.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>ui.blockdiagram.direction</name>
<value>output</value>
</assignment>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>conduit</type>
<isStart>false</isStart>
<port>
<name>outclk</name>
<direction>Output</direction>
<width>1</width>
<role>outclk</role>
</port>
</interface>
</module>
<plugin>
<instanceCount>1</instanceCount>
<name>altclkctrl</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>ALTCLKCTRL Intel FPGA IP</displayName>
<version>19.1</version>
</plugin>
<plugin>
<instanceCount>2</instanceCount>
<name>conduit_end</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Conduit</displayName>
<version>19.1</version>
</plugin>
<reportVersion>19.1 670</reportVersion>
<uniqueIdentifier></uniqueIdentifier>
</EnsembleReport>

60
FPGA_firmware/clkctrl/clkctrl.bsf
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 272 104)
(text "clkctrl" (rect 119 -1 141 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 88 20 100)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "inclk" (rect 0 0 16 12)(font "Arial" (font_size 8)))
(text "inclk" (rect 4 61 34 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 96 72)(line_width 1))
)
(port
(pt 272 72)
(output)
(text "outclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
(text "outclk" (rect 242 61 278 72)(font "Arial" (font_size 8)))
(line (pt 272 72)(pt 160 72)(line_width 1))
)
(drawing
(text "altclkctrl_input" (rect 13 43 122 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "inclk" (rect 101 67 232 144)(font "Arial" (color 0 0 0)))
(text "altclkctrl_output" (rect 161 43 424 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "outclk" (rect 132 67 300 144)(font "Arial" (color 0 0 0)))
(text " clkctrl " (rect 243 88 540 186)(font "Arial" ))
(line (pt 96 32)(pt 160 32)(line_width 1))
(line (pt 160 32)(pt 160 88)(line_width 1))
(line (pt 96 88)(pt 160 88)(line_width 1))
(line (pt 96 32)(pt 96 88)(line_width 1))
(line (pt 97 52)(pt 97 76)(line_width 1))
(line (pt 98 52)(pt 98 76)(line_width 1))
(line (pt 159 52)(pt 159 76)(line_width 1))
(line (pt 158 52)(pt 158 76)(line_width 1))
(line (pt 0 0)(pt 272 0)(line_width 1))
(line (pt 272 0)(pt 272 104)(line_width 1))
(line (pt 0 104)(pt 272 104)(line_width 1))
(line (pt 0 0)(pt 0 104)(line_width 1))
)
)

18
FPGA_firmware/clkctrl/clkctrl.csv
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# system info clkctrl on 2023.06.07.19:47:50
system_info:
name,value
DEVICE,10M50DAF484C6GES
DEVICE_FAMILY,MAX 10
GENERATION_ID,1686160070
#
#
# Files generated for clkctrl on 2023.06.07.19:47:50
files:
filepath,kind,attributes,module,is_top
simulation/clkctrl.v,VERILOG,,clkctrl,true
simulation/submodules/clkctrl_altclkctrl_0.v,VERILOG,,clkctrl_altclkctrl_0,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
clkctrl.altclkctrl_0,clkctrl_altclkctrl_0
1 # system info clkctrl on 2023.06.07.19:47:50
2 system_info:
3 name,value
4 DEVICE,10M50DAF484C6GES
5 DEVICE_FAMILY,MAX 10
6 GENERATION_ID,1686160070
7 #
8 #
9 # Files generated for clkctrl on 2023.06.07.19:47:50
10 files:
11 filepath,kind,attributes,module,is_top
12 simulation/clkctrl.v,VERILOG,,clkctrl,true
13 simulation/submodules/clkctrl_altclkctrl_0.v,VERILOG,,clkctrl_altclkctrl_0,false
14 #
15 # Map from instance-path to kind of module
16 instances:
17 instancePath,module
18 clkctrl.altclkctrl_0,clkctrl_altclkctrl_0

10
FPGA_firmware/clkctrl/clkctrl.spd
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<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="simulation/submodules/clkctrl_altclkctrl_0.v"
type="VERILOG"
library="altclkctrl_0" />
<file path="simulation/clkctrl.v" type="VERILOG" />
<topLevel name="clkctrl" />
<deviceFamily name="max10" />
</simPackage>

131
FPGA_firmware/clkctrl/clkctrl.xml
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@ -1,131 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<deploy
date="2023.06.07.19:47:52"
outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/">
<perimeter>
<parameter
name="AUTO_GENERATION_ID"
type="Integer"
defaultValue="0"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_UNIQUE_ID"
type="String"
defaultValue=""
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_FAMILY"
type="String"
defaultValue="MAX 10"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE"
type="String"
defaultValue="10M50DAF484C6GES"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_SPEEDGRADE"
type="String"
defaultValue="6"
onHdl="0"
affectsHdl="1" />
<interface name="altclkctrl_input" kind="conduit" start="0">
<property name="associatedClock" value="" />
<property name="associatedReset" value="" />
<port name="inclk" direction="input" role="inclk" width="1" />
</interface>
<interface name="altclkctrl_output" kind="conduit" start="0">
<property name="associatedClock" value="" />
<property name="associatedReset" value="" />
<port name="outclk" direction="output" role="outclk" width="1" />
</interface>
</perimeter>
<entity
path=""
parameterizationKey="clkctrl:1.0:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1686160072,AUTO_UNIQUE_ID=(altclkctrl:19.1:CLOCK_TYPE=1,DEVICE_FAMILY=MAX 10,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false)"
instancePathKey="clkctrl"
kind="clkctrl"
version="1.0"
name="clkctrl">
<parameter name="AUTO_GENERATION_ID" value="1686160072" />
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
<parameter name="AUTO_UNIQUE_ID" value="" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
<generatedFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/synthesis/clkctrl.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v"
type="VERILOG"
attributes="" />
</childGeneratedFiles>
<sourceFiles>
<file path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl.qsys" />
</sourceFiles>
<childSourceFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
</childSourceFiles>
<messages>
<message level="Debug" culprit="clkctrl">queue size: 0 starting:clkctrl "clkctrl"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Debug" culprit="clkctrl"><![CDATA["<b>clkctrl</b>" reuses <b>altclkctrl</b> "<b>submodules/clkctrl_altclkctrl_0</b>"]]></message>
<message level="Debug" culprit="clkctrl">queue size: 0 starting:altclkctrl "submodules/clkctrl_altclkctrl_0"</message>
<message level="Info" culprit="altclkctrl_0">Generating top-level entity clkctrl_altclkctrl_0.</message>
<message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/.</message>
<message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkctrl</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altclkctrl:19.1:CLOCK_TYPE=1,DEVICE_FAMILY=MAX 10,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false"
instancePathKey="clkctrl:.:altclkctrl_0"
kind="altclkctrl"
version="19.1"
name="clkctrl_altclkctrl_0">
<parameter name="NUMBER_OF_CLOCKS" value="1" />
<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
<parameter name="GUI_USE_ENA" value="false" />
<parameter name="DEVICE_FAMILY" value="MAX 10" />
<parameter name="ENA_REGISTER_MODE" value="1" />
<parameter name="CLOCK_TYPE" value="1" />
<generatedFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v"
type="VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="clkctrl" as="altclkctrl_0" />
<messages>
<message level="Debug" culprit="clkctrl">queue size: 0 starting:altclkctrl "submodules/clkctrl_altclkctrl_0"</message>
<message level="Info" culprit="altclkctrl_0">Generating top-level entity clkctrl_altclkctrl_0.</message>
<message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/.</message>
<message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkctrl</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
</messages>
</entity>
</deploy>

339
FPGA_firmware/clkctrl/synthesis/clkctrl.debuginfo
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@ -1,339 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="clkctrl" kind="system" version="19.1" fabric="QSYS">
<!-- Format version 19.1 670 (Future versions may contain additional information.) -->
<!-- 2023.06.07.19:47:52 -->
<!-- A collection of modules and connections -->
<parameter name="clockCrossingAdapter">
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
<value>HANDSHAKE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="device">
<type>java.lang.String</type>
<value>10M50DAF484C6GES</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>MAX10FPGA</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceSpeedGrade">
<type>java.lang.String</type>
<value>6</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="fabricMode">
<type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
<value>QSYS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="generationId">
<type>int</type>
<value>1686160072</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="globalResetBus">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="hdlLanguage">
<type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
<value>VERILOG</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="hideFromIPCatalog">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="lockedInterfaceDefinition">
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="maxAdditionalLatency">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="projectName">
<type>java.lang.String</type>
<value>m10_rgmii.qpf</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="sopcBorderPoints">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="systemHash">
<type>long</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="testBenchDutName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="timeStamp">
<type>long</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="useTestBenchNamingPattern">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<module
name="altclkctrl_0"
kind="altclkctrl"
version="19.1"
path="altclkctrl_0">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<parameter name="DEVICE_FAMILY">
<type>java.lang.String</type>
<value>MAX10FPGA</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
</parameter>
<parameter name="CLOCK_TYPE">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="NUMBER_OF_CLOCKS">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="ENA_REGISTER_MODE">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="GUI_USE_ENA">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="altclkctrl_input" kind="conduit_end" version="19.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>ui.blockdiagram.direction</name>
<value>input</value>
</assignment>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>conduit</type>
<isStart>false</isStart>
<port>
<name>inclk</name>
<direction>Input</direction>
<width>1</width>
<role>inclk</role>
</port>
</interface>
<interface name="altclkctrl_output" kind="conduit_end" version="19.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>ui.blockdiagram.direction</name>
<value>output</value>
</assignment>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>conduit</type>
<isStart>false</isStart>
<port>
<name>outclk</name>
<direction>Output</direction>
<width>1</width>
<role>outclk</role>
</port>
</interface>
</module>
<plugin>
<instanceCount>1</instanceCount>
<name>altclkctrl</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>ALTCLKCTRL Intel FPGA IP</displayName>
<version>19.1</version>
</plugin>
<plugin>
<instanceCount>2</instanceCount>
<name>conduit_end</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Conduit</displayName>
<version>19.1</version>
</plugin>
<reportVersion>19.1 670</reportVersion>
<uniqueIdentifier>02424A4180BE0000018896F8DFE3</uniqueIdentifier>
</EnsembleReport>

39
FPGA_firmware/clkctrl/synthesis/clkctrl.qip
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@ -1,39 +0,0 @@
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_TOOL_NAME "Qsys"
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_TOOL_VERSION "19.1"
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "clkctrl" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../clkctrl.sopcinfo"]
set_global_assignment -entity "clkctrl" -library "clkctrl" -name SLD_INFO "QSYS_NAME clkctrl HAS_SOPCINFO 1 GENERATION_ID 1686160072"
set_global_assignment -library "clkctrl" -name MISC_FILE [file join $::quartus(qip_path) "../clkctrl.cmp"]
set_global_assignment -library "clkctrl" -name SLD_FILE [file join $::quartus(qip_path) "clkctrl.debuginfo"]
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_QSYS_MODE "STANDALONE"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "clkctrl" -name MISC_FILE [file join $::quartus(qip_path) "../../clkctrl.qsys"]
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_NAME "Y2xrY3RybA=="
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_DISPLAY_NAME "Y2xrY3RybA=="
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY4NjE2MDA3Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNNTBEQUY0ODRDNkdFUw==::QXV0byBERVZJQ0U="
set_global_assignment -entity "clkctrl" -library "clkctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Ng==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_NAME "Y2xrY3RybF9hbHRjbGtjdHJsXzA="
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_DISPLAY_NAME "QUxUQ0xLQ1RSTCBJbnRlbCBGUEdBIElQ"
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_VERSION "MTkuMQ=="
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIEZhbWlseQ=="
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfVFlQRQ==::MQ==::SG93IGRvIHlvdSB3YW50IHRvIHVzZSB0aGUgQUxUQ0xLQ1RSTD8="
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NMT0NLUw==::MQ==::SG93IG1hbnkgY2xvY2sgaW5wdXRzIHdvdWxkIHlvdSBsaWtlPw=="
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_PARAMETER "R1VJX1VTRV9FTkE=::ZmFsc2U=::Q3JlYXRlICdlbmEnIHBvcnQgdG8gZW5hYmxlIG9yIGRpc2FibGUgdGhlIGNsb2NrIG5ldHdvcmsgZHJpdmVuIGJ5IHRoaXMgYnVmZmVyPw=="
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_COMPONENT_PARAMETER "VVNFX0dMSVRDSF9GUkVFX1NXSVRDSF9PVkVSX0lNUExFTUVOVEFUSU9O::ZmFsc2U=::RW5zdXJlIGdsaXRjaC1mcmVlIHN3aXRjaG92ZXIgaW1wbGVtZW50YXRpb24="
set_global_assignment -library "clkctrl" -name VERILOG_FILE [file join $::quartus(qip_path) "clkctrl.v"]
set_global_assignment -library "clkctrl" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/clkctrl_altclkctrl_0.v"]
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_TOOL_NAME "altclkctrl"
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_TOOL_VERSION "19.1"
set_global_assignment -entity "clkctrl_altclkctrl_0" -library "clkctrl" -name IP_TOOL_ENV "Qsys"

16
FPGA_firmware/clkctrl/synthesis/clkctrl.v
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@ -1,16 +0,0 @@
// clkctrl.v
// Generated using ACDS version 19.1 670
`timescale 1 ps / 1 ps
module clkctrl (
input wire inclk, // altclkctrl_input.inclk
output wire outclk // altclkctrl_output.outclk
);
clkctrl_altclkctrl_0 altclkctrl_0 (
.inclk (inclk), // altclkctrl_input.inclk
.outclk (outclk) // altclkctrl_output.outclk
);
endmodule

115
FPGA_firmware/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v
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@ -1,115 +0,0 @@
//altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="MAX 10" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
//VERSION_BEGIN 19.1 cbx_altclkbuf 2019:09:22:08:02:34:SJ cbx_cycloneii 2019:09:22:08:02:34:SJ cbx_lpm_add_sub 2019:09:22:08:02:34:SJ cbx_lpm_compare 2019:09:22:08:02:34:SJ cbx_lpm_decode 2019:09:22:08:02:34:SJ cbx_lpm_mux 2019:09:22:08:02:34:SJ cbx_mgl 2019:09:22:09:26:20:SJ cbx_nadder 2019:09:22:08:02:34:SJ cbx_stratix 2019:09:22:08:02:34:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_stratixiii 2019:09:22:08:02:34:SJ cbx_stratixv 2019:09:22:08:02:34:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.
//synthesis_resources = clkctrl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module clkctrl_altclkctrl_0_sub
(
ena,
inclk,
outclk) /* synthesis synthesis_clearbox=1 */;
input ena;
input [3:0] inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ena;
tri0 [3:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_clkctrl1_outclk;
wire [1:0] clkselect;
wire [1:0] clkselect_wire;
wire [3:0] inclk_wire;
fiftyfivenm_clkctrl clkctrl1
(
.clkselect(clkselect_wire),
.ena(ena),
.inclk(inclk_wire),
.outclk(wire_clkctrl1_outclk)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
clkctrl1.clock_type = "Global Clock",
clkctrl1.ena_register_mode = "falling edge",
clkctrl1.lpm_type = "fiftyfivenm_clkctrl";
assign
clkselect = {2{1'b0}},
clkselect_wire = {clkselect},
inclk_wire = {inclk},
outclk = wire_clkctrl1_outclk;
endmodule //clkctrl_altclkctrl_0_sub
//VALID FILE // (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clkctrl_altclkctrl_0 (
inclk,
outclk);
input inclk;
output outclk;
wire sub_wire0;
wire outclk;
wire sub_wire1;
wire sub_wire2;
wire [3:0] sub_wire3;
wire [2:0] sub_wire4;
assign outclk = sub_wire0;
assign sub_wire1 = 1'h1;
assign sub_wire2 = inclk;
assign sub_wire3[3:0] = {sub_wire4, sub_wire2};
assign sub_wire4[2:0] = 3'h0;
clkctrl_altclkctrl_0_sub clkctrl_altclkctrl_0_sub_component (
.ena (sub_wire1),
.inclk (sub_wire3),
.outclk (sub_wire0));
endmodule

90
FPGA_firmware/debouncer_testbench.v
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@ -1,90 +0,0 @@
//This is a testbench from the UDP generator
`timescale 1 ns / 1 ns
module debouncer_testbench();
//Signals
reg clk;
reg rst;
reg in;
wire out;
initial
begin
clk = 0;
rst = 1;
in = 0;
#50
rst = 0;
#20
in = 1;
#20
in = 0;
#200
in = 1;
#200
in = 0;
#100
in = 1;
#100
in = 0;
#20
in = 1;
#200
in = 0;
#20
in = 1;
#20
in = 0;
#20
in = 1;
#20
in = 0;
#20
in = 1;
#20
in = 0;
#20
in = 1;
#20
in = 0;
#1000
in = 1;
#500
in = 0;
#20000
$stop;
end
always #5 clk = ~clk;
debouncer #(
.LENGTH (25)
) the_debouncer(
.clk (clk),
.rst (rst),
.in (in),
.out (out)
);
endmodule

0
FPGA_firmware/debug.log
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2
FPGA_firmware/devplatforms/17.1std.1/devkit_simple_socket_server/devkit_simple_socket_server.qp_info
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@ -1,2 +0,0 @@
<platform><name>Nios II Simple Socket Server Ethernet Example</name><category>Design Example</category><version>1.0</version><acds_version>17.1std.1</acds_version><board>MAX 10 FPGA Development Kit</board><family>MAX 10</family><device>10M50DA</device><part>10M50DAF256C7G</part><vendor>Altera</vendor><description>This design example demonstrates communication with a telnet client on a development host PC. The telnet client offers a convenient way of issuing
commands over a TCP/IP socket to the Ethernet-connected NicheStack TCP/IP Stackrunning on the Altera development board with a simple TCP/IP socket server example. The socket server example receives commands sent over a TCP/IP connection and turns LEDs on and off according to the commands. Note that this design uses DDR3 memory and the pinout on the devkit changes based on the revision of your kit. See the MAX 10 dev kit baseline pinout design for a TCL script with the pinout changes between the different revisions of the development kits.</description><documentation><title>Nios II Simple Socket Server Ethernet Guide</title><url>http://www.alterawiki.com/uploads/e/e5/Simple_Socket_Ethernet.pdf</url></documentation><documentation><title>Using the NicheStack TCP/IP Stack - Nios II Tutorial</title><url>https://www.altera.com/en_US/pdfs/literature/tt/tt_nios2_tcpip.pdf</url></documentation></platform>

2
FPGA_firmware/devplatforms/17.1std.1/devkit_simple_socket_server/filelist.txt
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@ -1,2 +0,0 @@
devkit_simple_socket_server.qp_info
devkit_simple_socket_server.qar

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FPGA_firmware/enet_gtx_clk_ddio.xml
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<?xml version="1.0"?>
<instance entity-name="altera_gpio_lite" version="18.0" >
<generic name="DEVICE_FAMILY" value="MAX 10" />
<generic name="PIN_TYPE" value="output" />
<generic name="SIZE" value="1" />
<generic name="gui_true_diff_buf" value="false" />
<generic name="gui_pseudo_diff_buf" value="false" />
<generic name="gui_bus_hold" value="false" />
<generic name="gui_open_drain" value="false" />
<generic name="gui_enable_oe_port" value="false" />
<generic name="gui_enable_nsleep_port" value="false" />
<generic name="gui_io_reg_mode" value="ddr" />
<generic name="gui_enable_aclr_port" value="true" />
<generic name="gui_enable_aset_port" value="false" />
<generic name="gui_enable_sclr_port" value="false" />
<generic name="gui_set_registers_to_power_up_high" value="false" />
<generic name="gui_clock_enable" value="false" />
<generic name="gui_invert_output" value="false" />
<generic name="gui_invert_input_clock" value="false" />
<generic name="gui_use_register_to_drive_obuf_oe" value="false" />
<generic name="gui_use_ddio_reg_to_drive_oe" value="false" />
<generic name="gui_use_advanced_ddr_features" value="false" />
<generic name="gui_enable_phase_detector_for_ck" value="false" />
<generic name="gui_enable_oe_half_cycle_delay" value="true" />
<generic name="gui_enable_hr_clock" value="false" />
<generic name="gui_enable_invert_hr_clock_port" value="false" />
<generic name="gui_invert_clkdiv_input_clock" value="false" />
<generic name="gui_invert_output_clock" value="false" />
<generic name="gui_invert_oe_inclock" value="false" />
<generic name="gui_use_hardened_ddio_input_registers" value="false" />
</instance>

82
FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.bsf
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@ -1,82 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 208 184)
(text "enet_gtx_clk_ddio" (rect 51 -1 122 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 20 180)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "outclock" (rect 0 0 31 12)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 61 52 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 64 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "din[1..0]" (rect 0 0 29 12)(font "Arial" (font_size 8)))
(text "din[1..0]" (rect 4 101 58 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 64 112)(line_width 3))
)
(port
(pt 0 152)
(input)
(text "aclr" (rect 0 0 14 12)(font "Arial" (font_size 8)))
(text "aclr" (rect 4 141 28 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 64 152)(line_width 1))
)
(port
(pt 208 72)
(output)
(text "pad_out" (rect 0 0 31 12)(font "Arial" (font_size 8)))
(text "pad_out" (rect 166 61 208 72)(font "Arial" (font_size 8)))
(line (pt 208 72)(pt 144 72)(line_width 1))
)
(drawing
(text "outclock" (rect 18 43 84 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 69 67 174 144)(font "Arial" (color 0 0 0)))
(text "din" (rect 48 83 114 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 69 107 174 224)(font "Arial" (color 0 0 0)))
(text "pad_out" (rect 145 43 332 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 114 67 264 144)(font "Arial" (color 0 0 0)))
(text "aclr" (rect 44 123 112 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 69 147 174 304)(font "Arial" (color 0 0 0)))
(text " altera_gpio_lite " (rect 140 168 388 346)(font "Arial" ))
(line (pt 64 32)(pt 144 32)(line_width 1))
(line (pt 144 32)(pt 144 168)(line_width 1))
(line (pt 64 168)(pt 144 168)(line_width 1))
(line (pt 64 32)(pt 64 168)(line_width 1))
(line (pt 65 52)(pt 65 76)(line_width 1))
(line (pt 66 52)(pt 66 76)(line_width 1))
(line (pt 65 92)(pt 65 116)(line_width 1))
(line (pt 66 92)(pt 66 116)(line_width 1))
(line (pt 143 52)(pt 143 76)(line_width 1))
(line (pt 142 52)(pt 142 76)(line_width 1))
(line (pt 65 132)(pt 65 156)(line_width 1))
(line (pt 66 132)(pt 66 156)(line_width 1))
(line (pt 0 0)(pt 208 0)(line_width 1))
(line (pt 208 0)(pt 208 184)(line_width 1))
(line (pt 0 184)(pt 208 184)(line_width 1))
(line (pt 0 0)(pt 0 184)(line_width 1))
)
)

74
FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.qip
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@ -1,74 +0,0 @@
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_TOOL_NAME "altera_gpio_lite"
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_TOOL_VERSION "19.1"
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "enet_gtx_clk_ddio" -name MISC_FILE [file join $::quartus(qip_path) "enet_gtx_clk_ddio.cmp"]
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_QSYS_MODE "UNKNOWN"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_NAME "ZW5ldF9ndHhfY2xrX2RkaW8="
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_VERSION "MTkuMQ=="
set_global_assignment -entity "enet_gtx_clk_ddio" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW9fbGl0ZQ=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_VERSION "MTkuMQ=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::b3V0cHV0::RGF0YSBkaXJlY3Rpb24="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "U0laRQ==::MQ==::RGF0YSB3aWR0aA=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX3RydWVfZGlmZl9idWY=::ZmFsc2U=::VXNlIHRydWUgZGlmZmVyZW50aWFsIGJ1ZmZlcg=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzZXVkb19kaWZmX2J1Zg==::ZmFsc2U=::VXNlIHBzZXVkbyBkaWZmZXJlbnRpYWwgYnVmZmVy"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2J1c19ob2xk::ZmFsc2U=::VXNlIGJ1cy1ob2xkIGNpcmN1aXRyeQ=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX29wZW5fZHJhaW4=::ZmFsc2U=::VXNlIG9wZW4gZHJhaW4gb3V0cHV0"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9wb3J0::ZmFsc2U=::RW5hYmxlIG9lIHBvcnQ="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2lvX3JlZ19tb2Rl::ZGRy::UmVnaXN0ZXIgbW9kZQ=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9hY2xyX3BvcnQ=::dHJ1ZQ==::RW5hYmxlIGFjbHIgcG9ydA=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nsb2NrX2VuYWJsZQ==::ZmFsc2U=::RW5hYmxlIGluY2xvY2tlbi9vdXRjbG9ja2VuIHBvcnRz"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXQ=::ZmFsc2U=::SW52ZXJ0IGRpbg=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9yZWdpc3Rlcl90b19kcml2ZV9vYnVmX29l::ZmFsc2U=::VXNlIGEgc2luZ2xlIHJlZ2lzdGVyIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9kZGlvX3JlZ190b19kcml2ZV9vZQ==::ZmFsc2U=::VXNlIERESU8gcmVnaXN0ZXJzIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hZHZhbmNlZF9kZHJfZmVhdHVyZXM=::ZmFsc2U=::RW5hYmxlIGFkdmFuY2VkIEREUiBmZWF0dXJlcw=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9waGFzZV9kZXRlY3Rvcl9mb3JfY2s=::ZmFsc2U=::RW5hYmxlIFBoYXNlIERldGVjdG9yIGZyb20gQ0sgbG9vcGJhY2sgc2lnbmFs"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9oYWxmX2N5Y2xlX2RlbGF5::dHJ1ZQ==::QWRkIGhhbGYtY3ljbGUgZGVsYXkgdG8gT0Ugc2lnbmFs"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9ocl9jbG9jaw==::ZmFsc2U=::RW5hYmxlIGhhbGYtcmF0ZSBjbG9jayBwb3J0"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9pbnZlcnRfaHJfY2xvY2tfcG9ydA==::ZmFsc2U=::RW5hYmxlIGludmVydF9ocl9jbG9jayBwb3J0"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9jbGtkaXZfaW5wdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IGNsb2NrIGRpdmlkZXIgaW5wdXQgY2xvY2s="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IERESU8gb3V0Y2xvY2s="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vZV9pbmNsb2Nr::ZmFsc2U=::SW52ZXJ0IG91dHB1dCBlbmFibGUgKG9lKSByZWdpc3RlciBpbmNsb2Nr"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfTU9ERQ==::ZGRy::UkVHSVNURVJfTU9ERQ=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "QlVGRkVSX1RZUEU=::c2luZ2xlLWVuZGVk::QlVGRkVSX1RZUEU="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "QVNZTkNfTU9ERQ==::Y2xlYXI=::QVNZTkNfTU9ERQ=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "U1lOQ19NT0RF::bm9uZQ==::U1lOQ19NT0RF"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "QlVTX0hPTEQ=::ZmFsc2U=::QlVTX0hPTEQ="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "T1BFTl9EUkFJTl9PVVRQVVQ=::ZmFsc2U=::T1BFTl9EUkFJTl9PVVRQVVQ="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX1BPUlQ=::ZmFsc2U=::RU5BQkxFX09FX1BPUlQ="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05TTEVFUF9QT1JU::ZmFsc2U=::RU5BQkxFX05TTEVFUF9QT1JU"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMT0NLX0VOQV9QT1JU::ZmFsc2U=::RU5BQkxFX0NMT0NLX0VOQV9QT1JU"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA==::ZmFsc2U=::U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVA==::ZmFsc2U=::SU5WRVJUX09VVFBVVA=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0lOUFVUX0NMT0NL::ZmFsc2U=::SU5WRVJUX0lOUFVUX0NMT0NL"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U=::ZmFsc2U=::VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F::ZmFsc2U=::VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk=::dHJ1ZQ==::RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ=::ZmFsc2U=::RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0hSX0NMT0NL::ZmFsc2U=::RU5BQkxFX0hSX0NMT0NL"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX09VVFBVVF9DTE9DSw=="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09FX0lOQ0xPQ0s=::ZmFsc2U=::SU5WRVJUX09FX0lOQ0xPQ0s="
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw==::ZmFsc2U=::RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw=="
set_global_assignment -library "enet_gtx_clk_ddio" -name VERILOG_FILE [file join $::quartus(qip_path) "enet_gtx_clk_ddio.v"]
set_global_assignment -library "enet_gtx_clk_ddio" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "enet_gtx_clk_ddio/altera_gpio_lite.sv"]
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_TOOL_NAME "altera_gpio_lite"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_TOOL_VERSION "19.1"
set_global_assignment -entity "altera_gpio_lite" -library "enet_gtx_clk_ddio" -name IP_TOOL_ENV "mwpim"

7
FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.sip
View File

@ -1,7 +0,0 @@
set_global_assignment -entity "enet_gtx_clk_ddio" -library "lib_enet_gtx_clk_ddio" -name IP_TOOL_NAME "altera_gpio_lite"
set_global_assignment -entity "enet_gtx_clk_ddio" -library "lib_enet_gtx_clk_ddio" -name IP_TOOL_VERSION "19.1"
set_global_assignment -entity "enet_gtx_clk_ddio" -library "lib_enet_gtx_clk_ddio" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "lib_enet_gtx_clk_ddio" -name SPD_FILE [file join $::quartus(sip_path) "enet_gtx_clk_ddio.spd"]
set_global_assignment -library "lib_enet_gtx_clk_ddio" -name MISC_FILE [file join $::quartus(sip_path) "enet_gtx_clk_ddio_sim/enet_gtx_clk_ddio.v"]
set_global_assignment -library "lib_enet_gtx_clk_ddio" -name MISC_FILE [file join $::quartus(sip_path) "enet_gtx_clk_ddio_sim/altera_gpio_lite/altera_gpio_lite.sv"]

10
FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.spd
View File

@ -1,10 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="enet_gtx_clk_ddio_sim/altera_gpio_lite/altera_gpio_lite.sv"
type="SYSTEM_VERILOG"
library="enet_gtx_clk_ddio" />
<file path="enet_gtx_clk_ddio_sim/enet_gtx_clk_ddio.v" type="VERILOG" />
<topLevel name="enet_gtx_clk_ddio" />
<deviceFamily name="max10" />
</simPackage>

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FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio.v
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// megafunction wizard: %GPIO Lite Intel FPGA IP v19.1%
// GENERATION: XML
// enet_gtx_clk_ddio.v
// Generated using ACDS version 19.1 670
`timescale 1 ps / 1 ps
module enet_gtx_clk_ddio (
input wire outclock, // outclock.export
input wire [1:0] din, // din.export
output wire [0:0] pad_out, // pad_out.export
input wire aclr // aclr.export
);
altera_gpio_lite #(
.PIN_TYPE ("output"),
.SIZE (1),
.REGISTER_MODE ("ddr"),
.BUFFER_TYPE ("single-ended"),
.ASYNC_MODE ("clear"),
.SYNC_MODE ("none"),
.BUS_HOLD ("false"),
.OPEN_DRAIN_OUTPUT ("false"),
.ENABLE_OE_PORT ("false"),
.ENABLE_NSLEEP_PORT ("false"),
.ENABLE_CLOCK_ENA_PORT ("false"),
.SET_REGISTER_OUTPUTS_HIGH ("false"),
.INVERT_OUTPUT ("false"),
.INVERT_INPUT_CLOCK ("false"),
.USE_ONE_REG_TO_DRIVE_OE ("false"),
.USE_DDIO_REG_TO_DRIVE_OE ("false"),
.USE_ADVANCED_DDR_FEATURES ("false"),
.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
.ENABLE_OE_HALF_CYCLE_DELAY ("true"),
.INVERT_CLKDIV_INPUT_CLOCK ("false"),
.ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
.ENABLE_HR_CLOCK ("false"),
.INVERT_OUTPUT_CLOCK ("false"),
.INVERT_OE_INCLOCK ("false"),
.ENABLE_PHASE_DETECTOR_FOR_CK ("false")
) enet_gtx_clk_ddio_inst (
.outclock (outclock), // outclock.export
.din (din), // din.export
.pad_out (pad_out), // pad_out.export
.aclr (aclr), // aclr.export
.outclocken (1'b1), // (terminated)
.inclock (1'b0), // (terminated)
.inclocken (1'b0), // (terminated)
.fr_clock (), // (terminated)
.hr_clock (), // (terminated)
.invert_hr_clock (1'b0), // (terminated)
.phy_mem_clock (1'b0), // (terminated)
.mimic_clock (), // (terminated)
.dout (), // (terminated)
.pad_io (), // (terminated)
.pad_io_b (), // (terminated)
.pad_in (1'b0), // (terminated)
.pad_in_b (1'b0), // (terminated)
.pad_out_b (), // (terminated)
.aset (1'b0), // (terminated)
.sclr (1'b0), // (terminated)
.nsleep (1'b0), // (terminated)
.oe (1'b0) // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2023 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_gpio_lite" version="19.1" >
// Retrieval info: <generic name="DEVICE_FAMILY" value="MAX 10" />
// Retrieval info: <generic name="PIN_TYPE" value="output" />
// Retrieval info: <generic name="SIZE" value="1" />
// Retrieval info: <generic name="gui_true_diff_buf" value="false" />
// Retrieval info: <generic name="gui_pseudo_diff_buf" value="false" />
// Retrieval info: <generic name="gui_bus_hold" value="false" />
// Retrieval info: <generic name="gui_open_drain" value="false" />
// Retrieval info: <generic name="gui_enable_oe_port" value="false" />
// Retrieval info: <generic name="gui_enable_nsleep_port" value="false" />
// Retrieval info: <generic name="gui_io_reg_mode" value="ddr" />
// Retrieval info: <generic name="gui_enable_aclr_port" value="true" />
// Retrieval info: <generic name="gui_enable_aset_port" value="false" />
// Retrieval info: <generic name="gui_enable_sclr_port" value="false" />
// Retrieval info: <generic name="gui_set_registers_to_power_up_high" value="false" />
// Retrieval info: <generic name="gui_clock_enable" value="false" />
// Retrieval info: <generic name="gui_invert_output" value="false" />
// Retrieval info: <generic name="gui_invert_input_clock" value="false" />
// Retrieval info: <generic name="gui_use_register_to_drive_obuf_oe" value="false" />
// Retrieval info: <generic name="gui_use_ddio_reg_to_drive_oe" value="false" />
// Retrieval info: <generic name="gui_use_advanced_ddr_features" value="false" />
// Retrieval info: <generic name="gui_enable_phase_detector_for_ck" value="false" />
// Retrieval info: <generic name="gui_enable_oe_half_cycle_delay" value="true" />
// Retrieval info: <generic name="gui_enable_hr_clock" value="false" />
// Retrieval info: <generic name="gui_enable_invert_hr_clock_port" value="false" />
// Retrieval info: <generic name="gui_invert_clkdiv_input_clock" value="false" />
// Retrieval info: <generic name="gui_invert_output_clock" value="false" />
// Retrieval info: <generic name="gui_invert_oe_inclock" value="false" />
// Retrieval info: <generic name="gui_use_hardened_ddio_input_registers" value="false" />
// Retrieval info: </instance>
// IPFS_FILES : enet_gtx_clk_ddio.vo
// RELATED_FILES: enet_gtx_clk_ddio.v, altera_gpio_lite.sv

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FPGA_firmware/enet_gtx_clk_ddio/enet_gtx_clk_ddio_sim.f
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enet_gtx_clk_ddio_sim/enet_gtx_clk_ddio.v
enet_gtx_clk_ddio_sim/altera_gpio_lite/altera_gpio_lite.sv

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
# Date created = 13:50:14 June 05, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.0"
DATE = "13:50:14 June 05, 2019"
# Revisions
PROJECT_REVISION = "hit20v3"

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FPGA_firmware/hit20v3.qsf
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@ -664,5 +664,5 @@ set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SLD_FILE db/stp2_auto_stripped.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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FPGA_firmware/hit20v3_assignment_defaults.qdf
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@ -1,807 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
# Date created = 13:50:18 June 05, 2019
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus Prime software and is used
# to preserve global assignments across Quartus Prime versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
set_global_assignment -name IP_COMPONENT_INTERNAL Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name OPTIMIZATION_MODE Balanced
set_global_assignment -name ALLOW_REGISTER_MERGING On
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
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set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name OCP_HW_EVAL -value OFF
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY -value "Cyclone V"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
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set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
set_global_assignment -name PRPOF_ID Off
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name PHYSICAL_SYNTHESIS Off
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
set_global_assignment -name USE_CONF_DONE AUTO
set_global_assignment -name USE_PWRMGT_SCL AUTO
set_global_assignment -name USE_PWRMGT_SDA AUTO
set_global_assignment -name USE_PWRMGT_ALERT AUTO
set_global_assignment -name USE_INIT_DONE AUTO
set_global_assignment -name USE_CVP_CONFDONE AUTO
set_global_assignment -name USE_SEU_ERROR AUTO
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
set_global_assignment -name ENABLE_NCE_PIN Off
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name RESERVE_PR_PINS Off
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
set_global_assignment -name SEU_FIT_REPORT Off
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
set_global_assignment -name POR_SCHEME "Instant ON"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
set_global_assignment -name POF_VERIFY_PROTECT Off
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name GENERATE_PMSF_FILES On
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

1145
FPGA_firmware/hit20v3_test.out.sdc
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File diff suppressed because it is too large Load Diff

1
FPGA_firmware/m10_rgmii.out.sdc
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@ -1,5 +1,6 @@
#**************************************************************
# Create Clock
# modified by LQ.Qin for DDR3 clock
#**************************************************************
# RX clock, 125 MHz - M.D. 2019.10.07

5
FPGA_firmware/m10_rgmii.v
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@ -1,3 +1,8 @@
/*
created by M.Dziwiecki in 2019
modified by Lq.Qin in 2024 for reconstruction signal position and FWHM
*/
module m10_rgmii (
//Clock and Reset
input wire clk_50_max10,

24
FPGA_firmware/output_file_sum.map
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@ -1,24 +0,0 @@
BLOCK START ADDRESS END ADDRESS
ICB 0x00000000 0x00001FFF
UFM 0x00002000 0x00071FFF
CFM0 0x00072000 0x00161FFF (0x0014BA6B)
Max 10 Setting:
EPOF: OFF
Verify protect: OFF
Watchdog value: Not activated
Configure device from CFM0 only: OFF
POR: Instant ON
IO Pullup: ON
SPI IO Pullup: ON
Notes:
- Data checksum for this conversion is 0x0753386E
- All the addresses in this file are byte addresses

2
FPGA_firmware/output_files/.qsys_edit/filters.xml
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<?xml version="1.0" encoding="UTF-8"?>
<filters version="19.1" />

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FPGA_firmware/output_files/.qsys_edit/preferences.xml
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<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<debug showDebugMenu="0" />
<systemtable filter="All Interfaces">
<columns>
<connections preferredWidth="47" />
<irq preferredWidth="34" />
<inputclock preferredWidth="170" />
<name preferredWidth="186" />
</columns>
</systemtable>
<library expandedCategories="Library,Project" />
<window width="1920" height="1017" x="0" y="23" />
<hdlexample language="VERILOG" />
</preferences>

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FPGA_firmware/output_files/ChainFlash.cdf
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/* Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Ign)
Device PartName(10M50DAF484ES) MfrSpec(OpMask(0) SEC_Device(QSPI_512MB) Child_OpMask(2 0 1) PFLPath("/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/output_files/flash/ext_flash.pof"));
P ActionCode(Ign)
Device PartName(VTAP10) MfrSpec(OpMask(0));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

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FPGA_firmware/output_files/flash/ext_flash.pof
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BIN
FPGA_firmware/output_files/flash/flash_loader.sof
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FPGA_firmware/output_files/hit20v3.cdf
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/* Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Ign)
Device PartName(10M50DAF484ES) MfrSpec(OpMask(0) SEC_Device(QSPI_512MB) Child_OpMask(1 0));
P ActionCode(Ign)
Device PartName(VTAP10) MfrSpec(OpMask(0));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

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FPGA_firmware/output_files/hit20v3.pof
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FPGA_firmware/output_files/hit20v3.sld
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<sld_project_info>
<sld_infos>
<sld_info hpath="clkctrl:clkctrl_inst0" name="clkctrl_inst0">
<assignment_values>
<assignment_value text="QSYS_NAME clkctrl HAS_SOPCINFO 1 GENERATION_ID 1686160072"/>
</assignment_values>
</sld_info>
<sld_info hpath="clkctrl:clkctrl_inst1" name="clkctrl_inst1">
<assignment_values>
<assignment_value text="QSYS_NAME clkctrl HAS_SOPCINFO 1 GENERATION_ID 1686160072"/>
</assignment_values>
</sld_info>
<sld_info hpath="q_sys:q_sys_inst" name="q_sys_inst">
<assignment_values>
<assignment_value text="QSYS_NAME q_sys HAS_SOPCINFO 1 GENERATION_ID 1728634208"/>
</assignment_values>
</sld_info>
<sld_info hpath="sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:instrumentation_fabric" library="alt_sld_fab" name="instrumentation_fabric">
<assignment_values>
<assignment_value text="QSYS_NAME alt_sld_fab HAS_SOPCINFO 1"/>
</assignment_values>
</sld_info>
</sld_infos>
</sld_project_info>

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FPGA_firmware/output_files/hit20v3.sof
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BIN
FPGA_firmware/output_files/hit20v3_bkgsub.pof
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FPGA_firmware/output_files/hit20v3_time_limited.sof
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FPGA_firmware/output_files/stp2.stp
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<session jtag_chain="USB-BlasterII on 147.142.18.133 [USB-1]" jtag_device="@1: 10M50DA(.|ES)/10M50DC (0x031050DD)" sof_file="hit20v3.sof">
<display_tree gui_logging_enabled="0">
<display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
</display_tree>
<instance enabled="true" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
<node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
<position_info>
<single attribute="active tab" value="1"/>
<single attribute="data horizontal scroll position" value="480"/>
<single attribute="data vertical scroll position" value="0"/>
<single attribute="setup hierarchy algo_top_cl_cali_rms:recon" value="3"/>
<single attribute="setup hierarchy bkg_subtraction_pipe:bkg_subtraction0" value="3"/>
<single attribute="setup hierarchy m10_rgmii" value="3"/>
<single attribute="setup hierarchy q_sys:q_sys_inst" value="3"/>
<single attribute="setup hierarchy q_sys_calibration_ram:calibration_ram" value="3"/>
<single attribute="setup hierarchy sensor_algo:sensor_interface" value="3"/>
<single attribute="setup horizontal scroll position" value="0"/>
<single attribute="setup vertical scroll position" value="0"/>
<single attribute="zoom level denominator" value="1"/>
<single attribute="zoom level numerator" value="32"/>
<single attribute="zoom offset denominator" value="1"/>
<single attribute="zoom offset numerator" value="4080"/>
</position_info>
<signal_set global_temp="1" name="signal_set: 2024/07/25 16:46:53 #0">
<clock name="ddr3_ram_pll_ref_clk_clk" polarity="posedge" tap_mode="classic"/>
<config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="2048" trigger_in_enable="no" trigger_out_enable="no"/>
<top_entity/>
<signal_vec>
<trigger_input_vec>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" tap_mode="classic"/>
</trigger_input_vec>
<data_input_vec>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" tap_mode="classic"/>
</data_input_vec>
<storage_qualifier_input_vec>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" tap_mode="classic"/>
<wire name="q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" tap_mode="classic"/>
</storage_qualifier_input_vec>
</signal_vec>
<presentation>
<unified_setup_data_view>
<node data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="32" type="unknown"/>
<node data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" storage_index="137" tap_mode="classic" type="unknown"/>
<node data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" storage_index="139" tap_mode="classic" type="unknown"/>
<node data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" storage_index="138" tap_mode="classic" type="unknown"/>
<node data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" storage_index="136" tap_mode="classic" trigger_index="1" type="unknown"/>
<node data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" storage_index="125" tap_mode="classic" trigger_index="0" type="unknown"/>
<node data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" storage_index="126" tap_mode="classic" type="unknown"/>
<node data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" storage_index="124" tap_mode="classic" type="unknown"/>
<node data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" storage_index="107" tap_mode="classic" type="unknown"/>
<node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8..0]" order="msb_to_lsb" type="combinatorial">
<node data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" storage_index="74" tap_mode="classic" type="unknown"/>
<node data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" storage_index="73" tap_mode="classic" type="unknown"/>
<node data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" storage_index="72" tap_mode="classic" type="unknown"/>
<node data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" storage_index="71" tap_mode="classic" type="unknown"/>
<node data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" storage_index="70" tap_mode="classic" type="unknown"/>
<node data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" storage_index="69" tap_mode="classic" type="unknown"/>
<node data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" storage_index="68" tap_mode="classic" type="unknown"/>
<node data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" storage_index="67" tap_mode="classic" type="unknown"/>
<node data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" storage_index="66" tap_mode="classic" type="unknown"/>
</node>
<node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31..0]" order="msb_to_lsb" type="combinatorial">
<node data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" storage_index="99" tap_mode="classic" type="unknown"/>
<node data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" storage_index="98" tap_mode="classic" type="unknown"/>
<node data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" storage_index="96" tap_mode="classic" type="unknown"/>
<node data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" storage_index="95" tap_mode="classic" type="unknown"/>
<node data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" storage_index="94" tap_mode="classic" type="unknown"/>
<node data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" storage_index="93" tap_mode="classic" type="unknown"/>
<node data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" storage_index="92" tap_mode="classic" type="unknown"/>
<node data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" storage_index="91" tap_mode="classic" type="unknown"/>
<node data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" storage_index="90" tap_mode="classic" type="unknown"/>
<node data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" storage_index="89" tap_mode="classic" type="unknown"/>
<node data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" storage_index="88" tap_mode="classic" type="unknown"/>
<node data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" storage_index="87" tap_mode="classic" type="unknown"/>
<node data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" storage_index="85" tap_mode="classic" type="unknown"/>
<node data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" storage_index="84" tap_mode="classic" type="unknown"/>
<node data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" storage_index="83" tap_mode="classic" type="unknown"/>
<node data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" storage_index="82" tap_mode="classic" type="unknown"/>
<node data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" storage_index="81" tap_mode="classic" type="unknown"/>
<node data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" storage_index="80" tap_mode="classic" type="unknown"/>
<node data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" storage_index="79" tap_mode="classic" type="unknown"/>
<node data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" storage_index="78" tap_mode="classic" type="unknown"/>
<node data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" storage_index="77" tap_mode="classic" type="unknown"/>
<node data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" storage_index="76" tap_mode="classic" type="unknown"/>
<node data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" storage_index="106" tap_mode="classic" type="unknown"/>
<node data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" storage_index="105" tap_mode="classic" type="unknown"/>
<node data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" storage_index="104" tap_mode="classic" type="unknown"/>
<node data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" storage_index="103" tap_mode="classic" type="unknown"/>
<node data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" storage_index="102" tap_mode="classic" type="unknown"/>
<node data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" storage_index="101" tap_mode="classic" type="unknown"/>
<node data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" storage_index="100" tap_mode="classic" type="unknown"/>
<node data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" storage_index="97" tap_mode="classic" type="unknown"/>
<node data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" storage_index="86" tap_mode="classic" type="unknown"/>
<node data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" storage_index="75" tap_mode="classic" type="unknown"/>
</node>
<node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15..0]" order="msb_to_lsb" type="combinatorial">
<node data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" storage_index="114" tap_mode="classic" type="unknown"/>
<node data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" storage_index="113" tap_mode="classic" type="unknown"/>
<node data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" storage_index="112" tap_mode="classic" type="unknown"/>
<node data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" storage_index="111" tap_mode="classic" type="unknown"/>
<node data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" storage_index="110" tap_mode="classic" type="unknown"/>
<node data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" storage_index="109" tap_mode="classic" type="unknown"/>
<node data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" storage_index="123" tap_mode="classic" type="unknown"/>
<node data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" storage_index="122" tap_mode="classic" type="unknown"/>
<node data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" storage_index="121" tap_mode="classic" type="unknown"/>
<node data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" storage_index="120" tap_mode="classic" type="unknown"/>
<node data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" storage_index="119" tap_mode="classic" type="unknown"/>
<node data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" storage_index="118" tap_mode="classic" type="unknown"/>
<node data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" storage_index="117" tap_mode="classic" type="unknown"/>
<node data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" storage_index="116" tap_mode="classic" type="unknown"/>
<node data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" storage_index="115" tap_mode="classic" type="unknown"/>
<node data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" storage_index="108" tap_mode="classic" type="unknown"/>
</node>
<node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8..0]" order="msb_to_lsb" type="register">
<node data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" storage_index="135" tap_mode="classic" type="unknown"/>
<node data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" storage_index="134" tap_mode="classic" type="unknown"/>
<node data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" storage_index="133" tap_mode="classic" type="unknown"/>
<node data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" storage_index="132" tap_mode="classic" type="unknown"/>
<node data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" storage_index="131" tap_mode="classic" type="unknown"/>
<node data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" storage_index="130" tap_mode="classic" type="unknown"/>
<node data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" storage_index="129" tap_mode="classic" type="unknown"/>
<node data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" storage_index="128" tap_mode="classic" type="unknown"/>
<node data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" storage_index="127" tap_mode="classic" type="unknown"/>
</node>
<node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8..0]" order="msb_to_lsb" type="register">
<node data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" storage_index="33" tap_mode="classic" type="unknown"/>
<node data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" storage_index="32" tap_mode="classic" type="unknown"/>
<node data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" storage_index="31" tap_mode="classic" type="unknown"/>
<node data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" storage_index="30" tap_mode="classic" type="unknown"/>
<node data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" storage_index="29" tap_mode="classic" type="unknown"/>
<node data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" storage_index="28" tap_mode="classic" type="unknown"/>
<node data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" storage_index="27" tap_mode="classic" type="unknown"/>
<node data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" storage_index="26" tap_mode="classic" type="unknown"/>
<node data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" storage_index="25" tap_mode="classic" type="unknown"/>
</node>
<node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31..0]" order="msb_to_lsb" type="register">
<node data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" storage_index="58" tap_mode="classic" type="unknown"/>
<node data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" storage_index="57" tap_mode="classic" type="unknown"/>
<node data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" storage_index="55" tap_mode="classic" type="unknown"/>
<node data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" storage_index="54" tap_mode="classic" type="unknown"/>
<node data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" storage_index="53" tap_mode="classic" type="unknown"/>
<node data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" storage_index="52" tap_mode="classic" type="unknown"/>
<node data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" storage_index="51" tap_mode="classic" type="unknown"/>
<node data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" storage_index="50" tap_mode="classic" type="unknown"/>
<node data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" storage_index="49" tap_mode="classic" type="unknown"/>
<node data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" storage_index="48" tap_mode="classic" type="unknown"/>
<node data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" storage_index="47" tap_mode="classic" type="unknown"/>
<node data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" storage_index="46" tap_mode="classic" type="unknown"/>
<node data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" storage_index="44" tap_mode="classic" type="unknown"/>
<node data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" storage_index="43" tap_mode="classic" type="unknown"/>
<node data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" storage_index="42" tap_mode="classic" type="unknown"/>
<node data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" storage_index="41" tap_mode="classic" type="unknown"/>
<node data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" storage_index="40" tap_mode="classic" type="unknown"/>
<node data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" storage_index="39" tap_mode="classic" type="unknown"/>
<node data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" storage_index="38" tap_mode="classic" type="unknown"/>
<node data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" storage_index="37" tap_mode="classic" type="unknown"/>
<node data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" storage_index="36" tap_mode="classic" type="unknown"/>
<node data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" storage_index="35" tap_mode="classic" type="unknown"/>
<node data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" storage_index="65" tap_mode="classic" type="unknown"/>
<node data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" storage_index="64" tap_mode="classic" type="unknown"/>
<node data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" storage_index="63" tap_mode="classic" type="unknown"/>
<node data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" storage_index="62" tap_mode="classic" type="unknown"/>
<node data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" storage_index="61" tap_mode="classic" type="unknown"/>
<node data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" storage_index="60" tap_mode="classic" type="unknown"/>
<node data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" storage_index="59" tap_mode="classic" type="unknown"/>
<node data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" storage_index="56" tap_mode="classic" type="unknown"/>
<node data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" storage_index="45" tap_mode="classic" type="unknown"/>
<node data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" storage_index="34" tap_mode="classic" type="unknown"/>
</node>
<node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15..0]" order="msb_to_lsb" type="combinatorial">
<node data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" storage_index="6" tap_mode="classic" type="unknown"/>
<node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" storage_index="5" tap_mode="classic" type="unknown"/>
<node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" storage_index="4" tap_mode="classic" type="unknown"/>
<node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" storage_index="3" tap_mode="classic" type="unknown"/>
<node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" storage_index="2" tap_mode="classic" type="unknown"/>
<node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" storage_index="1" tap_mode="classic" type="unknown"/>
<node data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" storage_index="15" tap_mode="classic" type="unknown"/>
<node data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" storage_index="14" tap_mode="classic" type="unknown"/>
<node data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" storage_index="13" tap_mode="classic" type="unknown"/>
<node data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" storage_index="12" tap_mode="classic" type="unknown"/>
<node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" storage_index="11" tap_mode="classic" type="unknown"/>
<node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" storage_index="10" tap_mode="classic" type="unknown"/>
<node data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" storage_index="9" tap_mode="classic" type="unknown"/>
<node data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" storage_index="8" tap_mode="classic" type="unknown"/>
<node data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" storage_index="7" tap_mode="classic" type="unknown"/>
<node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" storage_index="0" tap_mode="classic" type="unknown"/>
</node>
<node is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8..0]" order="msb_to_lsb" type="register">
<node data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" storage_index="24" tap_mode="classic" type="unknown"/>
<node data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" storage_index="23" tap_mode="classic" type="unknown"/>
<node data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" storage_index="22" tap_mode="classic" type="unknown"/>
<node data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" storage_index="21" tap_mode="classic" type="unknown"/>
<node data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" storage_index="20" tap_mode="classic" type="unknown"/>
<node data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" storage_index="19" tap_mode="classic" type="unknown"/>
<node data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" storage_index="18" tap_mode="classic" type="unknown"/>
<node data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" storage_index="17" tap_mode="classic" type="unknown"/>
<node data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" storage_index="16" tap_mode="classic" type="unknown"/>
</node>
</unified_setup_data_view>
<data_view>
<net data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="32" type="unknown"/>
<net data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" storage_index="137" tap_mode="classic" type="unknown"/>
<net data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" storage_index="139" tap_mode="classic" type="unknown"/>
<net data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" storage_index="138" tap_mode="classic" type="unknown"/>
<net data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" storage_index="136" tap_mode="classic" trigger_index="1" type="unknown"/>
<net data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" storage_index="125" tap_mode="classic" trigger_index="0" type="unknown"/>
<net data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" storage_index="126" tap_mode="classic" type="unknown"/>
<net data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" storage_index="124" tap_mode="classic" type="unknown"/>
<net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" storage_index="107" tap_mode="classic" type="unknown"/>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8..0]" order="msb_to_lsb" type="combinatorial">
<net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" storage_index="74" tap_mode="classic" type="unknown"/>
<net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" storage_index="73" tap_mode="classic" type="unknown"/>
<net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" storage_index="72" tap_mode="classic" type="unknown"/>
<net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" storage_index="71" tap_mode="classic" type="unknown"/>
<net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" storage_index="70" tap_mode="classic" type="unknown"/>
<net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" storage_index="69" tap_mode="classic" type="unknown"/>
<net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" storage_index="68" tap_mode="classic" type="unknown"/>
<net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" storage_index="67" tap_mode="classic" type="unknown"/>
<net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" storage_index="66" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31..0]" order="msb_to_lsb" type="combinatorial">
<net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" storage_index="99" tap_mode="classic" type="unknown"/>
<net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" storage_index="98" tap_mode="classic" type="unknown"/>
<net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" storage_index="96" tap_mode="classic" type="unknown"/>
<net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" storage_index="95" tap_mode="classic" type="unknown"/>
<net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" storage_index="94" tap_mode="classic" type="unknown"/>
<net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" storage_index="93" tap_mode="classic" type="unknown"/>
<net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" storage_index="92" tap_mode="classic" type="unknown"/>
<net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" storage_index="91" tap_mode="classic" type="unknown"/>
<net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" storage_index="90" tap_mode="classic" type="unknown"/>
<net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" storage_index="89" tap_mode="classic" type="unknown"/>
<net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" storage_index="88" tap_mode="classic" type="unknown"/>
<net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" storage_index="87" tap_mode="classic" type="unknown"/>
<net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" storage_index="85" tap_mode="classic" type="unknown"/>
<net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" storage_index="84" tap_mode="classic" type="unknown"/>
<net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" storage_index="83" tap_mode="classic" type="unknown"/>
<net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" storage_index="82" tap_mode="classic" type="unknown"/>
<net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" storage_index="81" tap_mode="classic" type="unknown"/>
<net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" storage_index="80" tap_mode="classic" type="unknown"/>
<net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" storage_index="79" tap_mode="classic" type="unknown"/>
<net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" storage_index="78" tap_mode="classic" type="unknown"/>
<net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" storage_index="77" tap_mode="classic" type="unknown"/>
<net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" storage_index="76" tap_mode="classic" type="unknown"/>
<net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" storage_index="106" tap_mode="classic" type="unknown"/>
<net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" storage_index="105" tap_mode="classic" type="unknown"/>
<net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" storage_index="104" tap_mode="classic" type="unknown"/>
<net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" storage_index="103" tap_mode="classic" type="unknown"/>
<net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" storage_index="102" tap_mode="classic" type="unknown"/>
<net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" storage_index="101" tap_mode="classic" type="unknown"/>
<net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" storage_index="100" tap_mode="classic" type="unknown"/>
<net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" storage_index="97" tap_mode="classic" type="unknown"/>
<net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" storage_index="86" tap_mode="classic" type="unknown"/>
<net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" storage_index="75" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15..0]" order="msb_to_lsb" type="combinatorial">
<net data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" storage_index="114" tap_mode="classic" type="unknown"/>
<net data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" storage_index="113" tap_mode="classic" type="unknown"/>
<net data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" storage_index="112" tap_mode="classic" type="unknown"/>
<net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" storage_index="111" tap_mode="classic" type="unknown"/>
<net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" storage_index="110" tap_mode="classic" type="unknown"/>
<net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" storage_index="109" tap_mode="classic" type="unknown"/>
<net data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" storage_index="123" tap_mode="classic" type="unknown"/>
<net data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" storage_index="122" tap_mode="classic" type="unknown"/>
<net data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" storage_index="121" tap_mode="classic" type="unknown"/>
<net data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" storage_index="120" tap_mode="classic" type="unknown"/>
<net data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" storage_index="119" tap_mode="classic" type="unknown"/>
<net data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" storage_index="118" tap_mode="classic" type="unknown"/>
<net data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" storage_index="117" tap_mode="classic" type="unknown"/>
<net data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" storage_index="116" tap_mode="classic" type="unknown"/>
<net data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" storage_index="115" tap_mode="classic" type="unknown"/>
<net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" storage_index="108" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8..0]" order="msb_to_lsb" type="register">
<net data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" storage_index="135" tap_mode="classic" type="unknown"/>
<net data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" storage_index="134" tap_mode="classic" type="unknown"/>
<net data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" storage_index="133" tap_mode="classic" type="unknown"/>
<net data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" storage_index="132" tap_mode="classic" type="unknown"/>
<net data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" storage_index="131" tap_mode="classic" type="unknown"/>
<net data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" storage_index="130" tap_mode="classic" type="unknown"/>
<net data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" storage_index="129" tap_mode="classic" type="unknown"/>
<net data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" storage_index="128" tap_mode="classic" type="unknown"/>
<net data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" storage_index="127" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8..0]" order="msb_to_lsb" type="register">
<net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" storage_index="33" tap_mode="classic" type="unknown"/>
<net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" storage_index="32" tap_mode="classic" type="unknown"/>
<net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" storage_index="31" tap_mode="classic" type="unknown"/>
<net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" storage_index="30" tap_mode="classic" type="unknown"/>
<net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" storage_index="29" tap_mode="classic" type="unknown"/>
<net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" storage_index="28" tap_mode="classic" type="unknown"/>
<net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" storage_index="27" tap_mode="classic" type="unknown"/>
<net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" storage_index="26" tap_mode="classic" type="unknown"/>
<net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" storage_index="25" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31..0]" order="msb_to_lsb" type="register">
<net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" storage_index="58" tap_mode="classic" type="unknown"/>
<net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" storage_index="57" tap_mode="classic" type="unknown"/>
<net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" storage_index="55" tap_mode="classic" type="unknown"/>
<net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" storage_index="54" tap_mode="classic" type="unknown"/>
<net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" storage_index="53" tap_mode="classic" type="unknown"/>
<net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" storage_index="52" tap_mode="classic" type="unknown"/>
<net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" storage_index="51" tap_mode="classic" type="unknown"/>
<net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" storage_index="50" tap_mode="classic" type="unknown"/>
<net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" storage_index="49" tap_mode="classic" type="unknown"/>
<net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" storage_index="48" tap_mode="classic" type="unknown"/>
<net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" storage_index="47" tap_mode="classic" type="unknown"/>
<net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" storage_index="46" tap_mode="classic" type="unknown"/>
<net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" storage_index="44" tap_mode="classic" type="unknown"/>
<net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" storage_index="43" tap_mode="classic" type="unknown"/>
<net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" storage_index="42" tap_mode="classic" type="unknown"/>
<net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" storage_index="41" tap_mode="classic" type="unknown"/>
<net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" storage_index="40" tap_mode="classic" type="unknown"/>
<net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" storage_index="39" tap_mode="classic" type="unknown"/>
<net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" storage_index="38" tap_mode="classic" type="unknown"/>
<net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" storage_index="37" tap_mode="classic" type="unknown"/>
<net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" storage_index="36" tap_mode="classic" type="unknown"/>
<net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" storage_index="35" tap_mode="classic" type="unknown"/>
<net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" storage_index="65" tap_mode="classic" type="unknown"/>
<net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" storage_index="64" tap_mode="classic" type="unknown"/>
<net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" storage_index="63" tap_mode="classic" type="unknown"/>
<net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" storage_index="62" tap_mode="classic" type="unknown"/>
<net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" storage_index="61" tap_mode="classic" type="unknown"/>
<net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" storage_index="60" tap_mode="classic" type="unknown"/>
<net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" storage_index="59" tap_mode="classic" type="unknown"/>
<net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" storage_index="56" tap_mode="classic" type="unknown"/>
<net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" storage_index="45" tap_mode="classic" type="unknown"/>
<net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" storage_index="34" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15..0]" order="msb_to_lsb" type="combinatorial">
<net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" storage_index="6" tap_mode="classic" type="unknown"/>
<net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" storage_index="5" tap_mode="classic" type="unknown"/>
<net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" storage_index="4" tap_mode="classic" type="unknown"/>
<net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" storage_index="3" tap_mode="classic" type="unknown"/>
<net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" storage_index="2" tap_mode="classic" type="unknown"/>
<net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" storage_index="1" tap_mode="classic" type="unknown"/>
<net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" storage_index="15" tap_mode="classic" type="unknown"/>
<net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" storage_index="14" tap_mode="classic" type="unknown"/>
<net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" storage_index="13" tap_mode="classic" type="unknown"/>
<net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" storage_index="12" tap_mode="classic" type="unknown"/>
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" storage_index="11" tap_mode="classic" type="unknown"/>
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" storage_index="10" tap_mode="classic" type="unknown"/>
<net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" storage_index="9" tap_mode="classic" type="unknown"/>
<net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" storage_index="8" tap_mode="classic" type="unknown"/>
<net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" storage_index="7" tap_mode="classic" type="unknown"/>
<net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" storage_index="0" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8..0]" order="msb_to_lsb" type="register">
<net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" storage_index="24" tap_mode="classic" type="unknown"/>
<net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" storage_index="23" tap_mode="classic" type="unknown"/>
<net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" storage_index="22" tap_mode="classic" type="unknown"/>
<net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" storage_index="21" tap_mode="classic" type="unknown"/>
<net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" storage_index="20" tap_mode="classic" type="unknown"/>
<net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" storage_index="19" tap_mode="classic" type="unknown"/>
<net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" storage_index="18" tap_mode="classic" type="unknown"/>
<net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" storage_index="17" tap_mode="classic" type="unknown"/>
<net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" storage_index="16" tap_mode="classic" type="unknown"/>
</bus>
</data_view>
<setup_view>
<net data_index="140" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|waitrequest" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="32" type="unknown"/>
<net data_index="137" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_ready" storage_index="137" tap_mode="classic" type="unknown"/>
<net data_index="139" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_valid" storage_index="139" tap_mode="classic" type="unknown"/>
<net data_index="138" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_startofpacket" storage_index="138" tap_mode="classic" type="unknown"/>
<net data_index="136" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|to_udp_endofpacket" storage_index="136" tap_mode="classic" trigger_index="1" type="unknown"/>
<net data_index="125" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="true" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_startofpacket" storage_index="125" tap_mode="classic" trigger_index="0" type="unknown"/>
<net data_index="126" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_valid" storage_index="126" tap_mode="classic" type="unknown"/>
<net data_index="124" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_ready" storage_index="124" tap_mode="classic" type="unknown"/>
<net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_wren_a" storage_index="107" tap_mode="classic" type="unknown"/>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8..0]" order="msb_to_lsb" type="combinatorial">
<net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[8]" storage_index="74" tap_mode="classic" type="unknown"/>
<net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[7]" storage_index="73" tap_mode="classic" type="unknown"/>
<net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[6]" storage_index="72" tap_mode="classic" type="unknown"/>
<net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[5]" storage_index="71" tap_mode="classic" type="unknown"/>
<net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[4]" storage_index="70" tap_mode="classic" type="unknown"/>
<net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[3]" storage_index="69" tap_mode="classic" type="unknown"/>
<net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[2]" storage_index="68" tap_mode="classic" type="unknown"/>
<net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[1]" storage_index="67" tap_mode="classic" type="unknown"/>
<net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|address_a[0]" storage_index="66" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31..0]" order="msb_to_lsb" type="combinatorial">
<net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[31]" storage_index="99" tap_mode="classic" type="unknown"/>
<net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[30]" storage_index="98" tap_mode="classic" type="unknown"/>
<net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[29]" storage_index="96" tap_mode="classic" type="unknown"/>
<net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[28]" storage_index="95" tap_mode="classic" type="unknown"/>
<net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[27]" storage_index="94" tap_mode="classic" type="unknown"/>
<net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[26]" storage_index="93" tap_mode="classic" type="unknown"/>
<net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[25]" storage_index="92" tap_mode="classic" type="unknown"/>
<net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[24]" storage_index="91" tap_mode="classic" type="unknown"/>
<net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[23]" storage_index="90" tap_mode="classic" type="unknown"/>
<net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[22]" storage_index="89" tap_mode="classic" type="unknown"/>
<net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[21]" storage_index="88" tap_mode="classic" type="unknown"/>
<net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[20]" storage_index="87" tap_mode="classic" type="unknown"/>
<net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[19]" storage_index="85" tap_mode="classic" type="unknown"/>
<net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[18]" storage_index="84" tap_mode="classic" type="unknown"/>
<net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[17]" storage_index="83" tap_mode="classic" type="unknown"/>
<net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[16]" storage_index="82" tap_mode="classic" type="unknown"/>
<net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[15]" storage_index="81" tap_mode="classic" type="unknown"/>
<net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[14]" storage_index="80" tap_mode="classic" type="unknown"/>
<net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[13]" storage_index="79" tap_mode="classic" type="unknown"/>
<net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[12]" storage_index="78" tap_mode="classic" type="unknown"/>
<net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[11]" storage_index="77" tap_mode="classic" type="unknown"/>
<net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[10]" storage_index="76" tap_mode="classic" type="unknown"/>
<net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[9]" storage_index="106" tap_mode="classic" type="unknown"/>
<net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[8]" storage_index="105" tap_mode="classic" type="unknown"/>
<net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[7]" storage_index="104" tap_mode="classic" type="unknown"/>
<net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[6]" storage_index="103" tap_mode="classic" type="unknown"/>
<net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[5]" storage_index="102" tap_mode="classic" type="unknown"/>
<net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[4]" storage_index="101" tap_mode="classic" type="unknown"/>
<net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[3]" storage_index="100" tap_mode="classic" type="unknown"/>
<net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[2]" storage_index="97" tap_mode="classic" type="unknown"/>
<net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[1]" storage_index="86" tap_mode="classic" type="unknown"/>
<net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_ram:data_caled_ram0|data_a[0]" storage_index="75" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15..0]" order="msb_to_lsb" type="combinatorial">
<net data_index="114" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[15]" storage_index="114" tap_mode="classic" type="unknown"/>
<net data_index="113" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[14]" storage_index="113" tap_mode="classic" type="unknown"/>
<net data_index="112" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[13]" storage_index="112" tap_mode="classic" type="unknown"/>
<net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[12]" storage_index="111" tap_mode="classic" type="unknown"/>
<net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[11]" storage_index="110" tap_mode="classic" type="unknown"/>
<net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[10]" storage_index="109" tap_mode="classic" type="unknown"/>
<net data_index="123" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[9]" storage_index="123" tap_mode="classic" type="unknown"/>
<net data_index="122" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[8]" storage_index="122" tap_mode="classic" type="unknown"/>
<net data_index="121" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[7]" storage_index="121" tap_mode="classic" type="unknown"/>
<net data_index="120" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[6]" storage_index="120" tap_mode="classic" type="unknown"/>
<net data_index="119" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[5]" storage_index="119" tap_mode="classic" type="unknown"/>
<net data_index="118" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[4]" storage_index="118" tap_mode="classic" type="unknown"/>
<net data_index="117" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[3]" storage_index="117" tap_mode="classic" type="unknown"/>
<net data_index="116" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[2]" storage_index="116" tap_mode="classic" type="unknown"/>
<net data_index="115" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[1]" storage_index="115" tap_mode="classic" type="unknown"/>
<net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_in_data[0]" storage_index="108" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8..0]" order="msb_to_lsb" type="register">
<net data_index="135" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[8]" storage_index="135" tap_mode="classic" type="unknown"/>
<net data_index="134" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[7]" storage_index="134" tap_mode="classic" type="unknown"/>
<net data_index="133" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[6]" storage_index="133" tap_mode="classic" type="unknown"/>
<net data_index="132" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[5]" storage_index="132" tap_mode="classic" type="unknown"/>
<net data_index="131" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[4]" storage_index="131" tap_mode="classic" type="unknown"/>
<net data_index="130" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[3]" storage_index="130" tap_mode="classic" type="unknown"/>
<net data_index="129" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[2]" storage_index="129" tap_mode="classic" type="unknown"/>
<net data_index="128" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[1]" storage_index="128" tap_mode="classic" type="unknown"/>
<net data_index="127" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|read_cali_address[0]" storage_index="127" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8..0]" order="msb_to_lsb" type="register">
<net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[8]" storage_index="33" tap_mode="classic" type="unknown"/>
<net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[7]" storage_index="32" tap_mode="classic" type="unknown"/>
<net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[6]" storage_index="31" tap_mode="classic" type="unknown"/>
<net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[5]" storage_index="30" tap_mode="classic" type="unknown"/>
<net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[4]" storage_index="29" tap_mode="classic" type="unknown"/>
<net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[3]" storage_index="28" tap_mode="classic" type="unknown"/>
<net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[2]" storage_index="27" tap_mode="classic" type="unknown"/>
<net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[1]" storage_index="26" tap_mode="classic" type="unknown"/>
<net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_address_a[0]" storage_index="25" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31..0]" order="msb_to_lsb" type="register">
<net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[31]" storage_index="58" tap_mode="classic" type="unknown"/>
<net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[30]" storage_index="57" tap_mode="classic" type="unknown"/>
<net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[29]" storage_index="55" tap_mode="classic" type="unknown"/>
<net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[28]" storage_index="54" tap_mode="classic" type="unknown"/>
<net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[27]" storage_index="53" tap_mode="classic" type="unknown"/>
<net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[26]" storage_index="52" tap_mode="classic" type="unknown"/>
<net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[25]" storage_index="51" tap_mode="classic" type="unknown"/>
<net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[24]" storage_index="50" tap_mode="classic" type="unknown"/>
<net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[23]" storage_index="49" tap_mode="classic" type="unknown"/>
<net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[22]" storage_index="48" tap_mode="classic" type="unknown"/>
<net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[21]" storage_index="47" tap_mode="classic" type="unknown"/>
<net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[20]" storage_index="46" tap_mode="classic" type="unknown"/>
<net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[19]" storage_index="44" tap_mode="classic" type="unknown"/>
<net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[18]" storage_index="43" tap_mode="classic" type="unknown"/>
<net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[17]" storage_index="42" tap_mode="classic" type="unknown"/>
<net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[16]" storage_index="41" tap_mode="classic" type="unknown"/>
<net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[15]" storage_index="40" tap_mode="classic" type="unknown"/>
<net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[14]" storage_index="39" tap_mode="classic" type="unknown"/>
<net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[13]" storage_index="38" tap_mode="classic" type="unknown"/>
<net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[12]" storage_index="37" tap_mode="classic" type="unknown"/>
<net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[11]" storage_index="36" tap_mode="classic" type="unknown"/>
<net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[10]" storage_index="35" tap_mode="classic" type="unknown"/>
<net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[9]" storage_index="65" tap_mode="classic" type="unknown"/>
<net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[8]" storage_index="64" tap_mode="classic" type="unknown"/>
<net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[7]" storage_index="63" tap_mode="classic" type="unknown"/>
<net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[6]" storage_index="62" tap_mode="classic" type="unknown"/>
<net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[5]" storage_index="61" tap_mode="classic" type="unknown"/>
<net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[4]" storage_index="60" tap_mode="classic" type="unknown"/>
<net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[3]" storage_index="59" tap_mode="classic" type="unknown"/>
<net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[2]" storage_index="56" tap_mode="classic" type="unknown"/>
<net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[1]" storage_index="45" tap_mode="classic" type="unknown"/>
<net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|data_caled_data_a[0]" storage_index="34" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15..0]" order="msb_to_lsb" type="combinatorial">
<net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[15]" storage_index="6" tap_mode="classic" type="unknown"/>
<net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[14]" storage_index="5" tap_mode="classic" type="unknown"/>
<net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[13]" storage_index="4" tap_mode="classic" type="unknown"/>
<net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[12]" storage_index="3" tap_mode="classic" type="unknown"/>
<net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[11]" storage_index="2" tap_mode="classic" type="unknown"/>
<net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[10]" storage_index="1" tap_mode="classic" type="unknown"/>
<net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[9]" storage_index="15" tap_mode="classic" type="unknown"/>
<net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[8]" storage_index="14" tap_mode="classic" type="unknown"/>
<net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[7]" storage_index="13" tap_mode="classic" type="unknown"/>
<net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[6]" storage_index="12" tap_mode="classic" type="unknown"/>
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[5]" storage_index="11" tap_mode="classic" type="unknown"/>
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[4]" storage_index="10" tap_mode="classic" type="unknown"/>
<net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[3]" storage_index="9" tap_mode="classic" type="unknown"/>
<net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[2]" storage_index="8" tap_mode="classic" type="unknown"/>
<net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[1]" storage_index="7" tap_mode="classic" type="unknown"/>
<net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac[0]" storage_index="0" tap_mode="classic" type="unknown"/>
</bus>
<bus is_selected="false" level-0="alt_or" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8..0]" order="msb_to_lsb" type="register">
<net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[8]" storage_index="24" tap_mode="classic" type="unknown"/>
<net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[7]" storage_index="23" tap_mode="classic" type="unknown"/>
<net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[6]" storage_index="22" tap_mode="classic" type="unknown"/>
<net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[5]" storage_index="21" tap_mode="classic" type="unknown"/>
<net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[4]" storage_index="20" tap_mode="classic" type="unknown"/>
<net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[3]" storage_index="19" tap_mode="classic" type="unknown"/>
<net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[2]" storage_index="18" tap_mode="classic" type="unknown"/>
<net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[1]" storage_index="17" tap_mode="classic" type="unknown"/>
<net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_selected="false" is_storage_input="true" is_trigger_input="false" name="q_sys:q_sys_inst|sensor_algo:sensor_interface|algo_top_cl_cali_rms:recon|calibration:calibration0|cali_fac_buffer[0]" storage_index="16" tap_mode="classic" type="unknown"/>
</bus>
</setup_view>
<trigger_in_editor/>
<trigger_out_editor/>
</presentation>
<trigger attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2024/07/25 16:46:53 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="256" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
<power_up_trigger position="pre" storage_qualifier_disabled="no"/>
<events use_custom_flow_control="yes">
<level enabled="yes" name="condition1" type="basic">
<power_up enabled="yes">
</power_up>
<op_node/>
</level>
<custom_flow_control>
<runtime_configurable comparison_operator="yes" counter_action="no" flag_action="no" logical_operator="yes" numerical_value="yes" state_transition="yes"/>
<flow_expression><![CDATA[state ST1:
trigger;]]>
</flow_expression>
<power_up_flow_expression><![CDATA[state ST1:
trigger;]]>
</power_up_flow_expression>
</custom_flow_control>
</events>
<storage_qualifier_events>
<transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
<pwr_up_transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</pwr_up_transitional>
</transitional>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
</storage_qualifier_events>
<log>
<data global_temp="1" name="log: 2024/07/25 16:46:53 #2"/>
<extradata/>
</log>
</trigger>
</signal_set>
</instance>
<mnemonics/>
<static_plugin_mnemonics/>
<global_info>
<single attribute="active instance" value="0"/>
<single attribute="config widget visible" value="1"/>
<single attribute="data log widget visible" value="1"/>
<single attribute="hierarchy widget visible" value="1"/>
<single attribute="instance widget visible" value="1"/>
<single attribute="jtag widget visible" value="1"/>
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<multi attribute="column width" size="23" value="34,34,799,74,68,78,95,96,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/>
<multi attribute="frame size" size="2" value="1920,1017"/>
<multi attribute="jtag widget size" size="2" value="306,137"/>
</global_info>
</session>

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FPGA_firmware/output_files/stp_clu.stp
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FPGA_firmware/q_sys.BAK.qsys
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FPGA_firmware/q_sys.sopcinfo
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FPGA_firmware/q_sys/cali_ram.bsf
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@ -1,200 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 384 496)
(text "cali_ram" (rect 167 -1 201 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 480 20 492)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "cali_ram_clk1_clk" (rect 0 0 70 12)(font "Arial" (font_size 8)))
(text "cali_ram_clk1_clk" (rect 4 61 106 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 160 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "cali_ram_clk2_clk" (rect 0 0 71 12)(font "Arial" (font_size 8)))
(text "cali_ram_clk2_clk" (rect 4 101 106 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 160 112)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "cali_ram_reset1_reset" (rect 0 0 89 12)(font "Arial" (font_size 8)))
(text "cali_ram_reset1_reset" (rect 4 141 130 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 160 152)(line_width 1))
)
(port
(pt 0 192)
(input)
(text "cali_ram_reset2_reset" (rect 0 0 90 12)(font "Arial" (font_size 8)))
(text "cali_ram_reset2_reset" (rect 4 181 130 192)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 160 192)(line_width 1))
)
(port
(pt 0 232)
(input)
(text "cali_ram_s1_address[8..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
(text "cali_ram_s1_address[8..0]" (rect 4 221 154 232)(font "Arial" (font_size 8)))
(line (pt 0 232)(pt 160 232)(line_width 3))
)
(port
(pt 0 248)
(input)
(text "cali_ram_s1_clken" (rect 0 0 74 12)(font "Arial" (font_size 8)))
(text "cali_ram_s1_clken" (rect 4 237 106 248)(font "Arial" (font_size 8)))
(line (pt 0 248)(pt 160 248)(line_width 1))
)
(port
(pt 0 264)
(input)
(text "cali_ram_s1_chipselect" (rect 0 0 92 12)(font "Arial" (font_size 8)))
(text "cali_ram_s1_chipselect" (rect 4 253 136 264)(font "Arial" (font_size 8)))
(line (pt 0 264)(pt 160 264)(line_width 1))
)
(port
(pt 0 280)
(input)
(text "cali_ram_s1_write" (rect 0 0 71 12)(font "Arial" (font_size 8)))
(text "cali_ram_s1_write" (rect 4 269 106 280)(font "Arial" (font_size 8)))
(line (pt 0 280)(pt 160 280)(line_width 1))
)
(port
(pt 0 312)
(input)
(text "cali_ram_s1_writedata[15..0]" (rect 0 0 112 12)(font "Arial" (font_size 8)))
(text "cali_ram_s1_writedata[15..0]" (rect 4 301 172 312)(font "Arial" (font_size 8)))
(line (pt 0 312)(pt 160 312)(line_width 3))
)
(port
(pt 0 328)
(input)
(text "cali_ram_s1_byteenable[1..0]" (rect 0 0 115 12)(font "Arial" (font_size 8)))
(text "cali_ram_s1_byteenable[1..0]" (rect 4 317 172 328)(font "Arial" (font_size 8)))
(line (pt 0 328)(pt 160 328)(line_width 3))
)
(port
(pt 0 368)
(input)
(text "cali_ram_s2_address[8..0]" (rect 0 0 107 12)(font "Arial" (font_size 8)))
(text "cali_ram_s2_address[8..0]" (rect 4 357 154 368)(font "Arial" (font_size 8)))
(line (pt 0 368)(pt 160 368)(line_width 3))
)
(port
(pt 0 384)
(input)
(text "cali_ram_s2_chipselect" (rect 0 0 93 12)(font "Arial" (font_size 8)))
(text "cali_ram_s2_chipselect" (rect 4 373 136 384)(font "Arial" (font_size 8)))
(line (pt 0 384)(pt 160 384)(line_width 1))
)
(port
(pt 0 400)
(input)
(text "cali_ram_s2_clken" (rect 0 0 75 12)(font "Arial" (font_size 8)))
(text "cali_ram_s2_clken" (rect 4 389 106 400)(font "Arial" (font_size 8)))
(line (pt 0 400)(pt 160 400)(line_width 1))
)
(port
(pt 0 416)
(input)
(text "cali_ram_s2_write" (rect 0 0 73 12)(font "Arial" (font_size 8)))
(text "cali_ram_s2_write" (rect 4 405 106 416)(font "Arial" (font_size 8)))
(line (pt 0 416)(pt 160 416)(line_width 1))
)
(port
(pt 0 448)
(input)
(text "cali_ram_s2_writedata[15..0]" (rect 0 0 113 12)(font "Arial" (font_size 8)))
(text "cali_ram_s2_writedata[15..0]" (rect 4 437 172 448)(font "Arial" (font_size 8)))
(line (pt 0 448)(pt 160 448)(line_width 3))
)
(port
(pt 0 464)
(input)
(text "cali_ram_s2_byteenable[1..0]" (rect 0 0 116 12)(font "Arial" (font_size 8)))
(text "cali_ram_s2_byteenable[1..0]" (rect 4 453 172 464)(font "Arial" (font_size 8)))
(line (pt 0 464)(pt 160 464)(line_width 3))
)
(port
(pt 0 296)
(output)
(text "cali_ram_s1_readdata[15..0]" (rect 0 0 112 12)(font "Arial" (font_size 8)))
(text "cali_ram_s1_readdata[15..0]" (rect 4 285 166 296)(font "Arial" (font_size 8)))
(line (pt 0 296)(pt 160 296)(line_width 3))
)
(port
(pt 0 432)
(output)
(text "cali_ram_s2_readdata[15..0]" (rect 0 0 113 12)(font "Arial" (font_size 8)))
(text "cali_ram_s2_readdata[15..0]" (rect 4 421 166 432)(font "Arial" (font_size 8)))
(line (pt 0 432)(pt 160 432)(line_width 3))
)
(drawing
(text "cali_ram_clk1" (rect 82 43 242 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 165 67 348 144)(font "Arial" (color 0 0 0)))
(text "cali_ram_clk2" (rect 80 83 238 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 165 107 348 224)(font "Arial" (color 0 0 0)))
(text "cali_ram_reset1" (rect 68 123 226 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 165 147 360 304)(font "Arial" (color 0 0 0)))
(text "cali_ram_reset2" (rect 66 163 222 339)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 165 187 360 384)(font "Arial" (color 0 0 0)))
(text "cali_ram_s1" (rect 91 203 248 419)(font "Arial" (color 128 0 0)(font_size 9)))
(text "address" (rect 165 227 372 464)(font "Arial" (color 0 0 0)))
(text "clken" (rect 165 243 360 496)(font "Arial" (color 0 0 0)))
(text "chipselect" (rect 165 259 390 528)(font "Arial" (color 0 0 0)))
(text "write" (rect 165 275 360 560)(font "Arial" (color 0 0 0)))
(text "readdata" (rect 165 291 378 592)(font "Arial" (color 0 0 0)))
(text "writedata" (rect 165 307 384 624)(font "Arial" (color 0 0 0)))
(text "byteenable" (rect 165 323 390 656)(font "Arial" (color 0 0 0)))
(text "cali_ram_s2" (rect 89 339 244 691)(font "Arial" (color 128 0 0)(font_size 9)))
(text "address" (rect 165 363 372 736)(font "Arial" (color 0 0 0)))
(text "chipselect" (rect 165 379 390 768)(font "Arial" (color 0 0 0)))
(text "clken" (rect 165 395 360 800)(font "Arial" (color 0 0 0)))
(text "write" (rect 165 411 360 832)(font "Arial" (color 0 0 0)))
(text "readdata" (rect 165 427 378 864)(font "Arial" (color 0 0 0)))
(text "writedata" (rect 165 443 384 896)(font "Arial" (color 0 0 0)))
(text "byteenable" (rect 165 459 390 928)(font "Arial" (color 0 0 0)))
(text " cali_ram " (rect 344 480 748 970)(font "Arial" ))
(line (pt 160 32)(pt 224 32)(line_width 1))
(line (pt 224 32)(pt 224 480)(line_width 1))
(line (pt 160 480)(pt 224 480)(line_width 1))
(line (pt 160 32)(pt 160 480)(line_width 1))
(line (pt 161 52)(pt 161 76)(line_width 1))
(line (pt 162 52)(pt 162 76)(line_width 1))
(line (pt 161 92)(pt 161 116)(line_width 1))
(line (pt 162 92)(pt 162 116)(line_width 1))
(line (pt 161 132)(pt 161 156)(line_width 1))
(line (pt 162 132)(pt 162 156)(line_width 1))
(line (pt 161 172)(pt 161 196)(line_width 1))
(line (pt 162 172)(pt 162 196)(line_width 1))
(line (pt 161 212)(pt 161 332)(line_width 1))
(line (pt 162 212)(pt 162 332)(line_width 1))
(line (pt 161 348)(pt 161 468)(line_width 1))
(line (pt 162 348)(pt 162 468)(line_width 1))
(line (pt 0 0)(pt 384 0)(line_width 1))
(line (pt 384 0)(pt 384 496)(line_width 1))
(line (pt 0 496)(pt 384 496)(line_width 1))
(line (pt 0 0)(pt 0 496)(line_width 1))
)
)

343
FPGA_firmware/q_sys/cali_ram.xml
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40
FPGA_firmware/q_sys/cali_ram_bb.v
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@ -1,40 +0,0 @@
module cali_ram (
cali_ram_s2_address,
cali_ram_s2_chipselect,
cali_ram_s2_clken,
cali_ram_s2_write,
cali_ram_s2_readdata,
cali_ram_s2_writedata,
cali_ram_s2_byteenable,
cali_ram_clk2_clk,
cali_ram_reset2_reset,
cali_ram_reset1_reset,
cali_ram_s1_address,
cali_ram_s1_clken,
cali_ram_s1_chipselect,
cali_ram_s1_write,
cali_ram_s1_readdata,
cali_ram_s1_writedata,
cali_ram_s1_byteenable,
cali_ram_clk1_clk);
input [8:0] cali_ram_s2_address;
input cali_ram_s2_chipselect;
input cali_ram_s2_clken;
input cali_ram_s2_write;
output [15:0] cali_ram_s2_readdata;
input [15:0] cali_ram_s2_writedata;
input [1:0] cali_ram_s2_byteenable;
input cali_ram_clk2_clk;
input cali_ram_reset2_reset;
input cali_ram_reset1_reset;
input [8:0] cali_ram_s1_address;
input cali_ram_s1_clken;
input cali_ram_s1_chipselect;
input cali_ram_s1_write;
output [15:0] cali_ram_s1_readdata;
input [15:0] cali_ram_s1_writedata;
input [1:0] cali_ram_s1_byteenable;
input cali_ram_clk1_clk;
endmodule

21
FPGA_firmware/q_sys/cali_ram_inst.v
View File

@ -1,21 +0,0 @@
cali_ram u0 (
.cali_ram_s2_address (<connected-to-cali_ram_s2_address>), // cali_ram_s2.address
.cali_ram_s2_chipselect (<connected-to-cali_ram_s2_chipselect>), // .chipselect
.cali_ram_s2_clken (<connected-to-cali_ram_s2_clken>), // .clken
.cali_ram_s2_write (<connected-to-cali_ram_s2_write>), // .write
.cali_ram_s2_readdata (<connected-to-cali_ram_s2_readdata>), // .readdata
.cali_ram_s2_writedata (<connected-to-cali_ram_s2_writedata>), // .writedata
.cali_ram_s2_byteenable (<connected-to-cali_ram_s2_byteenable>), // .byteenable
.cali_ram_clk2_clk (<connected-to-cali_ram_clk2_clk>), // cali_ram_clk2.clk
.cali_ram_reset2_reset (<connected-to-cali_ram_reset2_reset>), // cali_ram_reset2.reset
.cali_ram_reset1_reset (<connected-to-cali_ram_reset1_reset>), // cali_ram_reset1.reset
.cali_ram_s1_address (<connected-to-cali_ram_s1_address>), // cali_ram_s1.address
.cali_ram_s1_clken (<connected-to-cali_ram_s1_clken>), // .clken
.cali_ram_s1_chipselect (<connected-to-cali_ram_s1_chipselect>), // .chipselect
.cali_ram_s1_write (<connected-to-cali_ram_s1_write>), // .write
.cali_ram_s1_readdata (<connected-to-cali_ram_s1_readdata>), // .readdata
.cali_ram_s1_writedata (<connected-to-cali_ram_s1_writedata>), // .writedata
.cali_ram_s1_byteenable (<connected-to-cali_ram_s1_byteenable>), // .byteenable
.cali_ram_clk1_clk (<connected-to-cali_ram_clk1_clk>) // cali_ram_clk1.clk
);

640
FPGA_firmware/q_sys/q_sys.bsf
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@ -1,640 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 624 1568)
(text "q_sys" (rect 295 -1 320 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 1552 20 1564)(font "Arial" ))
(port
(pt 0 112)
(input)
(text "button_pio_external_connection_export[8..0]" (rect 0 0 174 12)(font "Arial" (font_size 8)))
(text "button_pio_external_connection_export[8..0]" (rect 4 101 262 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 256 112)(line_width 3))
)
(port
(pt 0 152)
(input)
(text "clock_bridge_0_in_clk_clk" (rect 0 0 105 12)(font "Arial" (font_size 8)))
(text "clock_bridge_0_in_clk_clk" (rect 4 141 154 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 256 152)(line_width 1))
)
(port
(pt 0 192)
(input)
(text "ddr3_ram_pll_ref_clk_clk" (rect 0 0 103 12)(font "Arial" (font_size 8)))
(text "ddr3_ram_pll_ref_clk_clk" (rect 4 181 148 192)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 256 192)(line_width 1))
)
(port
(pt 0 232)
(input)
(text "debug_uart_external_connection_rxd" (rect 0 0 147 12)(font "Arial" (font_size 8)))
(text "debug_uart_external_connection_rxd" (rect 4 221 208 232)(font "Arial" (font_size 8)))
(line (pt 0 232)(pt 256 232)(line_width 1))
)
(port
(pt 0 344)
(input)
(text "eth_tse_mac_mdio_connection_mdio_in" (rect 0 0 161 12)(font "Arial" (font_size 8)))
(text "eth_tse_mac_mdio_connection_mdio_in" (rect 4 333 214 344)(font "Arial" (font_size 8)))
(line (pt 0 344)(pt 256 344)(line_width 1))
)
(port
(pt 0 416)
(input)
(text "eth_tse_mac_rgmii_connection_rgmii_in[3..0]" (rect 0 0 181 12)(font "Arial" (font_size 8)))
(text "eth_tse_mac_rgmii_connection_rgmii_in[3..0]" (rect 4 405 262 416)(font "Arial" (font_size 8)))
(line (pt 0 416)(pt 256 416)(line_width 3))
)
(port
(pt 0 448)
(input)
(text "eth_tse_mac_rgmii_connection_rx_control" (rect 0 0 171 12)(font "Arial" (font_size 8)))
(text "eth_tse_mac_rgmii_connection_rx_control" (rect 4 437 238 448)(font "Arial" (font_size 8)))
(line (pt 0 448)(pt 256 448)(line_width 1))
)
(port
(pt 0 504)
(input)
(text "eth_tse_mac_status_connection_set_10" (rect 0 0 161 12)(font "Arial" (font_size 8)))
(text "eth_tse_mac_status_connection_set_10" (rect 4 493 220 504)(font "Arial" (font_size 8)))
(line (pt 0 504)(pt 256 504)(line_width 1))
)
(port
(pt 0 520)
(input)
(text "eth_tse_mac_status_connection_set_1000" (rect 0 0 171 12)(font "Arial" (font_size 8)))
(text "eth_tse_mac_status_connection_set_1000" (rect 4 509 232 520)(font "Arial" (font_size 8)))
(line (pt 0 520)(pt 256 520)(line_width 1))
)
(port
(pt 0 592)
(input)
(text "eth_tse_pcs_mac_rx_clock_connection_clk" (rect 0 0 177 12)(font "Arial" (font_size 8)))
(text "eth_tse_pcs_mac_rx_clock_connection_clk" (rect 4 581 238 592)(font "Arial" (font_size 8)))
(line (pt 0 592)(pt 256 592)(line_width 1))
)
(port
(pt 0 632)
(input)
(text "eth_tse_pcs_mac_tx_clock_connection_clk" (rect 0 0 175 12)(font "Arial" (font_size 8)))
(text "eth_tse_pcs_mac_tx_clock_connection_clk" (rect 4 621 238 632)(font "Arial" (font_size 8)))
(line (pt 0 632)(pt 256 632)(line_width 1))
)
(port
(pt 0 944)
(input)
(text "mem_resetn_in_reset_reset_n" (rect 0 0 126 12)(font "Arial" (font_size 8)))
(text "mem_resetn_in_reset_reset_n" (rect 4 933 166 944)(font "Arial" (font_size 8)))
(line (pt 0 944)(pt 256 944)(line_width 1))
)
(port
(pt 0 1248)
(input)
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 1237 82 1248)(font "Arial" (font_size 8)))
(line (pt 0 1248)(pt 256 1248)(line_width 1))
)
(port
(pt 0 1288)
(input)
(text "sensor_in_adc_data[4..0]" (rect 0 0 102 12)(font "Arial" (font_size 8)))
(text "sensor_in_adc_data[4..0]" (rect 4 1277 148 1288)(font "Arial" (font_size 8)))
(line (pt 0 1288)(pt 256 1288)(line_width 3))
)
(port
(pt 0 1304)
(input)
(text "sensor_in_trg" (rect 0 0 55 12)(font "Arial" (font_size 8)))
(text "sensor_in_trg" (rect 4 1293 82 1304)(font "Arial" (font_size 8)))
(line (pt 0 1304)(pt 256 1304)(line_width 1))
)
(port
(pt 0 1464)
(input)
(text "sensor_synchro_ext_input[7..0]" (rect 0 0 127 12)(font "Arial" (font_size 8)))
(text "sensor_synchro_ext_input[7..0]" (rect 4 1453 184 1464)(font "Arial" (font_size 8)))
(line (pt 0 1464)(pt 256 1464)(line_width 3))
)
(port
(pt 0 1480)
(input)
(text "sensor_synchro_serial_rx" (rect 0 0 106 12)(font "Arial" (font_size 8)))
(text "sensor_synchro_serial_rx" (rect 4 1469 148 1480)(font "Arial" (font_size 8)))
(line (pt 0 1480)(pt 256 1480)(line_width 1))
)
(port
(pt 0 1536)
(input)
(text "sys_clk_clk" (rect 0 0 48 12)(font "Arial" (font_size 8)))
(text "sys_clk_clk" (rect 4 1525 70 1536)(font "Arial" (font_size 8)))
(line (pt 0 1536)(pt 256 1536)(line_width 1))
)
(port
(pt 624 72)
(output)
(text "altpll_shift_c0_clk" (rect 0 0 69 12)(font "Arial" (font_size 8)))
(text "altpll_shift_c0_clk" (rect 533 61 647 72)(font "Arial" (font_size 8)))
(line (pt 624 72)(pt 368 72)(line_width 1))
)
(port
(pt 0 72)
(output)
(text "altpll_shift_locked_conduit_export" (rect 0 0 132 12)(font "Arial" (font_size 8)))
(text "altpll_shift_locked_conduit_export" (rect 4 61 208 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 256 72)(line_width 1))
)
(port
(pt 0 248)
(output)
(text "debug_uart_external_connection_txd" (rect 0 0 146 12)(font "Arial" (font_size 8)))
(text "debug_uart_external_connection_txd" (rect 4 237 208 248)(font "Arial" (font_size 8)))
(line (pt 0 248)(pt 256 248)(line_width 1))
)
(port
(pt 624 112)
(output)
(text "enet_pll_c0_clk" (rect 0 0 61 12)(font "Arial" (font_size 8)))
(text "enet_pll_c0_clk" (rect 545 101 635 112)(font "Arial" (font_size 8)))
(line (pt 624 112)(pt 368 112)(line_width 1))
)
(port
(pt 624 152)
(output)
(text "enet_pll_c1_clk" (rect 0 0 60 12)(font "Arial" (font_size 8)))
(text "enet_pll_c1_clk" (rect 547 141 637 152)(font "Arial" (font_size 8)))
(line (pt 624 152)(pt 368 152)(line_width 1))
)
(port
(pt 624 192)
(output)
(text "enet_pll_c2_clk" (rect 0 0 61 12)(font "Arial" (font_size 8)))
(text "enet_pll_c2_clk" (rect 545 181 635 192)(font "Arial" (font_size 8)))
(line (pt 624 192)(pt 368 192)(line_width 1))
)
(port
(pt 624 232)
(output)
(text "enet_pll_c3_clk" (rect 0 0 61 12)(font "Arial" (font_size 8)))
(text "enet_pll_c3_clk" (rect 545 221 635 232)(font "Arial" (font_size 8)))
(line (pt 624 232)(pt 368 232)(line_width 1))
)
(port
(pt 624 272)
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(line (pt 257 812)(pt 257 836)(line_width 1))
(line (pt 258 812)(pt 258 836)(line_width 1))
(line (pt 257 852)(pt 257 908)(line_width 1))
(line (pt 258 852)(pt 258 908)(line_width 1))
(line (pt 257 924)(pt 257 948)(line_width 1))
(line (pt 258 924)(pt 258 948)(line_width 1))
(line (pt 257 964)(pt 257 1212)(line_width 1))
(line (pt 258 964)(pt 258 1212)(line_width 1))
(line (pt 257 1228)(pt 257 1252)(line_width 1))
(line (pt 258 1228)(pt 258 1252)(line_width 1))
(line (pt 257 1268)(pt 257 1388)(line_width 1))
(line (pt 258 1268)(pt 258 1388)(line_width 1))
(line (pt 257 1404)(pt 257 1428)(line_width 1))
(line (pt 258 1404)(pt 258 1428)(line_width 1))
(line (pt 257 1444)(pt 257 1500)(line_width 1))
(line (pt 258 1444)(pt 258 1500)(line_width 1))
(line (pt 257 1516)(pt 257 1540)(line_width 1))
(line (pt 258 1516)(pt 258 1540)(line_width 1))
(line (pt 0 0)(pt 624 0)(line_width 1))
(line (pt 624 0)(pt 624 1568)(line_width 1))
(line (pt 0 1568)(pt 624 1568)(line_width 1))
(line (pt 0 0)(pt 0 1568)(line_width 1))
)
)

1000
FPGA_firmware/q_sys/q_sys.csv
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3346
FPGA_firmware/q_sys/q_sys.spd
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21598
FPGA_firmware/q_sys/q_sys.xml
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File diff suppressed because one or more lines are too long

132
FPGA_firmware/q_sys/q_sys_bb.v
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@ -1,132 +0,0 @@
module q_sys (
altpll_shift_c0_clk,
altpll_shift_locked_conduit_export,
button_pio_external_connection_export,
clock_bridge_0_in_clk_clk,
ddr3_ram_pll_ref_clk_clk,
debug_uart_external_connection_rxd,
debug_uart_external_connection_txd,
enet_pll_c0_clk,
enet_pll_c1_clk,
enet_pll_c2_clk,
enet_pll_c3_clk,
enet_pll_c4_clk,
enet_pll_locked_conduit_export,
eth_tse_mac_mdio_connection_mdc,
eth_tse_mac_mdio_connection_mdio_in,
eth_tse_mac_mdio_connection_mdio_out,
eth_tse_mac_mdio_connection_mdio_oen,
eth_tse_mac_rgmii_connection_rgmii_in,
eth_tse_mac_rgmii_connection_rgmii_out,
eth_tse_mac_rgmii_connection_rx_control,
eth_tse_mac_rgmii_connection_tx_control,
eth_tse_mac_status_connection_set_10,
eth_tse_mac_status_connection_set_1000,
eth_tse_mac_status_connection_eth_mode,
eth_tse_mac_status_connection_ena_10,
eth_tse_pcs_mac_rx_clock_connection_clk,
eth_tse_pcs_mac_tx_clock_connection_clk,
ext_flash_flash_dataout_conduit_dataout,
ext_flash_flash_dclk_out_conduit_dclk_out,
ext_flash_flash_ncs_conduit_ncs,
frame_timer_export,
led_pio_external_connection_export,
mem_if_ddr3_emif_0_status_local_init_done,
mem_if_ddr3_emif_0_status_local_cal_success,
mem_if_ddr3_emif_0_status_local_cal_fail,
mem_resetn_in_reset_reset_n,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_dm,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
reset_reset_n,
sensor_in_adc_data,
sensor_in_trg,
sensor_out_adc_clk,
sensor_out_adc_cnv,
sensor_out_sensor_clk,
sensor_out_sensor_gain,
sensor_out_sensor_rst,
sensor_status_status_out,
sensor_synchro_ext_input,
sensor_synchro_serial_rx,
sensor_synchro_serial_tx,
sys_clk_clk);
output altpll_shift_c0_clk;
output altpll_shift_locked_conduit_export;
input [8:0] button_pio_external_connection_export;
input clock_bridge_0_in_clk_clk;
input ddr3_ram_pll_ref_clk_clk;
input debug_uart_external_connection_rxd;
output debug_uart_external_connection_txd;
output enet_pll_c0_clk;
output enet_pll_c1_clk;
output enet_pll_c2_clk;
output enet_pll_c3_clk;
output enet_pll_c4_clk;
output enet_pll_locked_conduit_export;
output eth_tse_mac_mdio_connection_mdc;
input eth_tse_mac_mdio_connection_mdio_in;
output eth_tse_mac_mdio_connection_mdio_out;
output eth_tse_mac_mdio_connection_mdio_oen;
input [3:0] eth_tse_mac_rgmii_connection_rgmii_in;
output [3:0] eth_tse_mac_rgmii_connection_rgmii_out;
input eth_tse_mac_rgmii_connection_rx_control;
output eth_tse_mac_rgmii_connection_tx_control;
input eth_tse_mac_status_connection_set_10;
input eth_tse_mac_status_connection_set_1000;
output eth_tse_mac_status_connection_eth_mode;
output eth_tse_mac_status_connection_ena_10;
input eth_tse_pcs_mac_rx_clock_connection_clk;
input eth_tse_pcs_mac_tx_clock_connection_clk;
inout [3:0] ext_flash_flash_dataout_conduit_dataout;
output ext_flash_flash_dclk_out_conduit_dclk_out;
output [0:0] ext_flash_flash_ncs_conduit_ncs;
output frame_timer_export;
output [7:0] led_pio_external_connection_export;
output mem_if_ddr3_emif_0_status_local_init_done;
output mem_if_ddr3_emif_0_status_local_cal_success;
output mem_if_ddr3_emif_0_status_local_cal_fail;
input mem_resetn_in_reset_reset_n;
output [13:0] memory_mem_a;
output [2:0] memory_mem_ba;
inout [0:0] memory_mem_ck;
inout [0:0] memory_mem_ck_n;
output [0:0] memory_mem_cke;
output [0:0] memory_mem_cs_n;
output [0:0] memory_mem_dm;
output [0:0] memory_mem_ras_n;
output [0:0] memory_mem_cas_n;
output [0:0] memory_mem_we_n;
output memory_mem_reset_n;
inout [7:0] memory_mem_dq;
inout [0:0] memory_mem_dqs;
inout [0:0] memory_mem_dqs_n;
output [0:0] memory_mem_odt;
input reset_reset_n;
input [4:0] sensor_in_adc_data;
input sensor_in_trg;
output sensor_out_adc_clk;
output sensor_out_adc_cnv;
output sensor_out_sensor_clk;
output sensor_out_sensor_gain;
output sensor_out_sensor_rst;
output [7:0] sensor_status_status_out;
input [7:0] sensor_synchro_ext_input;
input sensor_synchro_serial_rx;
output sensor_synchro_serial_tx;
input sys_clk_clk;
endmodule

67
FPGA_firmware/q_sys/q_sys_inst.v
View File

@ -1,67 +0,0 @@
q_sys u0 (
.altpll_shift_c0_clk (<connected-to-altpll_shift_c0_clk>), // altpll_shift_c0.clk
.altpll_shift_locked_conduit_export (<connected-to-altpll_shift_locked_conduit_export>), // altpll_shift_locked_conduit.export
.button_pio_external_connection_export (<connected-to-button_pio_external_connection_export>), // button_pio_external_connection.export
.clock_bridge_0_in_clk_clk (<connected-to-clock_bridge_0_in_clk_clk>), // clock_bridge_0_in_clk.clk
.ddr3_ram_pll_ref_clk_clk (<connected-to-ddr3_ram_pll_ref_clk_clk>), // ddr3_ram_pll_ref_clk.clk
.debug_uart_external_connection_rxd (<connected-to-debug_uart_external_connection_rxd>), // debug_uart_external_connection.rxd
.debug_uart_external_connection_txd (<connected-to-debug_uart_external_connection_txd>), // .txd
.enet_pll_c0_clk (<connected-to-enet_pll_c0_clk>), // enet_pll_c0.clk
.enet_pll_c1_clk (<connected-to-enet_pll_c1_clk>), // enet_pll_c1.clk
.enet_pll_c2_clk (<connected-to-enet_pll_c2_clk>), // enet_pll_c2.clk
.enet_pll_c3_clk (<connected-to-enet_pll_c3_clk>), // enet_pll_c3.clk
.enet_pll_c4_clk (<connected-to-enet_pll_c4_clk>), // enet_pll_c4.clk
.enet_pll_locked_conduit_export (<connected-to-enet_pll_locked_conduit_export>), // enet_pll_locked_conduit.export
.eth_tse_mac_mdio_connection_mdc (<connected-to-eth_tse_mac_mdio_connection_mdc>), // eth_tse_mac_mdio_connection.mdc
.eth_tse_mac_mdio_connection_mdio_in (<connected-to-eth_tse_mac_mdio_connection_mdio_in>), // .mdio_in
.eth_tse_mac_mdio_connection_mdio_out (<connected-to-eth_tse_mac_mdio_connection_mdio_out>), // .mdio_out
.eth_tse_mac_mdio_connection_mdio_oen (<connected-to-eth_tse_mac_mdio_connection_mdio_oen>), // .mdio_oen
.eth_tse_mac_rgmii_connection_rgmii_in (<connected-to-eth_tse_mac_rgmii_connection_rgmii_in>), // eth_tse_mac_rgmii_connection.rgmii_in
.eth_tse_mac_rgmii_connection_rgmii_out (<connected-to-eth_tse_mac_rgmii_connection_rgmii_out>), // .rgmii_out
.eth_tse_mac_rgmii_connection_rx_control (<connected-to-eth_tse_mac_rgmii_connection_rx_control>), // .rx_control
.eth_tse_mac_rgmii_connection_tx_control (<connected-to-eth_tse_mac_rgmii_connection_tx_control>), // .tx_control
.eth_tse_mac_status_connection_set_10 (<connected-to-eth_tse_mac_status_connection_set_10>), // eth_tse_mac_status_connection.set_10
.eth_tse_mac_status_connection_set_1000 (<connected-to-eth_tse_mac_status_connection_set_1000>), // .set_1000
.eth_tse_mac_status_connection_eth_mode (<connected-to-eth_tse_mac_status_connection_eth_mode>), // .eth_mode
.eth_tse_mac_status_connection_ena_10 (<connected-to-eth_tse_mac_status_connection_ena_10>), // .ena_10
.eth_tse_pcs_mac_rx_clock_connection_clk (<connected-to-eth_tse_pcs_mac_rx_clock_connection_clk>), // eth_tse_pcs_mac_rx_clock_connection.clk
.eth_tse_pcs_mac_tx_clock_connection_clk (<connected-to-eth_tse_pcs_mac_tx_clock_connection_clk>), // eth_tse_pcs_mac_tx_clock_connection.clk
.ext_flash_flash_dataout_conduit_dataout (<connected-to-ext_flash_flash_dataout_conduit_dataout>), // ext_flash_flash_dataout.conduit_dataout
.ext_flash_flash_dclk_out_conduit_dclk_out (<connected-to-ext_flash_flash_dclk_out_conduit_dclk_out>), // ext_flash_flash_dclk_out.conduit_dclk_out
.ext_flash_flash_ncs_conduit_ncs (<connected-to-ext_flash_flash_ncs_conduit_ncs>), // ext_flash_flash_ncs.conduit_ncs
.frame_timer_export (<connected-to-frame_timer_export>), // frame_timer.export
.led_pio_external_connection_export (<connected-to-led_pio_external_connection_export>), // led_pio_external_connection.export
.mem_if_ddr3_emif_0_status_local_init_done (<connected-to-mem_if_ddr3_emif_0_status_local_init_done>), // mem_if_ddr3_emif_0_status.local_init_done
.mem_if_ddr3_emif_0_status_local_cal_success (<connected-to-mem_if_ddr3_emif_0_status_local_cal_success>), // .local_cal_success
.mem_if_ddr3_emif_0_status_local_cal_fail (<connected-to-mem_if_ddr3_emif_0_status_local_cal_fail>), // .local_cal_fail
.mem_resetn_in_reset_reset_n (<connected-to-mem_resetn_in_reset_reset_n>), // mem_resetn_in_reset.reset_n
.memory_mem_a (<connected-to-memory_mem_a>), // memory.mem_a
.memory_mem_ba (<connected-to-memory_mem_ba>), // .mem_ba
.memory_mem_ck (<connected-to-memory_mem_ck>), // .mem_ck
.memory_mem_ck_n (<connected-to-memory_mem_ck_n>), // .mem_ck_n
.memory_mem_cke (<connected-to-memory_mem_cke>), // .mem_cke
.memory_mem_cs_n (<connected-to-memory_mem_cs_n>), // .mem_cs_n
.memory_mem_dm (<connected-to-memory_mem_dm>), // .mem_dm
.memory_mem_ras_n (<connected-to-memory_mem_ras_n>), // .mem_ras_n
.memory_mem_cas_n (<connected-to-memory_mem_cas_n>), // .mem_cas_n
.memory_mem_we_n (<connected-to-memory_mem_we_n>), // .mem_we_n
.memory_mem_reset_n (<connected-to-memory_mem_reset_n>), // .mem_reset_n
.memory_mem_dq (<connected-to-memory_mem_dq>), // .mem_dq
.memory_mem_dqs (<connected-to-memory_mem_dqs>), // .mem_dqs
.memory_mem_dqs_n (<connected-to-memory_mem_dqs_n>), // .mem_dqs_n
.memory_mem_odt (<connected-to-memory_mem_odt>), // .mem_odt
.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
.sensor_in_adc_data (<connected-to-sensor_in_adc_data>), // sensor.in_adc_data
.sensor_in_trg (<connected-to-sensor_in_trg>), // .in_trg
.sensor_out_adc_clk (<connected-to-sensor_out_adc_clk>), // .out_adc_clk
.sensor_out_adc_cnv (<connected-to-sensor_out_adc_cnv>), // .out_adc_cnv
.sensor_out_sensor_clk (<connected-to-sensor_out_sensor_clk>), // .out_sensor_clk
.sensor_out_sensor_gain (<connected-to-sensor_out_sensor_gain>), // .out_sensor_gain
.sensor_out_sensor_rst (<connected-to-sensor_out_sensor_rst>), // .out_sensor_rst
.sensor_status_status_out (<connected-to-sensor_status_status_out>), // sensor_status.status_out
.sensor_synchro_ext_input (<connected-to-sensor_synchro_ext_input>), // sensor_synchro.ext_input
.sensor_synchro_serial_rx (<connected-to-sensor_synchro_serial_rx>), // .serial_rx
.sensor_synchro_serial_tx (<connected-to-sensor_synchro_serial_tx>), // .serial_tx
.sys_clk_clk (<connected-to-sys_clk_clk>) // sys_clk.clk
);

38
FPGA_firmware/q_sys/sensor_algo.bsf
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@ -1,38 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 64)
(text "sensor_algo" (rect 13 -1 61 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 48 20 60)(font "Arial" ))
(drawing
(text " system " (rect 45 48 138 106)(font "Arial" ))
(line (pt 16 32)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 80 48)(line_width 1))
(line (pt 16 48)(pt 80 48)(line_width 1))
(line (pt 16 32)(pt 16 48)(line_width 1))
(line (pt 0 0)(pt 97 0)(line_width 1))
(line (pt 97 0)(pt 97 64)(line_width 1))
(line (pt 0 64)(pt 97 64)(line_width 1))
(line (pt 0 0)(pt 0 64)(line_width 1))
)
)

121
FPGA_firmware/q_sys/sensor_algo.xml
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@ -1,121 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<deploy
date="2024.07.17.13:03:39"
outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/">
<perimeter>
<parameter
name="AUTO_GENERATION_ID"
type="Integer"
defaultValue="0"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_UNIQUE_ID"
type="String"
defaultValue=""
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_FAMILY"
type="String"
defaultValue="MAX 10"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE"
type="String"
defaultValue="10M50DAF484C6GES"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_SPEEDGRADE"
type="String"
defaultValue="6"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_RATE"
type="Long"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_SENSOR_ALGO_0_CLK_RESET_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<interface name="sensor_algo_0_clk" kind="clock" start="0">
<property name="clockRate" value="0" />
<property name="externallyDriven" value="false" />
<property name="ptfSchematicName" value="" />
<port name="sensor_algo_0_clk_clk" direction="input" role="clk" width="1" />
</interface>
<interface name="sensor_algo_0_rst" kind="reset" start="0">
<property name="associatedClock" value="sensor_algo_0_clk" />
<property name="synchronousEdges" value="DEASSERT" />
<port
name="sensor_algo_0_rst_reset"
direction="input"
role="reset"
width="1" />
</interface>
</perimeter>
<entity
path=""
parameterizationKey="sensor_algo:1.0:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1721214219,AUTO_SENSOR_ALGO_0_CLK_CLOCK_DOMAIN=-1,AUTO_SENSOR_ALGO_0_CLK_CLOCK_RATE=-1,AUTO_SENSOR_ALGO_0_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(sensor_algo:1.0:)"
instancePathKey="sensor_algo"
kind="sensor_algo"
version="1.0"
name="sensor_algo">
<parameter name="AUTO_SENSOR_ALGO_0_CLK_RESET_DOMAIN" value="-1" />
<parameter name="AUTO_GENERATION_ID" value="1721214219" />
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
<parameter name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_RATE" value="-1" />
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
<parameter name="AUTO_UNIQUE_ID" value="" />
<parameter name="AUTO_SENSOR_ALGO_0_CLK_CLOCK_DOMAIN" value="-1" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
<generatedFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/sensor_algo.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/sensor_algo.v"
type="VERILOG" />
</childGeneratedFiles>
<sourceFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/sensor_algo.qsys" />
</sourceFiles>
<childSourceFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/sensor_algo.qsys" />
</childSourceFiles>
<instantiator instantiator="sensor_algo" as="sensor_algo_0" />
<messages>
<message level="Debug" culprit="sensor_algo">queue size: 0 starting:sensor_algo "sensor_algo"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Debug" culprit="sensor_algo"><![CDATA["<b>sensor_algo</b>" reuses <b>sensor_algo</b> "<b>sensor_algo</b>"]]></message>
</messages>
</entity>
</deploy>

5
FPGA_firmware/q_sys/sensor_algo_bb.v
View File

@ -1,5 +0,0 @@
module sensor_algo (
);
endmodule

3
FPGA_firmware/q_sys/sensor_algo_inst.v
View File

@ -1,3 +0,0 @@
sensor_algo u0 (
);

213
FPGA_firmware/q_sys/st_splitter16.bsf
View File

@ -1,213 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 480 304)
(text "st_splitter16" (rect 205 -1 251 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 288 20 300)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "st_splitter16_clk_clk" (rect 0 0 79 12)(font "Arial" (font_size 8)))
(text "st_splitter16_clk_clk" (rect 4 61 130 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 160 72)(line_width 1))
)
(port
(pt 0 128)
(input)
(text "st_splitter16_in_valid" (rect 0 0 81 12)(font "Arial" (font_size 8)))
(text "st_splitter16_in_valid" (rect 4 117 136 128)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 160 128)(line_width 1))
)
(port
(pt 0 144)
(input)
(text "st_splitter16_in_startofpacket" (rect 0 0 115 12)(font "Arial" (font_size 8)))
(text "st_splitter16_in_startofpacket" (rect 4 133 184 144)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 160 144)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "st_splitter16_in_endofpacket" (rect 0 0 112 12)(font "Arial" (font_size 8)))
(text "st_splitter16_in_endofpacket" (rect 4 149 172 160)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 160 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "st_splitter16_in_empty" (rect 0 0 89 12)(font "Arial" (font_size 8)))
(text "st_splitter16_in_empty" (rect 4 165 136 176)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 160 176)(line_width 1))
)
(port
(pt 0 192)
(input)
(text "st_splitter16_in_data[15..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
(text "st_splitter16_in_data[15..0]" (rect 4 181 172 192)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 160 192)(line_width 3))
)
(port
(pt 480 72)
(input)
(text "st_splitter16_out0_ready" (rect 0 0 97 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out0_ready" (rect 357 61 501 72)(font "Arial" (font_size 8)))
(line (pt 480 72)(pt 304 72)(line_width 1))
)
(port
(pt 480 192)
(input)
(text "st_splitter16_out1_ready" (rect 0 0 96 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out1_ready" (rect 359 181 503 192)(font "Arial" (font_size 8)))
(line (pt 480 192)(pt 304 192)(line_width 1))
)
(port
(pt 0 232)
(input)
(text "st_splitter16_reset_reset" (rect 0 0 97 12)(font "Arial" (font_size 8)))
(text "st_splitter16_reset_reset" (rect 4 221 154 232)(font "Arial" (font_size 8)))
(line (pt 0 232)(pt 160 232)(line_width 1))
)
(port
(pt 0 112)
(output)
(text "st_splitter16_in_ready" (rect 0 0 87 12)(font "Arial" (font_size 8)))
(text "st_splitter16_in_ready" (rect 4 101 136 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 160 112)(line_width 1))
)
(port
(pt 480 88)
(output)
(text "st_splitter16_out0_valid" (rect 0 0 92 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out0_valid" (rect 363 77 507 88)(font "Arial" (font_size 8)))
(line (pt 480 88)(pt 304 88)(line_width 1))
)
(port
(pt 480 104)
(output)
(text "st_splitter16_out0_startofpacket" (rect 0 0 126 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out0_startofpacket" (rect 320 93 512 104)(font "Arial" (font_size 8)))
(line (pt 480 104)(pt 304 104)(line_width 1))
)
(port
(pt 480 120)
(output)
(text "st_splitter16_out0_endofpacket" (rect 0 0 122 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out0_endofpacket" (rect 324 109 504 120)(font "Arial" (font_size 8)))
(line (pt 480 120)(pt 304 120)(line_width 1))
)
(port
(pt 480 136)
(output)
(text "st_splitter16_out0_empty" (rect 0 0 100 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out0_empty" (rect 356 125 500 136)(font "Arial" (font_size 8)))
(line (pt 480 136)(pt 304 136)(line_width 1))
)
(port
(pt 480 152)
(output)
(text "st_splitter16_out0_data[15..0]" (rect 0 0 114 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out0_data[15..0]" (rect 336 141 516 152)(font "Arial" (font_size 8)))
(line (pt 480 152)(pt 304 152)(line_width 3))
)
(port
(pt 480 208)
(output)
(text "st_splitter16_out1_valid" (rect 0 0 90 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out1_valid" (rect 365 197 509 208)(font "Arial" (font_size 8)))
(line (pt 480 208)(pt 304 208)(line_width 1))
)
(port
(pt 480 224)
(output)
(text "st_splitter16_out1_startofpacket" (rect 0 0 125 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out1_startofpacket" (rect 322 213 514 224)(font "Arial" (font_size 8)))
(line (pt 480 224)(pt 304 224)(line_width 1))
)
(port
(pt 480 240)
(output)
(text "st_splitter16_out1_endofpacket" (rect 0 0 121 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out1_endofpacket" (rect 326 229 506 240)(font "Arial" (font_size 8)))
(line (pt 480 240)(pt 304 240)(line_width 1))
)
(port
(pt 480 256)
(output)
(text "st_splitter16_out1_empty" (rect 0 0 99 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out1_empty" (rect 358 245 502 256)(font "Arial" (font_size 8)))
(line (pt 480 256)(pt 304 256)(line_width 1))
)
(port
(pt 480 272)
(output)
(text "st_splitter16_out1_data[15..0]" (rect 0 0 113 12)(font "Arial" (font_size 8)))
(text "st_splitter16_out1_data[15..0]" (rect 338 261 518 272)(font "Arial" (font_size 8)))
(line (pt 480 272)(pt 304 272)(line_width 3))
)
(drawing
(text "st_splitter16_clk" (rect 66 43 234 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 165 67 348 144)(font "Arial" (color 0 0 0)))
(text "st_splitter16_in" (rect 72 83 240 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "ready" (rect 165 107 360 224)(font "Arial" (color 0 0 0)))
(text "valid" (rect 165 123 360 256)(font "Arial" (color 0 0 0)))
(text "startofpacket" (rect 165 139 408 288)(font "Arial" (color 0 0 0)))
(text "endofpacket" (rect 165 155 396 320)(font "Arial" (color 0 0 0)))
(text "empty" (rect 165 171 360 352)(font "Arial" (color 0 0 0)))
(text "data" (rect 165 187 354 384)(font "Arial" (color 0 0 0)))
(text "st_splitter16_out0" (rect 305 43 718 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "ready" (rect 276 67 582 144)(font "Arial" (color 0 0 0)))
(text "valid" (rect 281 83 592 176)(font "Arial" (color 0 0 0)))
(text "startofpacket" (rect 244 99 566 208)(font "Arial" (color 0 0 0)))
(text "endofpacket" (rect 249 115 564 240)(font "Arial" (color 0 0 0)))
(text "empty" (rect 274 131 578 272)(font "Arial" (color 0 0 0)))
(text "data" (rect 283 147 590 304)(font "Arial" (color 0 0 0)))
(text "st_splitter16_out1" (rect 305 163 718 339)(font "Arial" (color 128 0 0)(font_size 9)))
(text "ready" (rect 276 187 582 384)(font "Arial" (color 0 0 0)))
(text "valid" (rect 281 203 592 416)(font "Arial" (color 0 0 0)))
(text "startofpacket" (rect 244 219 566 448)(font "Arial" (color 0 0 0)))
(text "endofpacket" (rect 249 235 564 480)(font "Arial" (color 0 0 0)))
(text "empty" (rect 274 251 578 512)(font "Arial" (color 0 0 0)))
(text "data" (rect 283 267 590 544)(font "Arial" (color 0 0 0)))
(text "st_splitter16_reset" (rect 52 203 218 419)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 165 227 360 464)(font "Arial" (color 0 0 0)))
(text " st_splitter16 " (rect 425 288 940 586)(font "Arial" ))
(line (pt 160 32)(pt 304 32)(line_width 1))
(line (pt 304 32)(pt 304 288)(line_width 1))
(line (pt 160 288)(pt 304 288)(line_width 1))
(line (pt 160 32)(pt 160 288)(line_width 1))
(line (pt 161 52)(pt 161 76)(line_width 1))
(line (pt 162 52)(pt 162 76)(line_width 1))
(line (pt 161 92)(pt 161 196)(line_width 1))
(line (pt 162 92)(pt 162 196)(line_width 1))
(line (pt 303 52)(pt 303 156)(line_width 1))
(line (pt 302 52)(pt 302 156)(line_width 1))
(line (pt 303 172)(pt 303 276)(line_width 1))
(line (pt 302 172)(pt 302 276)(line_width 1))
(line (pt 161 212)(pt 161 236)(line_width 1))
(line (pt 162 212)(pt 162 236)(line_width 1))
(line (pt 0 0)(pt 480 0)(line_width 1))
(line (pt 480 0)(pt 480 304)(line_width 1))
(line (pt 0 304)(pt 480 304)(line_width 1))
(line (pt 0 0)(pt 0 304)(line_width 1))
)
)

292
FPGA_firmware/q_sys/st_splitter16.xml
View File

@ -1,292 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<deploy
date="2024.07.02.15:16:06"
outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/">
<perimeter>
<parameter
name="AUTO_GENERATION_ID"
type="Integer"
defaultValue="0"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_UNIQUE_ID"
type="String"
defaultValue=""
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_FAMILY"
type="String"
defaultValue="MAX 10"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE"
type="String"
defaultValue="10M50DAF484C6GES"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_SPEEDGRADE"
type="String"
defaultValue="6"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_ST_SPLITTER16_CLK_CLOCK_RATE"
type="Long"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_ST_SPLITTER16_CLK_CLOCK_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_ST_SPLITTER16_CLK_RESET_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<interface name="st_splitter16_clk" kind="clock" start="0">
<property name="clockRate" value="0" />
<property name="externallyDriven" value="false" />
<property name="ptfSchematicName" value="" />
<port name="st_splitter16_clk_clk" direction="input" role="clk" width="1" />
</interface>
<interface name="st_splitter16_in" kind="avalon_streaming" start="0">
<property name="associatedClock" value="st_splitter16_clk" />
<property name="associatedReset" value="st_splitter16_reset" />
<property name="beatsPerCycle" value="1" />
<property name="dataBitsPerSymbol" value="8" />
<property name="emptyWithinPacket" value="false" />
<property name="errorDescriptor" value="" />
<property name="firstSymbolInHighOrderBits" value="true" />
<property name="highOrderSymbolAtMSB" value="false" />
<property name="maxChannel" value="0" />
<property name="packetDescription" value="" />
<property name="readyLatency" value="0" />
<property name="symbolsPerBeat" value="2" />
<port
name="st_splitter16_in_ready"
direction="output"
role="ready"
width="1" />
<port
name="st_splitter16_in_valid"
direction="input"
role="valid"
width="1" />
<port
name="st_splitter16_in_startofpacket"
direction="input"
role="startofpacket"
width="1" />
<port
name="st_splitter16_in_endofpacket"
direction="input"
role="endofpacket"
width="1" />
<port
name="st_splitter16_in_empty"
direction="input"
role="empty"
width="1" />
<port name="st_splitter16_in_data" direction="input" role="data" width="16" />
</interface>
<interface name="st_splitter16_out0" kind="avalon_streaming" start="1">
<property name="associatedClock" value="st_splitter16_clk" />
<property name="associatedReset" value="st_splitter16_reset" />
<property name="beatsPerCycle" value="1" />
<property name="dataBitsPerSymbol" value="8" />
<property name="emptyWithinPacket" value="false" />
<property name="errorDescriptor" value="" />
<property name="firstSymbolInHighOrderBits" value="true" />
<property name="highOrderSymbolAtMSB" value="false" />
<property name="maxChannel" value="0" />
<property name="packetDescription" value="" />
<property name="readyLatency" value="0" />
<property name="symbolsPerBeat" value="2" />
<port
name="st_splitter16_out0_ready"
direction="input"
role="ready"
width="1" />
<port
name="st_splitter16_out0_valid"
direction="output"
role="valid"
width="1" />
<port
name="st_splitter16_out0_startofpacket"
direction="output"
role="startofpacket"
width="1" />
<port
name="st_splitter16_out0_endofpacket"
direction="output"
role="endofpacket"
width="1" />
<port
name="st_splitter16_out0_empty"
direction="output"
role="empty"
width="1" />
<port
name="st_splitter16_out0_data"
direction="output"
role="data"
width="16" />
</interface>
<interface name="st_splitter16_out1" kind="avalon_streaming" start="1">
<property name="associatedClock" value="st_splitter16_clk" />
<property name="associatedReset" value="st_splitter16_reset" />
<property name="beatsPerCycle" value="1" />
<property name="dataBitsPerSymbol" value="8" />
<property name="emptyWithinPacket" value="false" />
<property name="errorDescriptor" value="" />
<property name="firstSymbolInHighOrderBits" value="true" />
<property name="highOrderSymbolAtMSB" value="false" />
<property name="maxChannel" value="0" />
<property name="packetDescription" value="" />
<property name="readyLatency" value="0" />
<property name="symbolsPerBeat" value="2" />
<port
name="st_splitter16_out1_ready"
direction="input"
role="ready"
width="1" />
<port
name="st_splitter16_out1_valid"
direction="output"
role="valid"
width="1" />
<port
name="st_splitter16_out1_startofpacket"
direction="output"
role="startofpacket"
width="1" />
<port
name="st_splitter16_out1_endofpacket"
direction="output"
role="endofpacket"
width="1" />
<port
name="st_splitter16_out1_empty"
direction="output"
role="empty"
width="1" />
<port
name="st_splitter16_out1_data"
direction="output"
role="data"
width="16" />
</interface>
<interface name="st_splitter16_reset" kind="reset" start="0">
<property name="associatedClock" value="st_splitter16_clk" />
<property name="synchronousEdges" value="DEASSERT" />
<port
name="st_splitter16_reset_reset"
direction="input"
role="reset"
width="1" />
</interface>
</perimeter>
<entity
path=""
parameterizationKey="st_splitter16:1.0:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1719926165,AUTO_ST_SPLITTER16_CLK_CLOCK_DOMAIN=-1,AUTO_ST_SPLITTER16_CLK_CLOCK_RATE=-1,AUTO_ST_SPLITTER16_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(altera_avalon_st_splitter:19.1:BITS_PER_SYMBOL=8,CHANNEL_WIDTH=1,DATA_WIDTH=16,EMPTY_WIDTH=1,ERROR_DESCRIPTOR=,ERROR_WIDTH=1,MAX_CHANNELS=1,NUMBER_OF_OUTPUTS=2,QUALIFY_VALID_OUT=1,READY_LATENCY=0,USE_CHANNEL=0,USE_DATA=1,USE_ERROR=0,USE_PACKETS=1,USE_READY=1,USE_VALID=1)"
instancePathKey="st_splitter16"
kind="st_splitter16"
version="1.0"
name="st_splitter16">
<parameter name="AUTO_ST_SPLITTER16_CLK_CLOCK_DOMAIN" value="-1" />
<parameter name="AUTO_GENERATION_ID" value="1719926165" />
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
<parameter name="AUTO_UNIQUE_ID" value="" />
<parameter name="AUTO_ST_SPLITTER16_CLK_CLOCK_RATE" value="-1" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
<parameter name="AUTO_ST_SPLITTER16_CLK_RESET_DOMAIN" value="-1" />
<generatedFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/st_splitter16.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
type="SYSTEM_VERILOG"
attributes="" />
</childGeneratedFiles>
<sourceFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/st_splitter16.qsys" />
</sourceFiles>
<childSourceFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_splitter/altera_avalon_st_splitter_hw.tcl" />
</childSourceFiles>
<messages>
<message level="Debug" culprit="st_splitter16">queue size: 0 starting:st_splitter16 "st_splitter16"</message>
<message level="Progress" culprit="min"></message>
<message level="Progress" culprit="max"></message>
<message level="Progress" culprit="current"></message>
<message level="Debug">Transform: CustomInstructionTransform</message>
<message level="Debug">No custom instruction connections, skipping transform </message>
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
<message level="Debug">Transform: MMTransform</message>
<message level="Debug">Transform: InterruptMapperTransform</message>
<message level="Debug">Transform: InterruptSyncTransform</message>
<message level="Debug">Transform: InterruptFanoutTransform</message>
<message level="Debug">Transform: AvalonStreamingTransform</message>
<message level="Debug">Transform: ResetAdaptation</message>
<message level="Debug" culprit="st_splitter16"><![CDATA["<b>st_splitter16</b>" reuses <b>altera_avalon_st_splitter</b> "<b>submodules/altera_avalon_st_splitter</b>"]]></message>
<message level="Debug" culprit="st_splitter16">queue size: 0 starting:altera_avalon_st_splitter "submodules/altera_avalon_st_splitter"</message>
<message level="Info" culprit="st_splitter16"><![CDATA["<b>st_splitter16</b>" instantiated <b>altera_avalon_st_splitter</b> "<b>st_splitter16</b>"]]></message>
</messages>
</entity>
<entity
path="submodules/"
parameterizationKey="altera_avalon_st_splitter:19.1:BITS_PER_SYMBOL=8,CHANNEL_WIDTH=1,DATA_WIDTH=16,EMPTY_WIDTH=1,ERROR_DESCRIPTOR=,ERROR_WIDTH=1,MAX_CHANNELS=1,NUMBER_OF_OUTPUTS=2,QUALIFY_VALID_OUT=1,READY_LATENCY=0,USE_CHANNEL=0,USE_DATA=1,USE_ERROR=0,USE_PACKETS=1,USE_READY=1,USE_VALID=1"
instancePathKey="st_splitter16:.:st_splitter16"
kind="altera_avalon_st_splitter"
version="19.1"
name="altera_avalon_st_splitter">
<parameter name="NUMBER_OF_OUTPUTS" value="2" />
<parameter name="USE_DATA" value="1" />
<parameter name="ERROR_DESCRIPTOR" value="" />
<parameter name="USE_PACKETS" value="1" />
<parameter name="USE_READY" value="1" />
<parameter name="MAX_CHANNELS" value="1" />
<parameter name="USE_ERROR" value="0" />
<parameter name="EMPTY_WIDTH" value="1" />
<parameter name="CHANNEL_WIDTH" value="1" />
<parameter name="READY_LATENCY" value="0" />
<parameter name="DATA_WIDTH" value="16" />
<parameter name="BITS_PER_SYMBOL" value="8" />
<parameter name="ERROR_WIDTH" value="1" />
<parameter name="QUALIFY_VALID_OUT" value="1" />
<parameter name="USE_VALID" value="1" />
<parameter name="USE_CHANNEL" value="0" />
<generatedFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/dev_room_qlq/sensor_algo_qsys/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
type="SYSTEM_VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_splitter/altera_avalon_st_splitter_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="st_splitter16" as="st_splitter16" />
<messages>
<message level="Debug" culprit="st_splitter16">queue size: 0 starting:altera_avalon_st_splitter "submodules/altera_avalon_st_splitter"</message>
<message level="Info" culprit="st_splitter16"><![CDATA["<b>st_splitter16</b>" instantiated <b>altera_avalon_st_splitter</b> "<b>st_splitter16</b>"]]></message>
</messages>
</entity>
</deploy>

44
FPGA_firmware/q_sys/st_splitter16_bb.v
View File

@ -1,44 +0,0 @@
module st_splitter16 (
st_splitter16_clk_clk,
st_splitter16_reset_reset,
st_splitter16_in_ready,
st_splitter16_in_valid,
st_splitter16_in_startofpacket,
st_splitter16_in_endofpacket,
st_splitter16_in_empty,
st_splitter16_in_data,
st_splitter16_out0_ready,
st_splitter16_out0_valid,
st_splitter16_out0_startofpacket,
st_splitter16_out0_endofpacket,
st_splitter16_out0_empty,
st_splitter16_out0_data,
st_splitter16_out1_ready,
st_splitter16_out1_valid,
st_splitter16_out1_startofpacket,
st_splitter16_out1_endofpacket,
st_splitter16_out1_empty,
st_splitter16_out1_data);
input st_splitter16_clk_clk;
input st_splitter16_reset_reset;
output st_splitter16_in_ready;
input st_splitter16_in_valid;
input st_splitter16_in_startofpacket;
input st_splitter16_in_endofpacket;
input [0:0] st_splitter16_in_empty;
input [15:0] st_splitter16_in_data;
input st_splitter16_out0_ready;
output st_splitter16_out0_valid;
output st_splitter16_out0_startofpacket;
output st_splitter16_out0_endofpacket;
output [0:0] st_splitter16_out0_empty;
output [15:0] st_splitter16_out0_data;
input st_splitter16_out1_ready;
output st_splitter16_out1_valid;
output st_splitter16_out1_startofpacket;
output st_splitter16_out1_endofpacket;
output [0:0] st_splitter16_out1_empty;
output [15:0] st_splitter16_out1_data;
endmodule

23
FPGA_firmware/q_sys/st_splitter16_inst.v
View File

@ -1,23 +0,0 @@
st_splitter16 u0 (
.st_splitter16_clk_clk (<connected-to-st_splitter16_clk_clk>), // st_splitter16_clk.clk
.st_splitter16_reset_reset (<connected-to-st_splitter16_reset_reset>), // st_splitter16_reset.reset
.st_splitter16_in_ready (<connected-to-st_splitter16_in_ready>), // st_splitter16_in.ready
.st_splitter16_in_valid (<connected-to-st_splitter16_in_valid>), // .valid
.st_splitter16_in_startofpacket (<connected-to-st_splitter16_in_startofpacket>), // .startofpacket
.st_splitter16_in_endofpacket (<connected-to-st_splitter16_in_endofpacket>), // .endofpacket
.st_splitter16_in_empty (<connected-to-st_splitter16_in_empty>), // .empty
.st_splitter16_in_data (<connected-to-st_splitter16_in_data>), // .data
.st_splitter16_out0_ready (<connected-to-st_splitter16_out0_ready>), // st_splitter16_out0.ready
.st_splitter16_out0_valid (<connected-to-st_splitter16_out0_valid>), // .valid
.st_splitter16_out0_startofpacket (<connected-to-st_splitter16_out0_startofpacket>), // .startofpacket
.st_splitter16_out0_endofpacket (<connected-to-st_splitter16_out0_endofpacket>), // .endofpacket
.st_splitter16_out0_empty (<connected-to-st_splitter16_out0_empty>), // .empty
.st_splitter16_out0_data (<connected-to-st_splitter16_out0_data>), // .data
.st_splitter16_out1_ready (<connected-to-st_splitter16_out1_ready>), // st_splitter16_out1.ready
.st_splitter16_out1_valid (<connected-to-st_splitter16_out1_valid>), // .valid
.st_splitter16_out1_startofpacket (<connected-to-st_splitter16_out1_startofpacket>), // .startofpacket
.st_splitter16_out1_endofpacket (<connected-to-st_splitter16_out1_endofpacket>), // .endofpacket
.st_splitter16_out1_empty (<connected-to-st_splitter16_out1_empty>), // .empty
.st_splitter16_out1_data (<connected-to-st_splitter16_out1_data>) // .data
);

63314
FPGA_firmware/q_sys/synthesis/q_sys.debuginfo
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FPGA_firmware/q_sys/synthesis/q_sys.qip
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FPGA_firmware/q_sys/synthesis/q_sys.regmap
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@ -1,769 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
<name>q_sys</name>
<peripherals>
<peripheral>
<name>q_sys_sysid_control_slave_altera_avalon_sysid</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>8</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ID</name>
<displayName>System ID</displayName>
<description>A unique 32-bit value that is based on the contents of the QSys system. The id is similar to a check-sum value; QSys systems with different components, different configuration options, or both, produce different id values.</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>${sysid_id_value}</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>id</name>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TIMESTAMP</name>
<displayName>Time stamp</displayName>
<description>A unique 32-bit value that is based on the system generation time. The value is equivalent to the number of seconds after Jan. 1, 1970.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>${sysid_timestamp_value}</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>timestamp</name>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>q_sys_sys_clk_timer_s1_altera_avalon_timer</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>16</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>status</name>
<displayName>Status</displayName>
<description>The status register has two defined bits. TO (timeout), RUN</description>
<addressOffset>0x0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
<fields>
<field><name>TO</name>
<description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<readAction>clear</readAction>
</field>
<field><name>RUN</name>
<description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by
a write operation to the status register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
<parameters>
<parameter>
<name>Reserved</name>
<value>true</value>
</parameter>
</parameters>
</field>
</fields>
</register>
<register>
<name>control</name>
<description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description>
<addressOffset>0x1</addressOffset>
<size>16</size>
<access>read-write</access>
<reset>
<value>0x0</value>
</reset>
<field>
<name>ITO</name>
<description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CONT</name>
<description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>START</name>
<description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>STOP</name>
<description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
<parameters>
<parameter>
<name>Reserved</name>
<value>true</value>
</parameter>
</parameters>
</field>
</register>
<register>
<name>${period_name_0}</name>
<description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_name_0_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${period_name_1}</name>
<description></description>
<addressOffset>0x3</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_name_1_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${period_snap_0}</name>
<description></description>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_snap_0_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${period_snap_1}</name>
<description></description>
<addressOffset>0x5</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_snap_1_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_0}</name>
<description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_1}</name>
<description></description>
<addressOffset>0x7</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_2}</name>
<description></description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_3}</name>
<description></description>
<addressOffset>0x9</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<name>q_sys_output_pio_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>32</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DATA</name>
<displayName>Data</displayName>
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>data</name>
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIRECTION</name>
<displayName>Direction</displayName>
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>direction</name>
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IRQ_MASK</name>
<displayName>Interrupt mask</displayName>
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>interruptmask</name>
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EDGE_CAP</name>
<displayName>Edge capture</displayName>
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>edgecapture</name>
<description>Edge detection for each input port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SET_BIT</name>
<displayName>Outset</displayName>
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outset</name>
<description>Specifies which bit of the output port to set.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CLEAR_BITS</name>
<displayName>Outclear</displayName>
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outclear</name>
<description>Specifies which output bit to clear.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>q_sys_frame_timer_s1_altera_avalon_timer</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>16</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>status</name>
<displayName>Status</displayName>
<description>The status register has two defined bits. TO (timeout), RUN</description>
<addressOffset>0x0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
<fields>
<field><name>TO</name>
<description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<readAction>clear</readAction>
</field>
<field><name>RUN</name>
<description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by
a write operation to the status register.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>2</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
<parameters>
<parameter>
<name>Reserved</name>
<value>true</value>
</parameter>
</parameters>
</field>
</fields>
</register>
<register>
<name>control</name>
<description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description>
<addressOffset>0x1</addressOffset>
<size>16</size>
<access>read-write</access>
<reset>
<value>0x0</value>
</reset>
<field>
<name>ITO</name>
<description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CONT</name>
<description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>START</name>
<description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>STOP</name>
<description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>Reserved</name>
<description>Reserved</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
<parameters>
<parameter>
<name>Reserved</name>
<value>true</value>
</parameter>
</parameters>
</field>
</register>
<register>
<name>${period_name_0}</name>
<description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_name_0_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${period_name_1}</name>
<description></description>
<addressOffset>0x3</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_name_1_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${period_snap_0}</name>
<description></description>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_snap_0_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${period_snap_1}</name>
<description></description>
<addressOffset>0x5</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>${period_snap_1_reset_value}</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_0}</name>
<description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_1}</name>
<description></description>
<addressOffset>0x7</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_2}</name>
<description></description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
<register>
<name>${snap_3}</name>
<description></description>
<addressOffset>0x9</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffff</resetMask>
</register>
</registers>
</peripheral>
<peripheral>
<baseAddress>0x00000000</baseAddress>
<name>q_sys_ext_flash_avl_csr_altera_generic_quad_spi_controller</name>
<description>altera_generic_quad_spi_controller</description>
<registers>
<register>
<access>read-only</access>
<addressOffset>0x0</addressOffset>
<displayName>flash_rd_status</displayName>
<description>Perform read operation on flash device status register and store the read back data. </description>
<name>flash_rd_status</name>
<resetMask>0xffffffff</resetMask>
<resetValue>0x00000000</resetValue>
<size>32</size>
</register>
<register>
<access>read-only</access>
<addressOffset>0x4</addressOffset>
<displayName>flash_rd_sid</displayName>
<description>Perform read operation to extract flash device silicon ID and store the read back data. Only support in EPCS16 and EPCS64 flash devices. </description>
<name>flash_rd_sid</name>
<resetMask>0xffffffff</resetMask>
<resetValue>0x00000000</resetValue>
<size>32</size>
</register>
<register>
<access>read-only</access>
<addressOffset>0x8</addressOffset>
<displayName>flash_rd_rdid</displayName>
<description>Perform read operation to extract flash device memory capacity and store the read back data. </description>
<name>flash_rd_rdid</name>
<resetMask>0xffffffff</resetMask>
<resetValue>0x00000000</resetValue>
<size>32</size>
</register>
<register>
<access>write-only</access>
<addressOffset>0xc</addressOffset>
<displayName>flash_mem_op</displayName>
<description>To protect and erase memory </description>
<name>flash_mem_op</name>
<resetMask>0xffffffff</resetMask>
<resetValue>0x00000000</resetValue>
<size>32</size>
<fields>
<field>
<access>write-only</access>
<bitRange>[1:0]</bitRange>
<modifiedWriteValues>modify</modifiedWriteValues>
<name>memory_operation</name>
</field>
<field>
<access>write-only</access>
<bitRange>[23:8]</bitRange>
<modifiedWriteValues>modify</modifiedWriteValues>
<name>sector_value</name>
</field>
</fields>
</register>
<register>
<access>read-write</access>
<addressOffset>0x10</addressOffset>
<displayName>flash_isr</displayName>
<description>Interrupt status register </description>
<name>flash_isr</name>
<resetMask>0xffffffff</resetMask>
<resetValue>0x00000000</resetValue>
<size>32</size>
<fields>
<field>
<access>read-write</access>
<bitRange>[0:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>illegal_erase</name>
</field>
<field>
<access>read-write</access>
<bitRange>[1:1]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>illegal_write</name>
</field>
</fields>
</register>
<register>
<access>read-write</access>
<addressOffset>0x14</addressOffset>
<displayName>flash_imr</displayName>
<description>To mask of interrupt status register </description>
<name>flash_imr</name>
<resetMask>0xffffffff</resetMask>
<resetValue>0x00000000</resetValue>
<size>32</size>
<fields>
<field>
<access>read-write</access>
<bitRange>[0:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>m_illegal_erase</name>
</field>
<field>
<access>read-write</access>
<bitRange>[1:1]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>m_illegal_write</name>
</field>
</fields>
</register>
<register>
<access>write-only</access>
<addressOffset>0x18</addressOffset>
<displayName>flash_chip_select</displayName>
<description>Chip select values </description>
<name>flash_chip_select</name>
<resetMask>0xffffffff</resetMask>
<resetValue>0x00000000</resetValue>
<size>32</size>
<fields>
<field>
<access>write-only</access>
<bitRange>[0:0]</bitRange>
<modifiedWriteValues>modify</modifiedWriteValues>
<name>chip_select_bit_1</name>
</field>
<field>
<access>write-only</access>
<bitRange>[1:1]</bitRange>
<modifiedWriteValues>modify</modifiedWriteValues>
<name>chip_select_bit_2</name>
</field>
<field>
<access>write-only</access>
<bitRange>[2:2]</bitRange>
<modifiedWriteValues>modify</modifiedWriteValues>
<name>chip_select_bit_3</name>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>q_sys_button_pio_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>32</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DATA</name>
<displayName>Data</displayName>
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>data</name>
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIRECTION</name>
<displayName>Direction</displayName>
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>direction</name>
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IRQ_MASK</name>
<displayName>Interrupt mask</displayName>
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>interruptmask</name>
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EDGE_CAP</name>
<displayName>Edge capture</displayName>
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>edgecapture</name>
<description>Edge detection for each input port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SET_BIT</name>
<displayName>Outset</displayName>
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outset</name>
<description>Specifies which bit of the output port to set.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CLEAR_BITS</name>
<displayName>Outclear</displayName>
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outclear</name>
<description>Specifies which output bit to clear.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>

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FPGA_firmware/q_sys/synthesis/q_sys.v
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365
FPGA_firmware/q_sys/synthesis/submodules/MM_to_ST_Adapter.v
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// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This logic recieves Avalon Memory Mapped read data and translates it into
the Avalon Streaming format. The ST format requires all data to be packed
until the final transfer when packet support is enabled. As a result when
you enable unaligned acceses the data from two sucessive reads must be
combined to form a single word of data. If you disable packet support
and unaligned access support this block will synthesize into wires.
This block does not provide any read throttling as it simply acts as a format
adapter between the read master port and the read master FIFO. All throttling
should be provided by the read master to prevent overflow. Since this logic
sits on the MM side of the FIFO the bytes are in 'little endian' format and
will get swapped around on the other side of the FIFO (symbol size can be adjusted
there too).
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address and length signals
instead to determine how much out of alignment the master begins.
2.1 Changed the extra last access logic to be based on the descriptor address
and length as apposed to the counter values. Created a new 'length_counter'
input to determine when the last read has arrived.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module MM_to_ST_Adapter (
clk,
reset,
length,
length_counter,
address,
reads_pending,
start,
readdata,
readdatavalid,
fifo_data,
fifo_write,
fifo_empty,
fifo_sop,
fifo_eop
);
parameter DATA_WIDTH = 32; // 8, 16, 32, 64, 128, or 256 are valid values (if 8 is used then disable unaligned accesses and turn on full word only accesses)
parameter LENGTH_WIDTH = 32;
parameter ADDRESS_WIDTH = 32;
parameter BYTE_ADDRESS_WIDTH = 2; // log2(DATA_WIDTH/8)
parameter READS_PENDING_WIDTH = 5;
parameter EMPTY_WIDTH = 2; // log2(DATA_WIDTH/8)
parameter PACKET_SUPPORT = 1; // when set to 1 eop, sop, and empty will be driven, otherwise they will be grounded
// only set one of these at a time
parameter UNALIGNED_ACCESS_ENABLE = 1; // when set to 1 this block will support packets and starting/ending on any boundary, do not use this if DATA_WIDTH is 8 (use 'FULL_WORD_ACCESS_ONLY')
parameter FULL_WORD_ACCESS_ONLY = 0; // when set to 1 this block will assume only full words are arriving (must start and stop on a word boundary).
input clk;
input reset;
input [LENGTH_WIDTH-1:0] length;
input [LENGTH_WIDTH-1:0] length_counter;
input [ADDRESS_WIDTH-1:0] address;
input [READS_PENDING_WIDTH-1:0] reads_pending;
input start; // one cycle strobe at the start of a transfer used to capture bytes_to_transfer
input [DATA_WIDTH-1:0] readdata;
input readdatavalid;
output wire [DATA_WIDTH-1:0] fifo_data;
output wire fifo_write;
output wire [EMPTY_WIDTH-1:0] fifo_empty;
output wire fifo_sop;
output wire fifo_eop;
// internal registers and wires
reg [DATA_WIDTH-1:0] readdata_d1;
reg readdatavalid_d1;
wire [DATA_WIDTH-1:0] data_in; // data_in will either be readdata or a pipelined copy of readdata depending on whether unaligned access support is enabled
wire valid_in; // valid in will either be readdatavalid or a pipelined copy of readdatavalid depending on whether unaligned access support is enabled
reg valid_in_d1;
wire [DATA_WIDTH-1:0] barrelshifter_A; // shifted current read data
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1; // shifted previously read data
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
wire extra_access_enable;
reg extra_access;
wire last_unaligned_fifo_write;
reg first_access_seen;
reg second_access_seen;
wire first_access_seen_rising_edge;
wire second_access_seen_rising_edge;
reg [BYTE_ADDRESS_WIDTH-1:0] byte_address;
reg [EMPTY_WIDTH-1:0] last_empty; // only the last word written into the FIFO can have empty bytes
reg start_and_end_same_cycle; // when the amount of data to transfer is only a full word or less
generate
if (UNALIGNED_ACCESS_ENABLE == 1) // unaligned so using a pipelined input
begin
assign data_in = readdata_d1;
assign valid_in = readdatavalid_d1;
end
else
begin
assign data_in = readdata; // no barrelshifters in this case so pipelining is not necessary
assign valid_in = readdatavalid;
end
endgenerate
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else
begin
if (readdatavalid == 1)
begin
readdata_d1 <= readdata;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdatavalid_d1 <= 0;
valid_in_d1 <= 0;
end
else
begin
readdatavalid_d1 <= readdatavalid;
valid_in_d1 <= valid_in; // used to flush the pipeline (extra fifo write) and prolong eop for one additional clock cycle
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (valid_in == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_access_seen <= 0;
end
else
begin
if (start == 1)
begin
first_access_seen <= 0;
end
else if (valid_in == 1)
begin
first_access_seen <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
second_access_seen <= 0;
end
else
begin
if (start == 1)
begin
second_access_seen <= 0;
end
else if ((first_access_seen == 1) & (valid_in == 1))
begin
second_access_seen <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
byte_address <= 0;
end
else if (start == 1)
begin
byte_address <= address[BYTE_ADDRESS_WIDTH-1:0];
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
last_empty <= 0;
end
else if (start == 1)
begin
last_empty <= ((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}; // if length isn't a multiple of the word size then we'll have some empty symbols/bytes during the last fifo write
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
extra_access <= 0;
end
else if (start == 1)
begin
extra_access <= extra_access_enable; // when set the number of reads and fifo writes are equal, otherwise there will be 1 less fifo write than reads (unaligned accesses only)
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_and_end_same_cycle <= 0;
end
else if (start == 1)
begin
start_and_end_same_cycle <= (length <= (DATA_WIDTH/8));
end
end
/* These barrelshifters will take the unaligned data coming into this block and shift the byte lanes appropriately to form a single packed word.
Zeros are shifted into the byte lanes that do not contain valid data for the combined word that will be buffered. This allows both barrelshifters
to be logically OR'ed together to form a single packed word. Shifter A is used to shift the current read data towards the upper bytes of the
combined word (since those are the upper addresses of the combined word). Shifter B after the pipeline stage called 'barrelshifter_B_d1' contains
the previously read data shifted towards the lower bytes (since those are the lower addresses of the combined word).
*/
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = data_in << (8 * ((DATA_WIDTH/8) - input_offset));
assign barrelshifter_input_B[input_offset] = data_in >> (8 * input_offset);
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[byte_address]; // upper portion of the packed word
assign barrelshifter_B = barrelshifter_input_B[byte_address]; // lower portion of the packed word (will be pipelined so it will be the previous word read by the master)
assign combined_word = (barrelshifter_A | barrelshifter_B_d1); // barrelshifters shift in zeros so we can just OR the words together here to create a packed word
assign first_access_seen_rising_edge = (valid_in == 1) & (first_access_seen == 0);
assign second_access_seen_rising_edge = ((first_access_seen == 1) & (valid_in == 1)) & (second_access_seen == 0);
assign extra_access_enable = (((DATA_WIDTH/8) - length[EMPTY_WIDTH-1:0]) & {EMPTY_WIDTH{1'b1}}) >= address[BYTE_ADDRESS_WIDTH-1:0]; // enable when empty >= byte address
/* Need to keep track of the last write to the FIFO so that we can fire EOP correctly as well as flush the pipeline when unaligned accesses
is enabled. The first read is filtered since it is considered to be only a partial word to be written into the FIFO but there are cases
when there is extra data that is buffered in 'barrelshifter_B_d1' but the transfer is done so we need to issue an additional write.
In general for every 'N' Avalon-MM reads 'N-1' writes to the FIFO will occur unless there is data still buffered in which one more write
to the FIFO will immediately follow the last read.
*/
assign last_unaligned_fifo_write = (reads_pending == 0) & (length_counter == 0) &
( ((extra_access == 0) & (valid_in == 1)) | // don't need a pipeline flush
((extra_access == 1) & (valid_in_d1 == 1) & (valid_in == 0)) ); // last write to flush the pipeline (need to make sure valid_in isn't asserted to make sure the last data is indeed coming since valid_in is pipelined)
// This block should be optimized down depending on the packet support or access type settings. In the case where packet support is off
// and only full accesses are used this block should become zero logic elements.
generate
if (PACKET_SUPPORT == 1)
begin
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_sop = (second_access_seen_rising_edge == 1) | ((start_and_end_same_cycle == 1) & (last_unaligned_fifo_write == 1));
assign fifo_eop = last_unaligned_fifo_write;
assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word
end
else
begin
assign fifo_sop = first_access_seen_rising_edge;
assign fifo_eop = (length_counter == 0) & (reads_pending == 1) & (valid_in == 1); // not using last_unaligned_fifo_write since it's pipelined and when unaligned accesses are disabled the input is not pipelined
if (FULL_WORD_ACCESS_ONLY == 1)
begin
assign fifo_empty = 0; // full accesses so no empty symbols throughout the transfer
end
else
begin
assign fifo_empty = (fifo_eop == 1)? last_empty : 0; // always full accesses until the last word
end
end
end
else
begin
assign fifo_eop = 0;
assign fifo_sop = 0;
assign fifo_empty = 0;
end
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_data = combined_word;
assign fifo_write = (first_access_seen == 1) & ((valid_in == 1) | (last_unaligned_fifo_write == 1)); // last_unaligned_fifo_write will inject an extra pulse right after the last read occurs when flushing of the pipeline is needed
end
else
begin // don't need to pipeline since the data will not go through the barrel shifters
assign fifo_data = data_in; // don't need to barrelshift when aligned accesses are used
assign fifo_write = valid_in; // the number of writes to the fifo needs to always equal the number of reads from memory
end
endgenerate
endmodule

154
FPGA_firmware/q_sys/synthesis/submodules/ST_to_MM_Adapter.v
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// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This logic recieves registers the byte address of the master when 'start'
is asserted. This block then barrelshifts the write data based on the byte
address to make sure that the input data (from the FIFO) is reformatted to
line up with memory properly.
The only throttling mechanism in this block is the FIFO not empty signal as
well as waitreqeust from the fabric.
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
much out of alignment the master begins.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule

253
FPGA_firmware/q_sys/synthesis/submodules/afi_mux_ddr3_ddrx.v
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@ -1,253 +0,0 @@
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// Filename: afi_mux.v
// This module contains a set of muxes between the sequencer AFI signals and the controller AFI signals
// During calibration, mux_sel = 1, sequencer AFI signals are selected
// After calibration is succesfu, mux_sel = 0, controller AFI signals are selected
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module afi_mux_ddr3_ddrx (
clk,
mux_sel,
afi_addr,
afi_ba,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dm,
afi_wlat,
afi_rlat,
afi_rst_n,
afi_dqs_burst,
afi_wdata,
afi_wdata_valid,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
afi_cal_success,
afi_cal_fail,
seq_mux_addr,
seq_mux_ba,
seq_mux_cs_n,
seq_mux_cke,
seq_mux_odt,
seq_mux_ras_n,
seq_mux_cas_n,
seq_mux_we_n,
seq_mux_dm,
seq_mux_rst_n,
seq_mux_dqs_burst,
seq_mux_wdata,
seq_mux_wdata_valid,
seq_mux_rdata_en,
seq_mux_rdata_en_full,
seq_mux_rdata,
seq_mux_rdata_valid,
phy_mux_addr,
phy_mux_ba,
phy_mux_cs_n,
phy_mux_cke,
phy_mux_odt,
phy_mux_ras_n,
phy_mux_cas_n,
phy_mux_we_n,
phy_mux_dm,
phy_mux_wlat,
phy_mux_rlat,
phy_mux_rst_n,
phy_mux_dqs_burst,
phy_mux_wdata,
phy_mux_wdata_valid,
phy_mux_rdata_en,
phy_mux_rdata_en_full,
phy_mux_rdata,
phy_mux_rdata_valid,
phy_mux_cal_success,
phy_mux_cal_fail
);
parameter AFI_ADDR_WIDTH = 0;
parameter AFI_BANKADDR_WIDTH = 0;
parameter AFI_CS_WIDTH = 0;
parameter AFI_CLK_EN_WIDTH = 0;
parameter AFI_ODT_WIDTH = 0;
parameter AFI_WLAT_WIDTH = 0;
parameter AFI_RLAT_WIDTH = 0;
parameter AFI_RRANK_WIDTH = 0;
parameter AFI_WRANK_WIDTH = 0;
parameter AFI_DM_WIDTH = 0;
parameter AFI_CONTROL_WIDTH = 0;
parameter AFI_DQ_WIDTH = 0;
parameter AFI_WRITE_DQS_WIDTH = 0;
parameter AFI_RATE_RATIO = 0;
parameter MRS_MIRROR_PING_PONG_ATSO = 0;
input clk;
input mux_sel;
// AFI inputs from the controller
input [AFI_ADDR_WIDTH-1:0] afi_addr;
input [AFI_BANKADDR_WIDTH-1:0] afi_ba;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_CS_WIDTH-1:0] afi_cs_n;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_DM_WIDTH-1:0] afi_dm;
output [AFI_WLAT_WIDTH-1:0] afi_wlat;
output [AFI_RLAT_WIDTH-1:0] afi_rlat;
input [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
input [AFI_WRITE_DQS_WIDTH-1:0] afi_dqs_burst;
input [AFI_DQ_WIDTH-1:0] afi_wdata;
input [AFI_WRITE_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_RATE_RATIO-1:0] afi_rdata_en;
input [AFI_RATE_RATIO-1:0] afi_rdata_en_full;
output [AFI_DQ_WIDTH-1:0] afi_rdata;
output [AFI_RATE_RATIO-1:0] afi_rdata_valid;
output afi_cal_success;
output afi_cal_fail;
// AFI inputs from the sequencer
input [AFI_ADDR_WIDTH-1:0] seq_mux_addr;
input [AFI_BANKADDR_WIDTH-1:0] seq_mux_ba;
input [AFI_CS_WIDTH-1:0] seq_mux_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] seq_mux_cke;
input [AFI_ODT_WIDTH-1:0] seq_mux_odt;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_ras_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_cas_n;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_we_n;
input [AFI_DM_WIDTH-1:0] seq_mux_dm;
input [AFI_CONTROL_WIDTH-1:0] seq_mux_rst_n;
input [AFI_WRITE_DQS_WIDTH-1:0] seq_mux_dqs_burst;
input [AFI_DQ_WIDTH-1:0] seq_mux_wdata;
input [AFI_WRITE_DQS_WIDTH-1:0] seq_mux_wdata_valid;
input [AFI_RATE_RATIO-1:0] seq_mux_rdata_en;
input [AFI_RATE_RATIO-1:0] seq_mux_rdata_en_full;
output [AFI_DQ_WIDTH-1:0] seq_mux_rdata;
output [AFI_RATE_RATIO-1:0] seq_mux_rdata_valid;
// Mux output to the rest of the PHY logic
output [AFI_ADDR_WIDTH-1:0] phy_mux_addr;
output [AFI_BANKADDR_WIDTH-1:0] phy_mux_ba;
output [AFI_CS_WIDTH-1:0] phy_mux_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] phy_mux_cke;
output [AFI_ODT_WIDTH-1:0] phy_mux_odt;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_ras_n;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_cas_n;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_we_n;
output [AFI_DM_WIDTH-1:0] phy_mux_dm;
input [AFI_WLAT_WIDTH-1:0] phy_mux_wlat;
input [AFI_RLAT_WIDTH-1:0] phy_mux_rlat;
output [AFI_CONTROL_WIDTH-1:0] phy_mux_rst_n;
output [AFI_WRITE_DQS_WIDTH-1:0] phy_mux_dqs_burst;
output [AFI_DQ_WIDTH-1:0] phy_mux_wdata;
output [AFI_WRITE_DQS_WIDTH-1:0] phy_mux_wdata_valid;
output [AFI_RATE_RATIO-1:0] phy_mux_rdata_en;
output [AFI_RATE_RATIO-1:0] phy_mux_rdata_en_full;
input [AFI_DQ_WIDTH-1:0] phy_mux_rdata;
input [AFI_RATE_RATIO-1:0] phy_mux_rdata_valid;
input phy_mux_cal_success;
input phy_mux_cal_fail;
reg [AFI_ADDR_WIDTH-1:0] afi_addr_r;
reg [AFI_BANKADDR_WIDTH-1:0] afi_ba_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r;
reg [AFI_CLK_EN_WIDTH-1:0] afi_cke_r;
reg [AFI_CS_WIDTH-1:0] afi_cs_n_r;
reg [AFI_ODT_WIDTH-1:0] afi_odt_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_we_n_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_rst_n_r;
reg [AFI_ADDR_WIDTH-1:0] seq_mux_addr_r;
reg [AFI_BANKADDR_WIDTH-1:0] seq_mux_ba_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_cas_n_r;
reg [AFI_CLK_EN_WIDTH-1:0] seq_mux_cke_r;
reg [AFI_CS_WIDTH-1:0] seq_mux_cs_n_r;
reg [AFI_ODT_WIDTH-1:0] seq_mux_odt_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_ras_n_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_we_n_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_rst_n_r;
always @(posedge clk)
begin
afi_addr_r <= afi_addr;
afi_ba_r <= afi_ba;
afi_cs_n_r <= afi_cs_n;
afi_cke_r <= afi_cke;
afi_odt_r <= afi_odt;
afi_ras_n_r <= afi_ras_n;
afi_cas_n_r <= afi_cas_n;
afi_we_n_r <= afi_we_n;
afi_rst_n_r <= afi_rst_n;
seq_mux_addr_r <= seq_mux_addr;
seq_mux_ba_r <= seq_mux_ba;
seq_mux_cs_n_r <= seq_mux_cs_n;
seq_mux_cke_r <= seq_mux_cke;
seq_mux_odt_r <= seq_mux_odt;
seq_mux_ras_n_r <= seq_mux_ras_n;
seq_mux_cas_n_r <= seq_mux_cas_n;
seq_mux_we_n_r <= seq_mux_we_n;
seq_mux_rst_n_r <= seq_mux_rst_n;
end
wire [AFI_DQ_WIDTH-1:0] afi_wdata_int;
assign afi_rdata = phy_mux_rdata;
assign afi_wdata_int = afi_wdata;
assign afi_rdata_valid = mux_sel ? {AFI_RATE_RATIO{1'b0}} : phy_mux_rdata_valid;
assign seq_mux_rdata = phy_mux_rdata;
assign seq_mux_rdata_valid = phy_mux_rdata_valid;
assign phy_mux_addr = mux_sel ? seq_mux_addr_r : afi_addr_r;
assign phy_mux_ba = mux_sel ? seq_mux_ba_r : afi_ba_r;
assign phy_mux_cs_n = mux_sel ? seq_mux_cs_n_r : afi_cs_n_r;
assign phy_mux_cke = mux_sel ? seq_mux_cke_r : afi_cke_r;
assign phy_mux_odt = mux_sel ? seq_mux_odt_r : afi_odt_r;
assign phy_mux_ras_n = mux_sel ? seq_mux_ras_n_r : afi_ras_n_r;
assign phy_mux_cas_n = mux_sel ? seq_mux_cas_n_r : afi_cas_n_r;
assign phy_mux_we_n = mux_sel ? seq_mux_we_n_r : afi_we_n_r;
assign phy_mux_dm = mux_sel ? seq_mux_dm : afi_dm;
assign afi_wlat = phy_mux_wlat;
assign afi_rlat = phy_mux_rlat;
assign phy_mux_rst_n = mux_sel ? seq_mux_rst_n_r : afi_rst_n_r;
assign phy_mux_dqs_burst = mux_sel ? seq_mux_dqs_burst : afi_dqs_burst;
assign phy_mux_wdata = mux_sel ? seq_mux_wdata : afi_wdata_int;
assign phy_mux_wdata_valid = mux_sel ? seq_mux_wdata_valid : afi_wdata_valid;
assign phy_mux_rdata_en = mux_sel ? seq_mux_rdata_en : afi_rdata_en;
assign phy_mux_rdata_en_full = mux_sel ? seq_mux_rdata_en_full : afi_rdata_en_full;
assign afi_cal_success = phy_mux_cal_success;
assign afi_cal_fail = phy_mux_cal_fail;
endmodule

112
FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.sdc
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@ -1,112 +0,0 @@
## Generated SDC file "sum_peak.out.sdc"
## Copyright (C) 2019 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and any partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel FPGA IP License Agreement, or other applicable license
## agreement, including, without limitation, that your use is for
## the sole purpose of programming logic devices manufactured by
## Intel and sold by Intel or its authorized distributors. Please
## refer to the applicable agreement for further details, at
## https://fpgasoftware.intel.com/eula.
## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition"
## DATE "Mon Jul 31 13:54:17 2023"
##
## DEVICE "10M50DAF484C6GES"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clk_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk_clk}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {clk_clk}] -rise_to [get_clocks {clk_clk}] 0.020
set_clock_uncertainty -rise_from [get_clocks {clk_clk}] -fall_to [get_clocks {clk_clk}] 0.020
set_clock_uncertainty -fall_from [get_clocks {clk_clk}] -rise_to [get_clocks {clk_clk}] 0.020
set_clock_uncertainty -fall_from [get_clocks {clk_clk}] -fall_to [get_clocks {clk_clk}] 0.020
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

311
FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.sv
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@ -1,311 +0,0 @@
/*
This is for get data from sensor(avalon_streaming source)
And at the same time,
frame counter counts the frameID
bkg_sub do the bkg calibration and sub bkg depends on the frameID
and cluster_locate start to locate the position of cluster when the bkg_sub_on is 1
at the mean time
the data after bkg_sub is stored in ram4sig, as well as the first three words(I put it at address 500 to 502)
*/
`timescale 100 ps / 100 ps
module algo_reconstruction (
//Clock/reset
input wire clk_clk, // clk.clk
input wire rst_reset, // connect to int_reset from sensor_interface, to reset frameID to 0;
//avalon ST sink
input logic unsigned[31:0] data_in_data, // data_in.data
output wire data_in_ready, // .ready
input wire data_in_valid, // .valid
input wire [1:0] data_in_empty, // .empty
input wire data_in_endofpacket, // .endofpacket
input wire data_in_startofpacket, // .startofpacket
//avalon ST source
output wire [31:0] data_out_data, // data_out.data
output wire [1:0] data_out_empty, // .empty
output wire data_out_endofpacket, // .endofpacket
output wire data_out_startofpacket, // .startofpacket
input wire data_out_ready, // .ready the UDP is ready
output wire data_out_valid, // .valid
output wire[26:0] frameID, // for assign signal in tb simulation
output wire bkg_sub_on,
output wire rst_frame,
//data for sig after bkg subtraction
input wire sig_rdclk, //the read port for sig_ram
input wire[8:0] sig_rdaddress, //0~319 for data. 500~502 for the 3 words head
output wire[31:0] sig_out,
output reg sig_ram_last,
//the output of cluster_locate
output wire[8:0] sig_ch_left,
output wire[8:0] sig_ch_right,
output wire has_cluster,
output wire no_cluster
);
//set a frameID counter
//frameID + 1 at the rising edge of data_in_startofpacket
//wire[26:0] frameID;
frame_counter framectr(
.clk_clk(clk_clk),
.rst_reset(rst_reset),
.sig(data_in_startofpacket),
.frame_Num(frameID)
);
// *********************** ST interface ***********************
reg [4:0] state; //State of the state machine
localparam STATE_IDLE = 5'd0; //waiting for SOP
localparam STATE_WORD0 = 5'd1; //sending first word :
localparam STATE_WORD1 = 5'd2; //sending second word:
localparam STATE_WORD2 = 5'd3; //sending third word :
localparam STATE_DATA_PRO = 5'd4; //blocking data do calculation
localparam STATE_DATA_NEXT = 5'd7; //sending data
localparam STATE_LOC = 5'd5; //calculatebb
//Helper stuff
reg [15:0] tx_ctr; //counter of sent data words
localparam WORDS_TO_SEND = 163;
//the number of clocks for STATE_DATA_PRO
reg [5:0] delay_ctr;
localparam DELAY_CLOCKS = 3;
// for sum
reg[31:0] sum_all;
//the bkg-ram
wire[15:0] bkg_signal0;
wire[15:0] bkg_signal1;
wire[31:0] bkg_input_data;
//signal after subtract background
//got the background signal at the third clock in STATE_DATA_PRO
//and subtract it to 16 bit by giving up the LSM, i.e. divide 2.
reg [16:0] signal0_17bit;
reg [16:0] signal1_17bit;
wire[15:0] signal0;
wire[15:0] signal1;
assign signal0 = bkg_sub_on?signal0_17bit[16:1]:signal0_17bit[15:0];
assign signal1 = bkg_sub_on?signal1_17bit[16:1]:signal1_17bit[15:0];
bkg_ram bkg_but0(
.clk_clk(clk_clk),
.rst_reset(rst_reset),
.frameID(frameID[26:0]),
.address(tx_ctr[8:0]),
.data_in_data(bkg_input_data[31:16]),
.bkg_signal(bkg_signal0),
.bkg_sub_status(bkg_sub_on)
);
bkg_ram bkg_but1(
.clk_clk(clk_clk),
.rst_reset(rst_reset),
.frameID(frameID[26:0]),
.address(tx_ctr[8:0]),
.data_in_data(bkg_input_data[15:0]),
.bkg_signal(bkg_signal1)
);
assign bkg_input_data = (state==STATE_DATA_NEXT)?~data_in_data:15'b0;
//The state machine
always @(posedge clk_clk or posedge rst_reset)
begin
if (rst_reset)
begin
state <= STATE_IDLE;
end
else
case(state)
STATE_IDLE:
begin
if (data_in_startofpacket)
begin
state <= STATE_WORD0;
tx_ctr <= 0;
end
end
STATE_WORD0:
begin
if (data_out_ready)
begin
state <= STATE_WORD1;
tx_ctr <= tx_ctr+ 1'b1;
end
end
STATE_WORD1:
begin
if (data_out_ready)
begin
state <= STATE_WORD2;
tx_ctr <= tx_ctr +1'b1;
end
end
STATE_WORD2:
begin
if (data_out_ready)
begin
state <= STATE_DATA_PRO;
tx_ctr <= tx_ctr +1'b1;
delay_ctr <= DELAY_CLOCKS -1;
end
end
STATE_DATA_PRO:
begin
delay_ctr <= delay_ctr -1;
if (delay_ctr == 0)
begin
state <= STATE_DATA_NEXT;
delay_ctr <= DELAY_CLOCKS - 1;
signal0_17bit <= {1'b0,~data_in_data[31:16]}-{1'b0,bkg_signal0};
signal1_17bit <= {1'b0,~data_in_data[15:0]}-{1'b0,bkg_signal1};
end
end
STATE_DATA_NEXT:
begin
if (data_out_ready)
begin
tx_ctr <= tx_ctr+1'b1;
if (tx_ctr == WORDS_TO_SEND -1) //last word, size matches
state <= STATE_LOC;
else
state <= STATE_DATA_PRO;
end
end
STATE_LOC:
begin
state <= STATE_IDLE;
end
default:
begin
state <= STATE_IDLE;
end
endcase
end
assign data_in_ready = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT)&&data_out_ready;
assign data_out_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT) ? 1 : 0;
//assign data_out_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT)? data_in_data: 0;
assign data_out_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:
(state == STATE_DATA_NEXT)? {~signal0,~signal1}: 0;
assign data_out_startofpacket = data_in_startofpacket;
assign data_out_endofpacket = (state == STATE_DATA_NEXT & tx_ctr == WORDS_TO_SEND-1) ? 1 : 0;
assign data_out_empty = 0;
//the signal indicate the signal after bkg sub is ready or not
wire sub_bkg_signal_ready;
assign sub_bkg_signal_ready = (delay_ctr == 0)? 1 :0;
//the rst signal for every frame
//wire rst_frame;
assign rst_frame = data_in_startofpacket || rst_reset;
//the cluster_locating part
//it is built by the fact that regardless data_out_ready signal, the STATE_DATA_PRO will go to STATE_DATA_NEXT
//so the signal after bkg sub will continue at least two clocks
reg[8:0] cl_address;
wire[15:0] cl_data_in_data;
wire cl_data_in_valid;
// reg[8:0] ch_left;
// reg[8:0] ch_right;
// wire[8:0] sig_ch_left;
// wire[8:0] sig_ch_right;
// wire has_cluster;
// wire no_cluster;
cluster_locate cl_but(
.clk_clk(clk_clk),
.rst_reset(rst_frame),
.address(cl_address),
.data_in_data(cl_data_in_data),
.data_in_valid(cl_data_in_valid),
.sig_ch_left(sig_ch_left),
.sig_ch_right(sig_ch_right),
.has_cluster(has_cluster),
.no_cluster(no_cluster)
);
reg[2:0] state_clu;
localparam STATE_CLU_IDLE = 0;
localparam STATE_CLU_FIRST = 1;
localparam STATE_CLU_SECOND = 3;
assign cl_data_in_data = (state_clu == STATE_CLU_FIRST)? signal0:
(state_clu == STATE_CLU_SECOND)? signal1: 0;
assign cl_data_in_valid = (bkg_sub_on & (state_clu == STATE_CLU_FIRST || state_clu == STATE_CLU_SECOND))? 1'b1: 1'b0;
always @ (posedge clk_clk or posedge rst_frame)
begin
if (rst_frame)
begin
state_clu <= STATE_CLU_IDLE;
cl_address <= 9'b0;
end
else case(state_clu)
STATE_CLU_IDLE:
begin
if (sub_bkg_signal_ready)
state_clu <= STATE_CLU_FIRST;
end
STATE_CLU_FIRST:
begin
state_clu <= STATE_CLU_SECOND;
cl_address <= cl_address + 1'b1;
end
STATE_CLU_SECOND:
begin
state_clu <= STATE_CLU_IDLE;
cl_address <= cl_address + 1'b1;
end
default:
state_clu <= STATE_CLU_IDLE;
endcase
end
//when bkg_sub is not on, store the original data
//store the signal after bkg_sub in ram
//the first there words are at address 500~502
wire sig_ram_wren;
wire[31:0] sig_ram_data;
wire[8:0] sig_wraddress;
ram4sig sig_ram (
.data(sig_ram_data),
.rdaddress(sig_rdaddress),
.rdclock(sig_rdclk),
.wraddress(sig_wraddress),
.wrclock(clk_clk),
.wren(sig_ram_wren),
.q(sig_out)
);
assign sig_ram_wren = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state_clu == STATE_CLU_FIRST || state_clu == STATE_CLU_SECOND)? 1: 0;
assign sig_wraddress = (state == STATE_WORD0)? 9'd500:
(state == STATE_WORD1)? 9'd501:
(state == STATE_WORD2)? 9'd502: cl_address;
assign sig_ram_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data: {16'b0,cl_data_in_data};
assign sig_ram_last = (state == STATE_LOC)? 1'b1: 1'b0;
endmodule

329
FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction.v
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@ -1,329 +0,0 @@
// sum_interface.v
`timescale 1 ps / 1 ps
module algo_reconstruction (
//Clock/reset
input wire clk_clk, // clk.clk
input wire rst_reset, // rst.reset
//Avalon ST receiver
input wire [31:0] data_in_data, // data_in.data
output wire data_in_ready, // .ready
input wire data_in_valid, // .valid
input wire [1:0] data_in_empty, // .empty
input wire data_in_endofpacket, // .endofpacket
input wire data_in_startofpacket, // .startofpacket
//Avalon ST transmitter
output wire [31:0] data_out_data, // avalon_streaming_source.data
output wire data_out_endofpacket, // .endofpacket
output wire data_out_startofpacket, // .startofpacket
input wire data_out_ready, // .ready
output wire data_out_valid, // .valid
output wire [1:0] data_out_empty // .empty
);
// *********************** Internal reset logic ************************
/*
The internal reset signal derives from the reset input).
It drives all subcomponents but registers (which use simpy the reset input).
This signal is registered to be sure that no glitches from register bank pass.
*/
reg int_rst;
always @(posedge clk_clk)
begin
int_rst <= rst_reset;
end
//Very important globals
reg[31:0] rx_buffer[162:0]; //Data to receive: 3 words header plus sensor data
wire start_transmission; //pulsing this signal causes the Avalon ST link to start transmission
reg[31:0] transmit_buffer[162:0]; //DATA to transmit, the last word is Sum_all.
//********************** Avalon receiver ************************
/*
The receiver is used to receive data from sensor interface
And a simple calculation
*/
reg [1:0] data_in_state;
localparam DATA_IN_STATE_IDLE = 0; //waiting for high
// localparam DATA_IN_VALID = 5; //valid wait for start packet
localparam DATA_IN_STATE_RECEIVE = 1; //receiving data
localparam DATA_IN_STATE_FINISH = 3; // finish receiveing to run algorithm
localparam DATA_IN_STATE_LOCK = 2; //roll to IDLE
localparam WORDS_TO_RECEIVE = 163;
localparam WORDS_TO_SEND = 163;
integer i; //for generate loops
//registers to drive input pins of ST interfaces
reg reg_in_ready;
//Helper stuff
reg[15:0] rx_ctr; //counter of receive data worDS_TO_RECEIVE
reg[31:0] sum_all; //
reg[31:0] sum_high;
reg[31:0] sum_low;
//the threshold bkg subtraction process
wire[15:0] channel_ctr0; //channel_ctr<= 2*rx_ctr -6
wire[15:0] channel_ctr1;
assign channel_ctr0 = (rx_ctr>2'b00)? (((rx_ctr-2'b01)<<1)): 16'h1FE;
assign channel_ctr1 = channel_ctr0 + 1'b1;
wire[15:0] bkg0;
wire[15:0] bkg1;
//bkg bkg_inst0(
// .address ( channel_ctr0[8:0]),
// .clock ( clk_clk),
// .q ( bkg0)
// );
//
//bkg bkg_inst1(
// .address ( channel_ctr1[8:0]),
// .clock ( clk_clk),
// .q ( bkg1)
// );
//
rom_bkg rom_bkg_inst (
.address_a ( channel_ctr0[8:0] ),
.address_b ( channel_ctr1[8:0] ),
.clock ( clk_clk),
.q_a ( bkg0),
.q_b ( bkg1)
);
// The state machine
always @(posedge clk_clk or posedge int_rst)
begin
if(int_rst)
begin
data_in_state <= DATA_IN_STATE_IDLE;
sum_all <= 0;
sum_high <= 0;
sum_low <= 0;
end
else
case(data_in_state)
DATA_IN_STATE_IDLE:
begin
if (data_in_valid)
begin
data_in_state <= DATA_IN_STATE_RECEIVE;
rx_ctr <= 0;
sum_all <= 0;
sum_high <= 0;
sum_low <= 0;
end
end
DATA_IN_STATE_RECEIVE:
begin
if (data_in_valid & data_in_ready)
begin
rx_ctr <= rx_ctr+1;
sum_high <= sum_high + data_in_data[31:16];
sum_low <= sum_low+ data_in_data[15:0];
end
if (rx_ctr == (WORDS_TO_RECEIVE-1))
begin
data_in_state <= DATA_IN_STATE_FINISH;
sum_all <= sum_low +sum_high;
end
end
DATA_IN_STATE_FINISH:
begin
data_in_state <= DATA_IN_STATE_LOCK;
rx_ctr <= 0;
end
DATA_IN_STATE_LOCK:
begin
if (~data_in_valid)
data_in_state <= DATA_IN_STATE_IDLE;
end
default:
data_in_state <= DATA_IN_STATE_IDLE;
endcase
end
//Combinational Part
always @ (*)
begin
if (int_rst)
begin
reg_in_ready <= 0;
end
else
case(data_in_state)
DATA_IN_STATE_IDLE, DATA_IN_STATE_LOCK:
begin
reg_in_ready <= 0;
end
DATA_IN_STATE_RECEIVE:
begin
if (data_in_startofpacket)
reg_in_ready <= 1;
if (data_in_ready)
rx_buffer[rx_ctr] <= (rx_ctr>2'b10)?{data_in_data[31:16]-bkg0, data_in_data[15:0]-bkg1}:data_in_data[31:0];
end
DATA_IN_STATE_FINISH:
begin
reg_in_ready <= 0;
for (i = 0; i < (WORDS_TO_SEND-1); i = i+1)
begin
transmit_buffer[i] <= rx_buffer[i];
end
transmit_buffer[WORDS_TO_SEND-1] <= sum_all;
end
default:
begin
reg_in_ready <= 0;
end
endcase
end
assign data_in_ready = reg_in_ready;
//Generate Avalon trigger signal
assign start_transmission = (data_in_state == DATA_IN_STATE_FINISH) ? 1 : 0;
// *********************** Avalon transmitter ************************
/*
The transmitter is used to transmit collected sensor data together with sync frame.
It can be later packed into UDP by UDP generator and sent over Ethernet. Or whatever.
The transmitter has 8-bit symbol, 4 symbols per beat. It's backpressurizable and includes packet signals.
The Empty signal is dummy (always zero), as the data is always aligned to 32-bit size.
The transmission starts when the 'start_transmission' signal gets pulsed
*/
assign data_out_empty = 2'b00;
reg [1:0] data_out_state; //State of the state machine
localparam DATA_OUT_STATE_IDLE = 0; //waiting for high
localparam DATA_OUT_STATE_SEND = 1; //sending data
localparam DATA_OUT_STATE_LOCK = 2; //waiting for trigger low
//registers to drive output pins of ST interfaces
reg reg_valid;
reg [31:0] reg_data;
reg reg_startofpacket;
reg reg_endofpacket;
//Helper stuff
reg [15:0] tx_ctr; //counter of sent data words
//The state machine
always @(posedge clk_clk or posedge int_rst)
begin
if (int_rst)
data_out_state <= DATA_OUT_STATE_IDLE;
else
case(data_out_state)
DATA_OUT_STATE_IDLE:
begin
if (start_transmission)
begin
data_out_state <= DATA_OUT_STATE_SEND;
tx_ctr <= 0;
end
end
DATA_OUT_STATE_SEND:
begin
if (data_out_ready)
tx_ctr <= tx_ctr + 1;
if (tx_ctr == (WORDS_TO_SEND-1))
data_out_state <= DATA_OUT_STATE_LOCK;
end
DATA_OUT_STATE_LOCK:
begin
tx_ctr <= 0;
if (~start_transmission)
data_out_state <= DATA_OUT_STATE_IDLE;
end
default:
data_out_state <= DATA_OUT_STATE_IDLE;
endcase
end
//Driving bus signals
always @( *)
begin
if (int_rst)
begin
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
end
else
case(data_out_state)
DATA_OUT_STATE_IDLE, DATA_OUT_STATE_LOCK:
begin
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
end
DATA_OUT_STATE_SEND:
begin
reg_valid = 1;
reg_data[31:0] = transmit_buffer[tx_ctr];
if (tx_ctr == 0)
reg_startofpacket = 1;
else
reg_startofpacket = 0;
if (tx_ctr == (WORDS_TO_SEND-1))
begin
reg_endofpacket = 1;
end
else
reg_endofpacket = 0;
end
default:
begin
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
end
endcase
end
assign data_out_valid = reg_valid;
assign data_out_data = reg_data;
assign data_out_startofpacket = reg_startofpacket;
assign data_out_endofpacket = reg_endofpacket;
endmodule

349
FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction_bkg.v
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@ -1,349 +0,0 @@
// the interface between sensor_interface and UDP
// with a sum_signal operation
// with background subtraction
// background info is in rom_bkg
`timescale 1 ps / 1 ps
module algo_reconstruction (
//Clock/reset
input wire clk_clk, // clk.clk
input wire rst_reset, // rst.reset
//Avalon ST receiver
(* keep *)input wire [31:0] data_in_data, // data_in.data
output wire data_in_ready, // .ready
input wire data_in_valid, // .valid
input wire [1:0] data_in_empty, // .empty
input wire data_in_endofpacket, // .endofpacket
input wire data_in_startofpacket, // .startofpacket
//Avalon ST transmitter
output wire [31:0] data_out_data, // avalon_streaming_source.data
output wire data_out_endofpacket, // .endofpacket
output wire data_out_startofpacket, // .startofpacket
input wire data_out_ready, // .ready
output wire data_out_valid, // .valid
output wire [1:0] data_out_empty // .empty
);
// *********************** Internal reset logic ************************
/*
The internal reset signal derives from the reset input).
It drives all subcomponents but registers (which use simpy the reset input).
This signal is registered to be sure that no glitches from register bank pass.
*/
reg int_rst;
always @(posedge clk_clk)
begin
int_rst <= rst_reset;
end
//Very important globals
reg[31:0] rx_buffer[162:0]; //Data to receive: 3 words header plus sensor data
wire start_transmission; //pulsing this signal causes the Avalon ST link to start transmission
reg[31:0] transmit_buffer[162:0]; //DATA to transmit, the last word is Sum_all.
//********************** Avalon receiver ************************
/*
The receiver is used to receive data from sensor interface
And a simple calculation
*/
reg [1:0] data_in_state;
localparam DATA_IN_STATE_IDLE = 0; //waiting for high
// localparam DATA_IN_VALID = 5; //valid wait for start packet
localparam DATA_IN_STATE_RECEIVE = 1; //receiving data
localparam DATA_IN_STATE_FINISH = 3; // finish and to copy data from rx_buffer to transmit_buffer;
localparam DATA_IN_STATE_LOCK_ALGO = 2; // leave for algorithm; currently
localparam WORDS_TO_RECEIVE = 163;
localparam WORDS_TO_SEND = 163;
integer i; //for generate loops
//registers to drive input pins of ST interfaces
reg reg_in_ready;
//Helper stuff
reg[15:0] rx_ctr; //counter of receive data worDS_TO_RECEIVE
// for sum
reg[31:0] sum_all; //
reg[31:0] sum_high;
reg[31:0] sum_low;
//the threshold bkg subtraction process
wire[31:0] channel_ctr; //channel_ctr<= 2*rx_ctr
reg[31:0] reg_channel_ctr;
assign channel_ctr = reg_channel_ctr;
//assign channel_ctr0 = rx_ctr<<1;
//assign channel_ctr1 = channel_ctr0 + 1'b1;
wire[31:0] bkg;
wire[31:0] wire_bkg;
wire[31:0] wire_rx_buffer; // the first 3 channel is data_in_data
wire[31:0] wire_for_sum; //the first 3 channel is 0
rom_bkg rom_bkg_inst (
.address_a ( channel_ctr[24:16]),
.address_b ( channel_ctr[8:0] ),
.clock ( clk_clk),
.q_a ( bkg[31:16]),
.q_b ( bkg[15:0])
);
// The state machine
always @(posedge clk_clk or posedge int_rst)
begin
if(int_rst)
begin
data_in_state <= DATA_IN_STATE_IDLE;
end
else
case(data_in_state)
DATA_IN_STATE_IDLE:
begin
if (data_in_valid & data_in_startofpacket)
begin
data_in_state <= DATA_IN_STATE_RECEIVE;
end
end
DATA_IN_STATE_RECEIVE:
begin
if (data_in_endofpacket)
begin
data_in_state <= DATA_IN_STATE_LOCK_ALGO;
end
end
DATA_IN_STATE_FINISH:
begin
data_in_state <= DATA_IN_STATE_IDLE;
end
DATA_IN_STATE_LOCK_ALGO:
begin
if (~data_in_valid)
data_in_state <= DATA_IN_STATE_FINISH;
end
default:
data_in_state <= DATA_IN_STATE_IDLE;
endcase
end
//Sequential Part for registers
always @(posedge clk_clk or posedge int_rst)
begin
if(int_rst)
begin
rx_ctr <= 0;
sum_all <= 0;
sum_high <= 0;
sum_low <= 0;
end
else
case(data_in_state)
DATA_IN_STATE_IDLE:
begin
rx_ctr <= 0;
sum_all <= 0;
sum_high <= 0;
sum_low <= 0;
end
DATA_IN_STATE_RECEIVE:
begin
rx_ctr <= rx_ctr + 1'b1;
reg_channel_ctr[31:16] <= rx_ctr << 1;
reg_channel_ctr[15:0] <= (rx_ctr << 1) + 1'b1;
rx_buffer[rx_ctr] <= wire_rx_buffer;
sum_high <= sum_high + wire_for_sum[31:16];
sum_low <= sum_low + wire_for_sum[15:0];
end
DATA_IN_STATE_FINISH:
begin
for (i = 0; i < (WORDS_TO_SEND-1); i = i+1)
begin
transmit_buffer[i] <= rx_buffer[i];
end
transmit_buffer[WORDS_TO_SEND-1] <= sum_all;// I should add one more state for sum_all
end
DATA_IN_STATE_LOCK_ALGO:
begin
sum_all <= sum_high + sum_low;
end
endcase
end
assign wire_bkg = ((rx_ctr == 0) |(rx_ctr == 1)| (rx_ctr == 2))? 0: bkg;
assign wire_rx_buffer = {data_in_data[31:16]-wire_bkg[31:16], data_in_data[15:0]-wire_bkg[15:0]};
assign wire_for_sum = ((rx_ctr == 0) |(rx_ctr == 1) | (rx_ctr == 2))?32'b0:wire_rx_buffer;
//Combinational Part
always @ (*)
begin
if (int_rst)
begin
reg_in_ready <= 0;
end
else
case(data_in_state)
DATA_IN_STATE_IDLE:
begin
reg_in_ready <= 0;
end
DATA_IN_STATE_RECEIVE:
begin
reg_in_ready <= 1;
end
DATA_IN_STATE_FINISH, DATA_IN_STATE_LOCK_ALGO:
begin
reg_in_ready <= 0;
end
default:
begin
reg_in_ready <= 0;
end
endcase
end
assign data_in_ready = reg_in_ready;
//Generate Avalon trigger signal
assign start_transmission = (data_in_state == DATA_IN_STATE_FINISH) ? 1 : 0;
// *********************** Avalon transmitter ************************
/*
The transmitter is used to transmit collected sensor data together with sync frame.
It can be later packed into UDP by UDP generator and sent over Ethernet. Or whatever.
The transmitter has 8-bit symbol, 4 symbols per beat. It's backpressurizable and includes packet signals.
The Empty signal is dummy (always zero), as the data is always aligned to 32-bit size.
The transmission starts when the 'start_transmission' signal gets pulsed
*/
assign data_out_empty = 2'b00;
reg [1:0] data_out_state; //State of the state machine
localparam DATA_OUT_STATE_IDLE = 0; //waiting for high
localparam DATA_OUT_STATE_SEND = 1; //sending data
localparam DATA_OUT_STATE_LOCK = 2; //waiting for trigger low
//registers to drive output pins of ST interfaces
reg reg_valid;
reg [31:0] reg_data;
reg reg_startofpacket;
reg reg_endofpacket;
//Helper stuff
reg [15:0] tx_ctr; //counter of sent data words
//The state machine
always @(posedge clk_clk or posedge int_rst)
begin
if (int_rst)
begin
data_out_state <= DATA_OUT_STATE_IDLE;
end
else
case(data_out_state)
DATA_OUT_STATE_IDLE:
begin
if (start_transmission)
begin
data_out_state <= DATA_OUT_STATE_SEND;
tx_ctr <= 0;
end
end
DATA_OUT_STATE_SEND:
begin
if (data_out_ready)
tx_ctr <= tx_ctr + 1;
if (tx_ctr == (WORDS_TO_SEND-1))
data_out_state <= DATA_OUT_STATE_LOCK;
end
DATA_OUT_STATE_LOCK:
begin
tx_ctr <= 0;
if (~start_transmission)
data_out_state <= DATA_OUT_STATE_IDLE;
end
default:
begin
data_out_state <= DATA_OUT_STATE_IDLE;
end
endcase
end
//Driving bus signals
always @( *)
begin
if (int_rst)
begin
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
end
else
case(data_out_state)
DATA_OUT_STATE_IDLE, DATA_OUT_STATE_LOCK:
begin
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
end
DATA_OUT_STATE_SEND:
begin
reg_data[31:0] = transmit_buffer[tx_ctr];
reg_valid = 1;
if (tx_ctr == 0)
reg_startofpacket = 1;
else
reg_startofpacket = 0;
if (tx_ctr == (WORDS_TO_SEND-1))
begin
reg_endofpacket = 1;
end
else
reg_endofpacket = 0;
end
default:
begin
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
end
endcase
end
assign data_out_valid = reg_valid;
assign data_out_data = reg_data;
assign data_out_startofpacket = reg_startofpacket;
assign data_out_endofpacket = reg_endofpacket;
endmodule

283
FPGA_firmware/q_sys/synthesis/submodules/algo_reconstruction_interface.v
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@ -1,283 +0,0 @@
// the interface between sensor_interface and UDP packet
// avalon_streaming sink and source
// words to send/receive is 163
`timescale 1 ps / 1 ps
module algo_reconstruction (
//Clock/reset
input wire clk_clk, // clk.clk
input wire rst_reset, // rst.reset
//Avalon ST receiver
input wire [31:0] data_in_data, // data_in.data
output wire data_in_ready, // .ready
input wire data_in_valid, // .valid
input wire [1:0] data_in_empty, // .empty
input wire data_in_endofpacket, // .endofpacket
input wire data_in_startofpacket, // .startofpacket
//Avalon ST transmitter
output wire [31:0] data_out_data, // avalon_streaming_source.data
output wire data_out_endofpacket, // .endofpacket
output wire data_out_startofpacket, // .startofpacket
input wire data_out_ready, // .ready
output wire data_out_valid, // .valid
output wire [1:0] data_out_empty // .empty
);
// *********************** Internal reset logic ************************
/*
The internal reset signal derives from the reset input).
It drives all subcomponents but registers (which use simpy the reset input).
This signal is registered to be sure that no glitches from register bank pass.
*/
reg int_rst;
always @(posedge clk_clk)
begin
int_rst <= rst_reset;
end
//Very important globals
reg[31:0] rx_buffer[162:0]; //Data to receive: 3 words header plus sensor data
wire start_transmission; //pulsing this signal causes the Avalon ST link to start transmission
reg[31:0] transmit_buffer[162:0]; //DATA to transmit
//********************** Avalon receiver ************************
reg [1:0] data_in_state;
localparam DATA_IN_STATE_IDLE = 0; //waiting for high
localparam DATA_IN_STATE_RECEIVE = 1; //receiving data
localparam DATA_IN_STATE_FINISH = 3; // finish receiveing to run algorithm
localparam DATA_IN_STATE_LOCK = 2; //roll to IDLE
localparam WORDS_TO_RECEIVE = 163;
localparam WORDS_TO_SEND = 163;
integer i; //for generate loops
//registers to drive input pins of ST interfaces
reg reg_in_ready;
//Helper stuff
reg[15:0] rx_ctr; //counter of receive data worDS_TO_RECEIVE
// The state machine
always @(posedge clk_clk or posedge int_rst)
begin
if(int_rst)
begin
data_in_state <= DATA_IN_STATE_IDLE;
end
else
case(data_in_state)
DATA_IN_STATE_IDLE:
begin
if (data_in_valid)
begin
data_in_state <= DATA_IN_STATE_RECEIVE;
rx_ctr <= 0;
end
end
DATA_IN_STATE_RECEIVE:
begin
if (data_in_valid & data_in_ready)
begin
rx_ctr <= rx_ctr+1;
end
if (rx_ctr == (WORDS_TO_RECEIVE-1))
begin
data_in_state <= DATA_IN_STATE_FINISH;
end
end
DATA_IN_STATE_FINISH:
begin
data_in_state <= DATA_IN_STATE_LOCK;
rx_ctr <= 0;
end
DATA_IN_STATE_LOCK:
begin
if (~data_in_valid)
data_in_state <= DATA_IN_STATE_IDLE;
end
default:
data_in_state <= DATA_IN_STATE_IDLE;
endcase
end
//Combinational Part
always @ (*)
begin
if (int_rst)
begin
reg_in_ready <= 0;
end
else
case(data_in_state)
DATA_IN_STATE_IDLE, DATA_IN_STATE_LOCK:
begin
reg_in_ready <= 0;
end
DATA_IN_STATE_RECEIVE:
begin
if (data_in_startofpacket)
reg_in_ready <= 1;
if (data_in_ready)
rx_buffer[rx_ctr] <= data_in_data[31:0];
end
DATA_IN_STATE_FINISH:
begin
reg_in_ready <= 0;
for (i = 0; i < (WORDS_TO_SEND); i = i+1)
begin
transmit_buffer[i] <= rx_buffer[i];
end
end
default:
begin
reg_in_ready <= 0;
end
endcase
end
assign data_in_ready = reg_in_ready;
//Generate Avalon trigger signal
assign start_transmission = (data_in_state == DATA_IN_STATE_FINISH) ? 1 : 0;
// *********************** Avalon transmitter ************************
/*
The transmitter is used to transmit collected sensor data together with sync frame.
It can be later packed into UDP by UDP generator and sent over Ethernet. Or whatever.
The transmitter has 8-bit symbol, 4 symbols per beat. It's backpressurizable and includes packet signals.
The Empty signal is dummy (always zero), as the data is always aligned to 32-bit size.
The transmission starts when the 'start_transmission' signal gets pulsed
*/
assign data_out_empty = 2'b00;
reg [1:0] data_out_state; //State of the state machine
localparam DATA_OUT_STATE_IDLE = 0; //waiting for high
localparam DATA_OUT_STATE_SEND = 1; //sending data
localparam DATA_OUT_STATE_LOCK = 2; //waiting for trigger low
//registers to drive output pins of ST interfaces
reg reg_valid;
reg [31:0] reg_data;
reg reg_startofpacket;
reg reg_endofpacket;
//Helper stuff
reg [15:0] tx_ctr; //counter of sent data words
//The state machine
always @(posedge clk_clk or posedge int_rst)
begin
if (int_rst)
data_out_state <= DATA_OUT_STATE_IDLE;
else
case(data_out_state)
DATA_OUT_STATE_IDLE:
begin
if (start_transmission)
begin
data_out_state <= DATA_OUT_STATE_SEND;
tx_ctr <= 0;
end
end
DATA_OUT_STATE_SEND:
begin
if (data_out_ready)
tx_ctr <= tx_ctr + 1;
if (tx_ctr == (WORDS_TO_SEND-1))
data_out_state <= DATA_OUT_STATE_LOCK;
end
DATA_OUT_STATE_LOCK:
begin
tx_ctr <= 0;
if (~start_transmission)
data_out_state <= DATA_OUT_STATE_IDLE;
end
default:
data_out_state <= DATA_OUT_STATE_IDLE;
endcase
end
//Driving bus signals
always @( *)
begin
if (int_rst)
begin
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
end
else
case(data_out_state)
DATA_OUT_STATE_IDLE, DATA_OUT_STATE_LOCK:
begin
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
end
DATA_OUT_STATE_SEND:
begin
reg_valid = 1;
reg_data[31:0] = transmit_buffer[tx_ctr];
if (tx_ctr == 0)
reg_startofpacket = 1;
else
reg_startofpacket = 0;
if (tx_ctr == (WORDS_TO_SEND-1))
begin
reg_endofpacket = 1;
end
else
reg_endofpacket = 0;
end
default:
begin
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
end
endcase
end
assign data_out_valid = reg_valid;
assign data_out_data = reg_data;
assign data_out_startofpacket = reg_startofpacket;
assign data_out_endofpacket = reg_endofpacket;
endmodule

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FPGA_firmware/q_sys/synthesis/submodules/algo_state.sv
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@ -1,202 +0,0 @@
// algo_state
/*
Takes an input stream and calculate some value
Remarks:
- The transfer is performed on the fly, without buffering. Input gets backpressed when needed
*/
`timescale 100 ps / 100 ps
module algo_reconstruction (
//Clock/reset
input wire clk_clk, // clk.clk
input wire rst_reset, // rst.reset
//avalon ST sink
input wire [31:0] data_in_data, // data_in.data
output wire data_in_ready, // .ready
input wire data_in_valid, // .valid
input wire [1:0] data_in_empty, // .empty
input wire data_in_endofpacket, // .endofpacket
input wire data_in_startofpacket, // .startofpacket
//avalon ST source
output wire [31:0] data_out_data, // data_out.data
output wire [1:0] data_out_empty, // .empty
output wire data_out_endofpacket, // .endofpacket
output wire data_out_startofpacket, // .startofpacket
input wire data_out_ready, // .ready
output wire data_out_valid // .valid
);
// *********************** ST interface ***********************
reg [4:0] state; //State of the state machine
localparam STATE_IDLE = 0; //waiting for SOP
localparam STATE_WORD0 = 1; //sending first word :
localparam STATE_WORD1 = 2; //sending second word:
localparam STATE_WORD2 = 3; //sending third word :
localparam STATE_DATA = 4; //sending data
localparam STATE_CALC = 5; //calculate
localparam STATE_RESULT = 6; //send result//LAST_WORDS
reg reg_ready; //registers to drive output pins of ST interfaces
reg reg_valid;
reg [31:0] reg_data;
reg reg_startofpacket;
reg reg_endofpacket;
reg reg_empty;
//Helper stuff
reg [15:0] tx_ctr; //counter of sent data words
localparam WORDS_TO_SEND = 163;
// for sum
reg[31:0] sum_all;
//The state machine
always @(posedge clk_clk or posedge rst_reset)
begin
if (rst_reset)
begin
state <= STATE_IDLE;
end
else
case(state)
STATE_IDLE:
begin
if (data_in_startofpacket)
begin
state <= STATE_WORD0;
tx_ctr <= 0;
end
end
STATE_WORD0, STATE_WORD1,STATE_WORD2:
begin
if (data_out_ready & data_in_valid)
begin
state <= state + 1;
tx_ctr <= tx_ctr +1;
end
end
STATE_DATA:
begin
if (data_out_ready && data_in_valid)
begin
tx_ctr <= tx_ctr+1;
if (tx_ctr == WORDS_TO_SEND -2) //last word, size matches
state <= STATE_CALC;
end
end
STATE_CALC:
begin
sum_all <= 32'h1199;
state <= STATE_RESULT;
end
STATE_RESULT:
begin
if (data_out_ready)
begin
tx_ctr <= tx_ctr+1;
state <= STATE_IDLE;
end
end
default:
begin
state <= STATE_IDLE;
end
endcase
end
//Driving bus signals
always_comb
begin
if (rst_reset)
begin
reg_ready = 0;
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
reg_empty = 0;
end
else
case(state)
STATE_IDLE:
begin
reg_ready = 0;
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
reg_empty = 0;
end
STATE_WORD0:
begin
reg_ready = data_out_ready;
reg_valid = 1;
reg_data = data_in_data;
reg_startofpacket = 1;
reg_endofpacket = 0;
reg_empty = 0;
end
STATE_WORD1,STATE_WORD2:
begin
reg_ready = 1;
reg_valid = 1;
reg_data = data_in_data;
reg_startofpacket = 0;
reg_endofpacket = 0;
reg_empty = 0;
end
STATE_DATA:
begin
reg_ready = 1;
reg_valid = 1;
reg_data = data_in_data;
reg_startofpacket = 0;
reg_endofpacket = 0;
reg_empty = 0;
end
STATE_CALC:
begin
reg_ready = 1;
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
reg_empty = 0;
end
STATE_RESULT:
begin
reg_ready = 0;
reg_valid = 1;
reg_data = sum_all;
reg_startofpacket = 0;
reg_endofpacket = 1;
reg_empty = 0;
end
default:
begin
reg_ready = 0;
reg_valid = 0;
reg_data = 0;
reg_startofpacket = 0;
reg_endofpacket = 0;
reg_empty = 0;
end
endcase
end
assign data_in_ready = reg_ready;
assign data_out_valid = reg_valid;
assign data_out_data = reg_data;
assign data_out_startofpacket = reg_startofpacket;
assign data_out_endofpacket = reg_endofpacket;
assign data_out_empty = reg_empty;
endmodule

352
FPGA_firmware/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v
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//module algo_top_cl_cali_rms
//combine bkg_subtraction, cluster_locate, and calibration, and rms
//tested with algo_top_cl_cali_rms_tb.v
module algo_top_cl_cali_rms(
//clock and reset
input wire clk,
input wire rst, // connect to rst_run
//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence // 163 word = 3 header + 160 data
input wire [31:0] data_in_data, // st.data
output wire data_in_ready, // .ready
input wire data_in_valid, // .valid
input wire [1:0] data_in_empty, // .empty
input wire data_in_endofpacket, // .endofpacket
input wire data_in_startofpacket, // .startofpacket
//avalon ST(Streaming) source: 0 readlatency and 0 readallowence // 3 + 160 + 4 = 167 words * 32bit
output wire [31:0] to_udp_data, // st.data
input wire to_udp_ready, // .ready
output wire to_udp_valid, // .valid
output wire [1:0] to_udp_empty, // .empty
output wire to_udp_endofpacket, // .endofpacket
output wire to_udp_startofpacket , // .startofpacket
//Avalon MM slave
input wire [1:0] csr_address, // avalon_slave.address
input wire csr_read, // .read
output wire [31:0] csr_readdata, // .readdata
input wire csr_write, // .write
input wire [31:0] csr_writedata, // .writedata
input wire [3:0] csr_byteenable, // .byteenable
//for cluster => will be in register map
input wire [7:0] CL_THRESHOLD,
input wire [7:0] CL_SIZE,
input wire [7:0] IN_ALGO_THRESHOLD,
//the interface with cali_ram (storing cali factor) Avalon-MM: read califac from this ram; output is not registered
output wire [8:0] address,
output wire clken,
input wire [15:0] cali_fac,
input wire waitrequest
);
//avalon source for header
wire [31:0] header_data;
wire header_ready;
wire [1:0] header_empty;
wire header_endofpacket;
wire header_startofpacket;
wire header_valid;
//avalon source for channel data
wire [31:0] channel_data;
wire channel_ready;
wire [1:0] channel_empty;
wire channel_endofpacket;
wire channel_startofpacket;
wire channel_valid;
//avalon source for result
wire [31:0] recon_data;
wire recon_ready;
wire [1:0] recon_empty;
wire recon_endofpacket;
wire recon_startofpacket;
wire recon_valid;
/******************** merge three data source together *****************************************/
reg [1:0] avalon_sender_state;
localparam STATE_IDLE = 2'd0;
localparam STATE_HEADER = 2'd1;
localparam STATE_CHANNEL = 2'd3;
localparam STATE_RECON = 2'd2;
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
avalon_sender_state <= STATE_IDLE;
end
else case(avalon_sender_state)
STATE_IDLE:
begin
if (header_startofpacket)
avalon_sender_state <= STATE_HEADER;
end
STATE_HEADER:
begin
if (channel_startofpacket)
avalon_sender_state <= STATE_CHANNEL;
end
STATE_CHANNEL:
begin
if (recon_startofpacket)
avalon_sender_state <= STATE_RECON;
end
STATE_RECON:
begin
if (recon_endofpacket && to_udp_ready)
avalon_sender_state <= STATE_IDLE;
end
default:
avalon_sender_state <= STATE_IDLE;
endcase
end
assign to_udp_data = (avalon_sender_state == STATE_HEADER)? header_data: (avalon_sender_state == STATE_CHANNEL)? channel_data: (avalon_sender_state == STATE_RECON)? recon_data: 32'd0;
assign header_ready = (avalon_sender_state == STATE_HEADER)? to_udp_ready: 1'b0;
assign channel_ready = (avalon_sender_state == STATE_CHANNEL)? to_udp_ready: 1'b0;
assign recon_ready = (avalon_sender_state == STATE_RECON)? to_udp_ready: 1'b0;
assign to_udp_empty = 2'b0;
assign to_udp_startofpacket = (avalon_sender_state == STATE_HEADER)? header_startofpacket: 1'b0;
assign to_udp_endofpacket = (avalon_sender_state == STATE_RECON)? recon_endofpacket: 1'b0;
assign to_udp_valid = (avalon_sender_state == STATE_HEADER)? header_valid: (avalon_sender_state == STATE_CHANNEL)? channel_valid: (avalon_sender_state == STATE_RECON)? recon_valid: 1'b0;
wire [31:0] wire_data0;
wire wire_ready0;
wire wire_valid0;
wire [1:0] wire_empty0;
wire wire_endofpacket0;
wire wire_startofpacket0;
wire bkg_sub_on;
bkg_subtraction_pipe #(.BKG_FRAME(8192)) bkg_subtraction0( //4 for simulation, 8192 for real firmware setup
.clk (clk),
.rst (rst),
.data_in_data (data_in_data),
.data_in_ready (data_in_ready),
.data_in_valid (data_in_valid),
.data_in_empty (data_in_empty),
.data_in_startofpacket (data_in_startofpacket),
.data_in_endofpacket (data_in_endofpacket),
.data_out_data (wire_data0),
.data_out_empty (wire_empty0),
.data_out_endofpacket (wire_endofpacket0),
.data_out_startofpacket (wire_startofpacket0),
.data_out_ready (wire_ready0),
.data_out_valid (wire_valid0),
.bkg_sub_on (bkg_sub_on),
//3 header
.to_udp_data (header_data),
.to_udp_ready(header_ready),
.to_udp_valid (header_valid),
.to_udp_empty (header_empty),
.to_udp_endofpacket (header_endofpacket),
.to_udp_startofpacket (header_startofpacket)
);
wire [15:0] wire_data1;
wire wire_ready1;
wire wire_valid1;
wire wire_empty1;
wire wire_endofpacket1;
wire wire_startofpacket1;
stl2sts stl2sts0(
.clk (clk),
.rst (rst),
.data_in_data (wire_data0),
.data_in_ready (wire_ready0),
.data_in_valid (wire_valid0),
.data_in_empty (wire_empty0),
.data_in_startofpacket (wire_startofpacket0),
.data_in_endofpacket (wire_endofpacket0),
.data_out_data (wire_data1),
.data_out_empty (wire_empty1),
.data_out_endofpacket (wire_endofpacket1),
.data_out_startofpacket (wire_startofpacket1),
.data_out_ready (wire_ready1),
.data_out_valid (wire_valid1)
);
//from st_splitter0 to cluster_locate
wire [15:0] wire_data2;
wire wire_ready2;
wire wire_valid2;
wire wire_empty2;
wire wire_endofpacket2;
wire wire_startofpacket2;
//from st_splitter0 to calibration
wire [15:0] wire_data3;
wire wire_ready3;
wire wire_valid3;
wire wire_empty3;
wire wire_endofpacket3;
wire wire_startofpacket3;
st_splitter16 st_splitter0 (
.st_splitter16_clk_clk (clk), // st_splitter16_clk.clk
.st_splitter16_reset_reset (rst), // st_splitter16_reset.reset
.st_splitter16_in_ready (wire_ready1), // st_splitter16_in.ready
.st_splitter16_in_valid (wire_valid1), // .valid
.st_splitter16_in_startofpacket (wire_startofpacket1), // .startofpacket
.st_splitter16_in_endofpacket (wire_endofpacket1), // .endofpacket
.st_splitter16_in_empty (wire_empty1), // .empty
.st_splitter16_in_data (wire_data1), // .data
.st_splitter16_out0_ready (wire_ready2), // st_splitter16_out0.ready
.st_splitter16_out0_valid (wire_valid2), // .valid
.st_splitter16_out0_startofpacket (wire_startofpacket2), // .startofpacket
.st_splitter16_out0_endofpacket (wire_endofpacket2), // .endofpacket
.st_splitter16_out0_empty (wire_empty2), // .empty
.st_splitter16_out0_data (wire_data2), // .data
.st_splitter16_out1_ready (wire_ready3), // st_splitter16_out1.ready
.st_splitter16_out1_valid (wire_valid3), // .valid
.st_splitter16_out1_startofpacket (wire_startofpacket3), // .startofpacket
.st_splitter16_out1_endofpacket (wire_endofpacket3), // .endofpacket
.st_splitter16_out1_empty (wire_empty3), // .empty
.st_splitter16_out1_data (wire_data3) // .data
);
wire[8:0] sig_ch_left;
wire[8:0] sig_ch_right;
wire has_cluster;
wire no_cluster;
wire cl_last_channel;
cluster_locate cluster_locate0(
.clk (clk),
.rst (rst),
.data_in_data (wire_data2),
.data_in_ready (wire_ready2),
.data_in_valid (wire_valid2),
.data_in_empty (wire_empty2),
.data_in_startofpacket (wire_startofpacket2),
.data_in_endofpacket (wire_endofpacket2),
.THRESHOLD ({8'b0,CL_THRESHOLD}),
.SIZE ({1'b0,CL_SIZE}),
.sig_ch_left (sig_ch_left),
.sig_ch_right (sig_ch_right),
.has_cluster (has_cluster),
.no_cluster (no_cluster),
.data_in_last (cl_last_channel)
);
wire[8:0] data_caled_address;
wire [15:0] data_caled;
wire data_caled_rd_enable;
//when bkg_sub_on is off, it equals to 8192.... the scaled 1 for calibration factor
wire [15:0] cali_fac_masked = bkg_sub_on? cali_fac:16'd8192;
calibration calibration0(
.clk(clk),
.rst(rst),
.data_in_data (wire_data3),
.data_in_ready (wire_ready3),
.data_in_valid (wire_valid3),
.data_in_empty (wire_empty3),
.data_in_startofpacket (wire_startofpacket3),
.data_in_endofpacket (wire_endofpacket3),
.address (address),
.clken (clken),
.cali_fac (cali_fac_masked),
.waitrequest(waitrequest),
.data_caled_address(data_caled_address),
.data_caled(data_caled),
.data_caled_rd_enable(data_caled_rd_enable),
.to_udp_data (channel_data),
.to_udp_ready(channel_ready),
.to_udp_valid (channel_valid),
.to_udp_empty (channel_empty),
.to_udp_endofpacket (channel_endofpacket),
.to_udp_startofpacket (channel_startofpacket)
);
rms rms0(
.clk(clk),
.rst(rst),
.bkg_sub_on (bkg_sub_on),
.sig_ram_last (cl_last_channel),
.sig_rdaddress(data_caled_address),
.sig(data_caled),
.sig_rd_eable(data_caled_rd_enable),
.sig_ch_left (sig_ch_left),
.sig_ch_right (sig_ch_right),
.has_cluster (has_cluster),
.no_cluster (no_cluster),
.to_udp_data (recon_data),
.to_udp_ready(recon_ready),
.to_udp_valid (recon_valid),
.to_udp_empty (recon_empty),
.to_udp_endofpacket (recon_endofpacket),
.to_udp_startofpacket (recon_startofpacket)
);
endmodule

563
FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v
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@ -1,563 +0,0 @@
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : (DDR1/2/3,LPDDR1) address and command decoder
//
// File : alt_mem_ddrx_addr_cmd.v
//
// Abstract : Address and command decoder
///////////////////////////////////////////////////////////////////////////////
//altera message_off 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_addr_cmd
# (parameter
// Global parameters
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CKE_WIDTH = 1, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 16, // max supported address bits, must be >= row bits (For ddr3 >=13 even if row=12)
CFG_MEM_IF_ROW_WIDTH = 16, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_CTL_RATE = "FULL",
CFG_DWIDTH_RATIO = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
//run-time configuration interface
cfg_type,
cfg_output_regd,
cfg_enable_chipsel_for_sideband, // to indicate should we de-assert cs_n for sideband signal (self refresh and deep power down specific)
// AFI interface (Signals from Arbiter block)
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_auto_precharge,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_zq_cal,
bg_do_lmr,
bg_do_burst_terminate, //Currently does not exist in arbiter
bg_do_deep_pdown, //Currently does not exist in arbiter
// address information
bg_to_chip, // active high input (one hot)
bg_to_bank,
bg_to_row,
bg_to_col,
bg_to_lmr, //Currently doesn not exist in arbiter
lmr_opcode,
//output to PHY
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_rst_n
);
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input ctl_cal_success;
//run-time configuration input
input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type;
input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
input cfg_enable_chipsel_for_sideband;
// Arbiter command inputs
input bg_do_write;
input bg_do_read;
input bg_do_burst_chop;
input bg_do_auto_precharge;
input bg_do_activate;
input bg_do_precharge;
input [CFG_MEM_IF_CHIP-1:0] bg_do_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] bg_do_refresh;
input [CFG_MEM_IF_CHIP-1:0] bg_do_self_refresh;
input [CFG_MEM_IF_CHIP-1:0] bg_do_power_down;
input [CFG_MEM_IF_CHIP-1:0] bg_do_zq_cal;
input bg_do_lmr;
input bg_do_burst_terminate;
input [CFG_MEM_IF_CHIP-1:0] bg_do_deep_pdown;
input [CFG_MEM_IF_CHIP-1:0] bg_to_chip;
input [CFG_MEM_IF_BA_WIDTH-1:0] bg_to_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] bg_to_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] bg_to_col;
input [CFG_MEM_IF_BA_WIDTH-1:0] bg_to_lmr;
input [CFG_MEM_IF_ADDR_WIDTH-1:0] lmr_opcode;
//output
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
wire bg_do_read;
wire bg_do_burst_chop;
wire bg_do_auto_precharge;
wire bg_do_activate;
wire bg_do_precharge;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_precharge_all;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_refresh;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_self_refresh;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_power_down;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_zq_cal;
wire bg_do_lmr;
wire [CFG_MEM_IF_CHIP-1:0] bg_do_deep_pdown;
wire bg_do_burst_terminate;
reg [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
reg [CFG_MEM_IF_CHIP-1:0] do_power_down;
reg [CFG_MEM_IF_CHIP-1:0] do_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] do_self_refresh_r;
reg [CFG_MEM_IF_CHIP-1:0] do_power_down_r;
reg [CFG_MEM_IF_CHIP-1:0] do_deep_pdown_r;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] int_cs_n;
reg int_ras_n;
reg int_cas_n;
reg int_we_n;
reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] int_ba;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke ;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n ;
reg combi_ras_n;
reg combi_cas_n;
reg combi_we_n ;
reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] combi_ba ;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr ;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke_r ;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n_r ;
reg combi_ras_n_r;
reg combi_cas_n_r;
reg combi_we_n_r ;
reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] combi_ba_r ;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr_r ;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_row;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] temp_col;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_col;
wire col12;
wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_col_r;
reg [CFG_MEM_IF_CHIP-1:0] chip_in_self_refresh;
//=================================================================================================//
generate
if (CFG_MEM_IF_ADDR_WIDTH > CFG_MEM_IF_ROW_WIDTH)
begin
assign int_row = {{(CFG_MEM_IF_ADDR_WIDTH - CFG_MEM_IF_ROW_WIDTH){1'b0}},bg_to_row};
end
else
begin
assign int_row = bg_to_row;
end
endgenerate
assign temp_col = {{(CFG_MEM_IF_ADDR_WIDTH - CFG_MEM_IF_COL_WIDTH){1'b0}},bg_to_col};
assign afi_rst_n = {(CFG_DWIDTH_RATIO/2){1'b1}};
assign col12 = (cfg_type == `MMR_TYPE_DDR3) ? ~bg_do_burst_chop : temp_col[11]; //DDR3
generate
if (CFG_MEM_IF_ADDR_WIDTH < 13)
begin
assign int_col = {temp_col[CFG_MEM_IF_ADDR_WIDTH-1:10],bg_do_auto_precharge,temp_col[9:0]};
end
else if (CFG_MEM_IF_ADDR_WIDTH == 13)
begin
assign int_col = {col12,temp_col[10],bg_do_auto_precharge,temp_col[9:0]};
end
else
begin
assign int_col = {temp_col[CFG_MEM_IF_ADDR_WIDTH-3:11],col12,temp_col[10],bg_do_auto_precharge,temp_col[9:0]};
end
endgenerate
generate
if (CFG_DWIDTH_RATIO == 2)
begin
assign afi_cke = int_cke;
assign afi_cs_n = int_cs_n;
assign afi_ras_n = int_ras_n;
assign afi_cas_n = int_cas_n;
assign afi_we_n = int_we_n;
assign afi_ba = int_ba;
assign afi_addr = int_addr;
end
else
begin
assign afi_cke = {int_cke,int_cke_r};
assign afi_cs_n = {int_cs_n,{CFG_MEM_IF_CHIP{1'b1}}}; // to provide time for addr bus to settle at high freq, cs sent on 2nd phase
assign afi_ras_n = {int_ras_n,int_ras_n};
assign afi_cas_n = {int_cas_n,int_cas_n};
assign afi_we_n = {int_we_n,int_we_n};
assign afi_ba = {int_ba,int_ba};
assign afi_addr = {int_addr,int_addr};
end
endgenerate
always @(posedge ctl_clk, negedge ctl_reset_n) // aligns cke with cs for slf rfsh & pwrdwn(lpddr1)which is defined only when cs_n goes low
begin
if (!ctl_reset_n)
int_cke_r <= {(CFG_MEM_IF_CKE_WIDTH){1'b0}};
else
int_cke_r <= int_cke;
end
always @(posedge ctl_clk, negedge ctl_reset_n) // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
begin
if (!ctl_reset_n)
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
else
if ((bg_do_self_refresh) || (bg_do_deep_pdown && cfg_type == `MMR_TYPE_LPDDR1)) //LPDDDR1
chip_in_self_refresh <= bg_to_chip;
else
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
combi_cke_r <= {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n_r <= {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n_r <= 1'b1;
combi_cas_n_r <= 1'b1;
combi_we_n_r <= 1'b1;
combi_ba_r <= {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr_r <= {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
else
begin
combi_cke_r <= combi_cke;
combi_cs_n_r <= combi_cs_n;
combi_ras_n_r <= combi_ras_n;
combi_cas_n_r <= combi_cas_n;
combi_we_n_r <= combi_we_n;
combi_ba_r <= combi_ba;
combi_addr_r <= combi_addr;
end
end
always @(*)
begin
if (cfg_output_regd)
begin
int_cke = combi_cke_r;
int_cs_n = combi_cs_n_r;
int_ras_n = combi_ras_n_r;
int_cas_n = combi_cas_n_r;
int_we_n = combi_we_n_r;
int_ba = combi_ba_r;
int_addr = combi_addr_r;
end
else
begin
int_cke = combi_cke;
int_cs_n = combi_cs_n;
int_ras_n = combi_ras_n;
int_cas_n = combi_cas_n;
int_we_n = combi_we_n;
int_ba = combi_ba;
int_addr = combi_addr;
end
end
//CKE generation block
always @(*)
begin
if (ctl_cal_success)
begin
combi_cke = ~(bg_do_self_refresh | bg_do_power_down | bg_do_deep_pdown);
end
else
begin
combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
end
end
//Pulse generator for self refresh, power down and deep power down
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_self_refresh_r <= {(CFG_MEM_IF_CHIP){1'b0}};
do_power_down_r <= {(CFG_MEM_IF_CHIP){1'b0}};
do_deep_pdown_r <= {(CFG_MEM_IF_CHIP){1'b0}};
end
else
begin
do_self_refresh_r <= ~bg_do_self_refresh;
do_power_down_r <= ~bg_do_power_down;
do_deep_pdown_r <= ~bg_do_deep_pdown;
end
end
always @(*)
begin
do_self_refresh = bg_do_self_refresh & do_self_refresh_r;
do_power_down = bg_do_power_down & do_power_down_r;
do_deep_pdown = bg_do_deep_pdown & do_deep_pdown_r;
end
always @(*) //All Command inputs are mutually exclusive
begin
if (ctl_cal_success)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; //Should we put default condition into if(!bg_do_refresh && !bg_do_activate....)??
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
if (|bg_do_refresh)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_do_refresh;
combi_ras_n = 1'b0;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|bg_do_precharge_all)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_do_precharge_all;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = bg_to_bank;
combi_addr[10]= 1'b1;
end
if (bg_do_activate)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = bg_to_bank;
combi_addr = int_row;
end
if (bg_do_precharge)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = bg_to_bank;
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (bg_do_write)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b0;
combi_we_n = 1'b0;
combi_ba = bg_to_bank;
combi_addr = int_col;
end
if (bg_do_read)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
combi_ba = bg_to_bank;
combi_addr = int_col;
end
if (|do_power_down)
begin
// combi_cke = ~bg_to_chip;
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|do_deep_pdown) //Put assertion for memory type ddr2 and ddr3 as an error
begin
// combi_cke = ~bg_to_chip;
if (cfg_enable_chipsel_for_sideband)
begin
combi_cs_n = ~do_deep_pdown; // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
end
else
begin
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
end
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|do_self_refresh)
begin
// combi_cke = ~bg_to_chip;
if (cfg_enable_chipsel_for_sideband)
begin
combi_cs_n = ~do_self_refresh; // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode
end
else
begin
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
end
combi_ras_n = 1'b0;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
if (|bg_do_zq_cal) // Only short zqcal supported
begin
if (cfg_type == `MMR_TYPE_DDR3) //DDR3
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_do_zq_cal;
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
else // Should we flag error or issue as NOP
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
if (bg_do_lmr)
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; // to support chng rfsh time based on temp
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b0;
combi_we_n = 1'b0;
combi_ba = bg_to_lmr;
combi_addr = lmr_opcode;
end
if (bg_do_burst_terminate)
begin
if (cfg_type == `MMR_TYPE_LPDDR1) //lpddr1
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~bg_to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
else
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
end
else
begin
// combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
endmodule

808
FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v
View File

@ -1,808 +0,0 @@
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_addr_cmd_wrap
# ( parameter
CFG_MEM_IF_CHIP = 2,
CFG_MEM_IF_CKE_WIDTH = 2, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 16, // max supported address bits, must be >= row bits
CFG_MEM_IF_ROW_WIDTH = 16, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_LPDDR2_ENABLED = 1,
CFG_PORT_WIDTH_TYPE = 3,
CFG_DWIDTH_RATIO = 2,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_LOCAL_ID_WIDTH = 8,
CFG_DATA_ID_WIDTH = 4,
CFG_INT_SIZE_WIDTH = 4,
CFG_ODT_ENABLED = 1,
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_PORT_WIDTH_CAS_WR_LAT = 5,
CFG_PORT_WIDTH_TCL = 5,
CFG_PORT_WIDTH_ADD_LAT = 5,
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4,
CFG_PORT_WIDTH_OUTPUT_REGD = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
cfg_type,
cfg_tcl,
cfg_cas_wr_lat,
cfg_add_lat,
cfg_write_odt_chip,
cfg_read_odt_chip,
cfg_burst_length,
cfg_output_regd_for_afi_output,
// burst generator command signals
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_lmr_read,
bg_do_refresh_1bank,
bg_do_zq_cal,
bg_do_lmr,
bg_localid,
bg_dataid,
bg_size,
// burst generator address signals
bg_to_chip, // active high input (one hot)
bg_to_bank,
bg_to_row,
bg_to_col,
bg_to_lmr,
lmr_opcode,
//output
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_ba,
afi_addr,
afi_rst_n,
afi_odt
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam CFG_FR_DWIDTH_RATIO = 2;
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk ;
input ctl_reset_n ;
input ctl_cal_success ;
//run-time csr chain input
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type ;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl ;
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat ;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat ;
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip ;
input [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip ;
input [4:0] cfg_burst_length ;
//output regd signal from rdwr_tmg block
input [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd_for_afi_output;
//command inputs
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col ;
input bg_do_lmr_read ;
input bg_do_refresh_1bank ;
input [7:0] bg_to_lmr ;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid ;
input [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid ;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size ;
input [CFG_MEM_IF_ADDR_WIDTH-1:0] lmr_opcode ;
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke ;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n ;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba ;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n ;
output [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_odt ;
// -----------------------------
// port type declaration
// -----------------------------
reg [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke ;
reg [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n ;
reg [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba ;
reg [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n ;
reg [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_odt ;
// -----------------------------
// signal declaration
// -----------------------------
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rmw_correct ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rmw_partial ;
wire [CFG_MEM_IF_CKE_WIDTH - 1:0] int_afi_cke [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_CHIP- 1:0] int_afi_cs_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_ras_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_cas_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_we_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_BA_WIDTH - 1:0] int_afi_ba [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_ADDR_WIDTH-1:0] int_afi_addr [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rst_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rmw_correct [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rmw_partial [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_CKE_WIDTH - 1:0] int_afi_cke_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_CHIP- 1:0] int_afi_cs_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_ras_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_cas_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_we_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_BA_WIDTH - 1:0] int_afi_ba_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_ADDR_WIDTH-1:0] int_afi_addr_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_rst_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_rmw_correct_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_rmw_partial_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_cke ;
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_cs_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_ras_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_cas_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_we_n ;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_ba ;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_addr ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rst_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rmw_correct ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rmw_partial ;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_cs_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_ras_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_cas_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_ba;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_rst_n;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_write ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_read ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_burst_chop ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_burst_terminate ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_auto_precharge ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_correct ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_partial ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_activate ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_precharge ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_correct_r ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_partial_r ;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_precharge_all [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_refresh [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_self_refresh [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_power_down [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_deep_pdown [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_zq_cal [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_lmr ;
reg [CFG_MEM_IF_CHIP -1:0] int_bg_to_chip [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH -1:0] int_bg_to_bank [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH -1:0] int_bg_to_row [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH -1:0] int_bg_to_col [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] int_bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_bg_size;
reg int_bg_do_lmr_read;
reg int_bg_do_refresh_1bank;
wire [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0] afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0] mux_afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] cfg_enable_chipsel_for_sideband;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh_r;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown_r;
wire one = 1'b1;
wire zero = 1'b0;
// -----------------------------
// module definition
// -----------------------------
genvar afi_j, afi_n;
generate
// map int_afi_* multi-dimensional array signals to afi_* output port signals
for (afi_n = 0; afi_n < (CFG_DWIDTH_RATIO/2); afi_n = afi_n + 1'b1)
begin : gen_afi_signals
always @ (*)
begin
if (cfg_output_regd_for_afi_output == 2)
begin
afi_cke [((afi_n+1) * CFG_MEM_IF_CKE_WIDTH) -1 : (afi_n * CFG_MEM_IF_CKE_WIDTH)] = int_afi_cke_r [afi_n] ;
afi_cs_n [((afi_n+1) * CFG_MEM_IF_CHIP) -1 : (afi_n * CFG_MEM_IF_CHIP)] = int_afi_cs_n_r [afi_n] ;
afi_ras_n [afi_n] = int_afi_ras_n_r [afi_n] ;
afi_cas_n [afi_n] = int_afi_cas_n_r [afi_n] ;
afi_we_n [afi_n] = int_afi_we_n_r [afi_n] ;
afi_ba [((afi_n+1) * CFG_MEM_IF_BA_WIDTH) -1 : (afi_n * CFG_MEM_IF_BA_WIDTH)] = int_afi_ba_r [afi_n] ;
afi_addr [((afi_n+1) * CFG_MEM_IF_ADDR_WIDTH)-1 : (afi_n * CFG_MEM_IF_ADDR_WIDTH)] = int_afi_addr_r [afi_n] ;
afi_rst_n [afi_n] = int_afi_rst_n_r [afi_n] ;
afi_rmw_correct [afi_n] = int_afi_rmw_correct_r [afi_n] ;
afi_rmw_partial [afi_n] = int_afi_rmw_partial_r [afi_n] ;
end
else
begin
afi_cke [((afi_n+1) * CFG_MEM_IF_CKE_WIDTH) -1 : (afi_n * CFG_MEM_IF_CKE_WIDTH)] = int_afi_cke [afi_n] ;
afi_cs_n [((afi_n+1) * CFG_MEM_IF_CHIP) -1 : (afi_n * CFG_MEM_IF_CHIP)] = int_afi_cs_n [afi_n] ;
afi_ras_n [afi_n] = int_afi_ras_n [afi_n] ;
afi_cas_n [afi_n] = int_afi_cas_n [afi_n] ;
afi_we_n [afi_n] = int_afi_we_n [afi_n] ;
afi_ba [((afi_n+1) * CFG_MEM_IF_BA_WIDTH) -1 : (afi_n * CFG_MEM_IF_BA_WIDTH)] = int_afi_ba [afi_n] ;
afi_addr [((afi_n+1) * CFG_MEM_IF_ADDR_WIDTH)-1 : (afi_n * CFG_MEM_IF_ADDR_WIDTH)] = int_afi_addr [afi_n] ;
afi_rst_n [afi_n] = int_afi_rst_n [afi_n] ;
afi_rmw_correct [afi_n] = int_afi_rmw_correct [afi_n] ;
afi_rmw_partial [afi_n] = int_afi_rmw_partial [afi_n] ;
end
end
end
// generate int_afi_* signals based on CFG_DWIDTH_RATIO & CFG_AFI_INTF_PHASE_NUM
if (CFG_DWIDTH_RATIO == 2)
begin
// full rate, with any phase
assign int_afi_cke [0] = fr_afi_cke ;
assign int_afi_cs_n [0] = fr_afi_cs_n ;
assign int_afi_ras_n [0] = fr_afi_ras_n ;
assign int_afi_cas_n [0] = fr_afi_cas_n ;
assign int_afi_we_n [0] = fr_afi_we_n ;
assign int_afi_ba [0] = fr_afi_ba ;
assign int_afi_addr [0] = fr_afi_addr ;
assign int_afi_rst_n [0] = fr_afi_rst_n ;
assign int_afi_rmw_correct [0] = fr_afi_rmw_correct ;
assign int_afi_rmw_partial [0] = fr_afi_rmw_partial ;
end
else if ((CFG_DWIDTH_RATIO/2) == CFG_AFI_INTF_PHASE_NUM)
begin
// map phase_afi_* signals to int_afi_* signals
// half rate , with phase=2
// quarter rate, with phase=4
for (afi_j = 0; afi_j < CFG_AFI_INTF_PHASE_NUM; afi_j = afi_j + 1'b1)
begin : gen_afi_signals_0
assign int_afi_cke [afi_j] = phase_afi_cke [afi_j] ;
assign int_afi_cs_n [afi_j] = phase_afi_cs_n [afi_j] ;
assign int_afi_ras_n [afi_j] = phase_afi_ras_n [afi_j] ;
assign int_afi_cas_n [afi_j] = phase_afi_cas_n [afi_j] ;
assign int_afi_we_n [afi_j] = phase_afi_we_n [afi_j] ;
assign int_afi_ba [afi_j] = phase_afi_ba [afi_j] ;
assign int_afi_addr [afi_j] = phase_afi_addr [afi_j] ;
assign int_afi_rst_n [afi_j] = phase_afi_rst_n [afi_j] ;
assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j] ;
assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j] ;
end
end
else // only supports case CFG_AFI_INTF_PHASE_NUM < (CFG_DWIDTH_RATIO/2)
begin
// map phase_afi_* signals to selected int_afi_* signals, and drive the rest to default values
// for cs_n signals:
// half rate , with phase=1, drives int_afi_* 1 only
// quarter rate , with phase=2, drives int_afi_* 1 & 3
// for other signals:
// half rate , with phase=1, drives int_afi_* 0 & 1 with the same value
// quarter rate , with phase=2, drives int_afi_* 0 & 1 or 2 & 3 with the same value
// Why? to improve timing margin on PHY side
for (afi_j = 0; afi_j < (CFG_DWIDTH_RATIO/2); afi_j = afi_j + 1)
begin : gen_afi_signals_1
// Assign even phase with '1' because we only issue on odd phase (2T timing)
assign int_afi_cs_n [afi_j] = ((afi_j % CFG_AFI_INTF_PHASE_NUM) == 1) ? phase_afi_cs_n [afi_j / CFG_AFI_INTF_PHASE_NUM] : { CFG_MEM_IF_CHIP {1'b1} };
// Assign the last CKE with phase_afi_cs_n[1], the rest with phase_afi_cs_n[0]
assign int_afi_cke [afi_j] = (afi_j == ((CFG_DWIDTH_RATIO/2) - 1)) ? phase_afi_cke [1] : phase_afi_cke [0];
assign int_afi_ras_n [afi_j] = phase_afi_ras_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_cas_n [afi_j] = phase_afi_cas_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_we_n [afi_j] = phase_afi_we_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_ba [afi_j] = phase_afi_ba [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_addr [afi_j] = phase_afi_addr [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rst_n [afi_j] = phase_afi_rst_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j / CFG_AFI_INTF_PHASE_NUM];
end
end
for (afi_j = 0; afi_j < (CFG_DWIDTH_RATIO/2); afi_j = afi_j + 1)
begin : gen_afi_signals_r
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_afi_cke_r [afi_j] <= 0;
int_afi_cs_n_r [afi_j] <= 0;
int_afi_ras_n_r [afi_j] <= 0;
int_afi_cas_n_r [afi_j] <= 0;
int_afi_we_n_r [afi_j] <= 0;
int_afi_ba_r [afi_j] <= 0;
int_afi_addr_r [afi_j] <= 0;
int_afi_rst_n_r [afi_j] <= 0;
int_afi_rmw_correct_r [afi_j] <= 0;
int_afi_rmw_partial_r [afi_j] <= 0;
end
else
begin
int_afi_cke_r [afi_j] <= int_afi_cke [afi_j];
int_afi_cs_n_r [afi_j] <= int_afi_cs_n [afi_j];
int_afi_ras_n_r [afi_j] <= int_afi_ras_n [afi_j];
int_afi_cas_n_r [afi_j] <= int_afi_cas_n [afi_j];
int_afi_we_n_r [afi_j] <= int_afi_we_n [afi_j];
int_afi_ba_r [afi_j] <= int_afi_ba [afi_j];
int_afi_addr_r [afi_j] <= int_afi_addr [afi_j];
int_afi_rst_n_r [afi_j] <= int_afi_rst_n [afi_j];
int_afi_rmw_correct_r [afi_j] <= int_afi_rmw_correct [afi_j];
int_afi_rmw_partial_r [afi_j] <= int_afi_rmw_partial [afi_j];
end
end
end
endgenerate
// phase_afi_* signal generation
// instantiates an alt_mem_ddrx_addr_cmd for every phase
// maps bg_* signals to the correct instantiation
genvar afi_k;
generate
for (afi_k = 0; afi_k < CFG_AFI_INTF_PHASE_NUM; afi_k = afi_k + 1)
begin : gen_bg_afi_signal_decode
always @ (*)
begin
int_bg_do_write [afi_k] = bg_do_write [afi_k];
int_bg_do_read [afi_k] = bg_do_read [afi_k];
int_bg_do_burst_chop [afi_k] = bg_do_burst_chop [afi_k];
int_bg_do_burst_terminate [afi_k] = bg_do_burst_terminate [afi_k];
int_bg_do_auto_precharge [afi_k] = bg_do_auto_precharge [afi_k];
int_bg_do_rmw_correct [afi_k] = bg_do_rmw_correct [afi_k];
int_bg_do_rmw_partial [afi_k] = bg_do_rmw_partial [afi_k];
int_bg_do_activate [afi_k] = bg_do_activate [afi_k];
int_bg_do_precharge [afi_k] = bg_do_precharge [afi_k];
int_bg_to_chip [afi_k] = bg_to_chip [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_to_bank [afi_k] = bg_to_bank [(((afi_k+1)*CFG_MEM_IF_BA_WIDTH )-1):(afi_k*CFG_MEM_IF_BA_WIDTH )];
int_bg_to_row [afi_k] = bg_to_row [(((afi_k+1)*CFG_MEM_IF_ROW_WIDTH)-1):(afi_k*CFG_MEM_IF_ROW_WIDTH)];
int_bg_to_col [afi_k] = bg_to_col [(((afi_k+1)*CFG_MEM_IF_COL_WIDTH)-1):(afi_k*CFG_MEM_IF_COL_WIDTH)];
end
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
always @ (*)
begin
int_bg_do_precharge_all [afi_k] = bg_do_precharge_all [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_refresh [afi_k] = bg_do_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_self_refresh [afi_k] = bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_power_down [afi_k] = bg_do_power_down [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_deep_pdown [afi_k] = bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_zq_cal [afi_k] = bg_do_zq_cal [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_lmr [afi_k] = bg_do_lmr [afi_k];
end
always @ (*)
begin
cfg_enable_chipsel_for_sideband [afi_k] = one;
end
end
else // half and quarter rate
begin
always @ (*)
begin
int_bg_do_precharge_all [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_precharge_all [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : {CFG_MEM_IF_CHIP{1'b0}};
int_bg_do_refresh [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : {CFG_MEM_IF_CHIP{1'b0}};
int_bg_do_zq_cal [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_zq_cal [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : {CFG_MEM_IF_CHIP{1'b0}};
int_bg_do_lmr [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_lmr [afi_k ] : 1'b0;
// We need to assign these command to all phase
// because these command might take one or more controller clock cycles
// and we want to prevent CKE from toggling due to prolong commands
int_bg_do_power_down [afi_k] = bg_do_power_down [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
int_bg_do_self_refresh [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_self_refresh_r [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
int_bg_do_deep_pdown [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_deep_pdown_r [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
end
always @ (*)
begin
// We need to disable one phase of chipsel logic for sideband in half/quarter rate
// in order to prevent CS_N from going low for 2 clock cycles (deep power down and self refresh only)
cfg_enable_chipsel_for_sideband [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? one : zero;
end
end
// addresss command block instantiated based on number of phases
alt_mem_ddrx_addr_cmd # (
.CFG_PORT_WIDTH_TYPE ( CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_OUTPUT_REGD ( CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_MEM_IF_CHIP ( CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH ( CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH ( CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH ( CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH ( CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH ( CFG_MEM_IF_BA_WIDTH ),
.CFG_DWIDTH_RATIO ( CFG_FR_DWIDTH_RATIO )
) alt_mem_ddrx_addr_cmd_inst (
.ctl_clk ( ctl_clk ),
.ctl_reset_n ( ctl_reset_n ),
.ctl_cal_success ( ctl_cal_success ),
.cfg_type ( cfg_type ),
.cfg_output_regd ( cfg_output_regd_for_afi_output ),
.cfg_enable_chipsel_for_sideband ( cfg_enable_chipsel_for_sideband [afi_k] ),
.bg_do_write ( int_bg_do_write [afi_k] ),
.bg_do_read ( int_bg_do_read [afi_k] ),
.bg_do_auto_precharge ( int_bg_do_auto_precharge [afi_k] ),
.bg_do_burst_chop ( int_bg_do_burst_chop [afi_k] ),
.bg_do_activate ( int_bg_do_activate [afi_k] ),
.bg_do_precharge ( int_bg_do_precharge [afi_k] ),
.bg_do_refresh ( int_bg_do_refresh [afi_k] ),
.bg_do_power_down ( int_bg_do_power_down [afi_k] ),
.bg_do_self_refresh ( int_bg_do_self_refresh [afi_k] ),
.bg_do_lmr ( int_bg_do_lmr [afi_k] ),
.bg_do_precharge_all ( int_bg_do_precharge_all [afi_k] ),
.bg_do_zq_cal ( int_bg_do_zq_cal [afi_k] ),
.bg_do_deep_pdown ( int_bg_do_deep_pdown [afi_k] ),
.bg_do_burst_terminate ( int_bg_do_burst_terminate [afi_k] ),
.bg_to_chip ( int_bg_to_chip [afi_k] ),
.bg_to_bank ( int_bg_to_bank [afi_k] ),
.bg_to_row ( int_bg_to_row [afi_k] ),
.bg_to_col ( int_bg_to_col [afi_k] ),
.bg_to_lmr ( bg_to_lmr ),
.lmr_opcode ( lmr_opcode ),
.afi_cke ( int_ddrx_afi_cke [afi_k] ),
.afi_cs_n ( int_ddrx_afi_cs_n [afi_k] ),
.afi_ras_n ( int_ddrx_afi_ras_n [afi_k] ),
.afi_cas_n ( int_ddrx_afi_cas_n [afi_k] ),
.afi_we_n ( int_ddrx_afi_we_n [afi_k] ),
.afi_ba ( int_ddrx_afi_ba [afi_k] ),
.afi_addr ( int_ddrx_afi_addr [afi_k] ),
.afi_rst_n ( int_ddrx_afi_rst_n [afi_k] )
);
if (CFG_LPDDR2_ENABLED)
begin
alt_mem_ddrx_lpddr2_addr_cmd # (
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH (CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH (CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_FR_DWIDTH_RATIO )
) alt_mem_ddrx_lpddr2_addr_cmd_inst (
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.ctl_cal_success (ctl_cal_success ),
.cfg_output_regd (cfg_output_regd_for_afi_output ),
.cfg_enable_chipsel_for_sideband (cfg_enable_chipsel_for_sideband [afi_k]),
.do_write (int_bg_do_write [afi_k]),
.do_read (int_bg_do_read [afi_k]),
.do_auto_precharge (int_bg_do_auto_precharge [afi_k]),
.do_activate (int_bg_do_activate [afi_k]),
.do_precharge (int_bg_do_precharge [afi_k]),
.do_refresh (int_bg_do_refresh [afi_k]),
.do_power_down (int_bg_do_power_down [afi_k]),
.do_self_refresh (int_bg_do_self_refresh [afi_k]),
.do_lmr (int_bg_do_lmr [afi_k]),
.do_precharge_all (int_bg_do_precharge_all [afi_k]),
.do_deep_pwrdwn (int_bg_do_deep_pdown [afi_k]),
.do_burst_terminate (int_bg_do_burst_terminate [afi_k]),
.do_lmr_read (int_bg_do_lmr_read ),
.do_refresh_1bank (int_bg_do_refresh_1bank ),
.to_chip (int_bg_to_chip [afi_k]),
.to_bank (int_bg_to_bank [afi_k]),
.to_row (int_bg_to_row [afi_k]),
.to_col (int_bg_to_col [afi_k]),
.to_lmr (bg_to_lmr ),
.lmr_opcode (lmr_opcode[7:0] ),
.afi_cke (int_lpddr2_afi_cke [afi_k]),
.afi_cs_n (int_lpddr2_afi_cs_n [afi_k]),
.afi_addr (int_lpddr2_afi_addr [afi_k]),
.afi_rst_n (int_lpddr2_afi_rst_n [afi_k])
);
end
else
begin
assign int_lpddr2_afi_cke [afi_k] = {(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_cs_n [afi_k] = {(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_addr [afi_k] = {(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_rst_n [afi_k] = { (CFG_FR_DWIDTH_RATIO/2) {1'b0}};
end
always @ (*)
begin
// Mux to select ddrx or lpddr2 addrcmd decoder blocks
if (cfg_type == `MMR_TYPE_LPDDR2)
begin
phase_afi_cke [afi_k] = int_lpddr2_afi_cke [afi_k] ;
phase_afi_cs_n [afi_k] = int_lpddr2_afi_cs_n [afi_k] ;
phase_afi_ras_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_cas_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_we_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_ba [afi_k] = {(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
phase_afi_addr [afi_k] = int_lpddr2_afi_addr [afi_k] ;
phase_afi_rst_n [afi_k] = int_lpddr2_afi_rst_n[afi_k] ;
end
else
begin
phase_afi_cke [afi_k] = int_ddrx_afi_cke [afi_k] ;
phase_afi_cs_n [afi_k] = int_ddrx_afi_cs_n [afi_k] ;
phase_afi_ras_n [afi_k] = int_ddrx_afi_ras_n [afi_k] ;
phase_afi_cas_n [afi_k] = int_ddrx_afi_cas_n [afi_k] ;
phase_afi_we_n [afi_k] = int_ddrx_afi_we_n [afi_k] ;
phase_afi_ba [afi_k] = int_ddrx_afi_ba [afi_k] ;
phase_afi_addr [afi_k] = int_ddrx_afi_addr [afi_k] ;
phase_afi_rst_n [afi_k] = int_ddrx_afi_rst_n [afi_k] ;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_bg_do_rmw_correct_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
int_bg_do_rmw_partial_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
end
else
begin
int_bg_do_rmw_correct_r[afi_k] <= int_bg_do_rmw_correct [afi_k];
int_bg_do_rmw_partial_r[afi_k] <= int_bg_do_rmw_partial [afi_k];
end
end
always @ (*)
begin
if (cfg_output_regd_for_afi_output)
begin
phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct_r [afi_k];
phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial_r [afi_k];
end
else
begin
phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct [afi_k];
phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial [afi_k];
end
end
alt_mem_ddrx_odt_gen #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP (CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
odt_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_write_odt_chip (cfg_write_odt_chip ),
.cfg_read_odt_chip (cfg_read_odt_chip ),
.cfg_burst_length (cfg_burst_length ),
.cfg_output_regd (cfg_output_regd_for_afi_output ),
.bg_do_read (int_bg_do_read [afi_k]),
.bg_do_write (int_bg_do_write [afi_k]),
.bg_do_burst_chop (int_bg_do_burst_chop [afi_k]),
.bg_to_chip (int_bg_to_chip [afi_k]),
.afi_odt (afi_odt_h_l [afi_k])
);
end
always @ (*)
begin
int_bg_dataid = bg_dataid;
int_bg_localid = bg_localid;
int_bg_size = bg_size;
int_bg_do_lmr_read = bg_do_lmr_read;
int_bg_do_refresh_1bank = bg_do_refresh_1bank;
end
endgenerate
// ODT output generation
always @ (*)
begin
afi_odt = mux_afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1];
end
// generate ODT output signal from odt_gen
assign mux_afi_odt_h_l [0] = afi_odt_h_l [0];
genvar afi_m;
generate
for (afi_m = 1; afi_m < CFG_AFI_INTF_PHASE_NUM; afi_m = afi_m + 1)
begin : mux_for_odt
assign mux_afi_odt_h_l [afi_m] = mux_afi_odt_h_l [afi_m-1] | afi_odt_h_l [afi_m];
end
endgenerate
// generate fr_* signals from phase_* signals
assign mux_afi_cke [0] = phase_afi_cke [0];
assign mux_afi_cs_n [0] = phase_afi_cs_n [0];
assign mux_afi_ras_n [0] = phase_afi_ras_n [0];
assign mux_afi_cas_n [0] = phase_afi_cas_n [0];
assign mux_afi_we_n [0] = phase_afi_we_n [0];
assign mux_afi_ba [0] = phase_afi_ba [0];
assign mux_afi_addr [0] = phase_afi_addr [0];
assign mux_afi_rst_n [0] = phase_afi_rst_n [0];
assign mux_afi_rmw_correct [0] = phase_afi_rmw_correct [0];
assign mux_afi_rmw_partial [0] = phase_afi_rmw_partial [0];
genvar afi_l;
generate
for (afi_l = 1; afi_l < CFG_AFI_INTF_PHASE_NUM; afi_l = afi_l + 1)
begin : gen_resolve_phase_for_fullrate
assign mux_afi_cke [afi_l] = mux_afi_cke [(afi_l-1)] & phase_afi_cke [afi_l];
assign mux_afi_cs_n [afi_l] = mux_afi_cs_n [(afi_l-1)] & phase_afi_cs_n [afi_l];
assign mux_afi_ras_n [afi_l] = mux_afi_ras_n [(afi_l-1)] & phase_afi_ras_n [afi_l];
assign mux_afi_cas_n [afi_l] = mux_afi_cas_n [(afi_l-1)] & phase_afi_cas_n [afi_l];
assign mux_afi_we_n [afi_l] = mux_afi_we_n [(afi_l-1)] & phase_afi_we_n [afi_l];
assign mux_afi_ba [afi_l] = mux_afi_ba [(afi_l-1)] | phase_afi_ba [afi_l];
assign mux_afi_addr [afi_l] = mux_afi_addr [(afi_l-1)] | phase_afi_addr [afi_l];
assign mux_afi_rst_n [afi_l] = mux_afi_rst_n [(afi_l-1)] | phase_afi_rst_n [afi_l];
assign mux_afi_rmw_correct [afi_l] = mux_afi_rmw_correct [(afi_l-1)] | phase_afi_rmw_correct [afi_l];
assign mux_afi_rmw_partial [afi_l] = mux_afi_rmw_partial [(afi_l-1)] | phase_afi_rmw_partial [afi_l];
end
endgenerate
assign fr_afi_cke = mux_afi_cke [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_cs_n = mux_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_ras_n = mux_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_cas_n = mux_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_we_n = mux_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_ba = mux_afi_ba [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_addr = mux_afi_addr [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rst_n = mux_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rmw_correct = mux_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rmw_partial = mux_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1];
// Registered version of self refresh and power down
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
bg_do_self_refresh_r <= 0;
bg_do_deep_pdown_r <= 0;
end
else
begin
bg_do_self_refresh_r <= bg_do_self_refresh;
bg_do_deep_pdown_r <= bg_do_deep_pdown;
end
end
endmodule

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FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v
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FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v
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FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v
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@ -1,155 +0,0 @@
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* message_disable = "14320" *) module alt_mem_ddrx_buffer
# (
// module parameter port list
parameter
ADDR_WIDTH = 3,
DATA_WIDTH = 8,
REGISTER_OUTPUT = 0
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
write_valid,
write_address,
write_data,
// read interface
read_valid,
read_address,
read_data
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam BUFFER_DEPTH = two_pow_N(ADDR_WIDTH);
localparam BUFFER_REGISTER_OUTPUT = (REGISTER_OUTPUT) ? "CLOCK0" : "UNREGISTERED";
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
input write_valid;
input [ADDR_WIDTH-1:0] write_address;
input [DATA_WIDTH-1:0] write_data;
// read interface
input read_valid;
input [ADDR_WIDTH-1:0] read_address;
output [DATA_WIDTH-1:0] read_data;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
wire write_valid;
wire [ADDR_WIDTH-1:0] write_address;
wire [DATA_WIDTH-1:0] write_data;
// read interface
wire read_valid;
wire [ADDR_WIDTH-1:0] read_address;
wire [DATA_WIDTH-1:0] read_data;
// -----------------------------
// module definition
// -----------------------------
altsyncram altsyncram_component
(
.wren_a (write_valid),
.clock0 (ctl_clk),
.address_a (write_address),
.address_b (read_address),
.data_a (write_data),
.q_b (read_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.intended_device_family = "Stratix",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = BUFFER_DEPTH,
altsyncram_component.numwords_b = BUFFER_DEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = BUFFER_REGISTER_OUTPUT,
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
// alt_ddrx_ram_2port
// ram_inst
// (
// .clock (ctl_clk),
// .wren (write_valid),
// .wraddress (write_address),
// .data (write_data),
// .rdaddress (read_address),
// .q (read_data)
// );
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule

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FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v
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// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module alt_mem_ddrx_buffer_manager
# (
parameter
CFG_BUFFER_ADDR_WIDTH = 6
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
writeif_ready,
writeif_valid,
writeif_address,
writeif_address_blocked,
// buffer write interface
buffwrite_valid,
buffwrite_address,
// read interface
readif_valid,
readif_address,
// buffer read interface
buffread_valid,
buffread_datavalid,
buffread_address
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_BUFFER_DEPTH = two_pow_N(CFG_BUFFER_ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
output writeif_ready;
input writeif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
input writeif_address_blocked;
// buffer write interface
output buffwrite_valid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
input readif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
output buffread_valid;
output buffread_datavalid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
reg writeif_ready;
wire writeif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
wire writeif_address_blocked;
// buffer write interface
wire buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
wire readif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
wire buffread_valid;
reg buffread_datavalid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// signal declaration
// -----------------------------
wire writeif_accepted;
reg [CTL_BUFFER_DEPTH-1:0] mux_writeif_ready;
reg [CTL_BUFFER_DEPTH-1:0] buffer_valid_array;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter;
reg err_buffer_valid_counter_overflow;
// -----------------------------
// module definition
// -----------------------------
assign writeif_accepted = writeif_ready & writeif_valid;
assign buffwrite_address = writeif_address;
assign buffwrite_valid = writeif_accepted;
assign buffread_address = readif_address;
assign buffread_valid = readif_valid;
always @ (*)
begin
if (writeif_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
writeif_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
writeif_ready = ~&buffer_valid_counter;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffread_datavalid <= 0;
end
else
begin
buffread_datavalid <= buffread_valid;
end
end
// genvar i;
// generate
// for (i = 0; i < CTL_BUFFER_DEPTH; i = i + 1)
// begin : gen_mux_buffer_valid_array_signals
// wire [CFG_BUFFER_ADDR_WIDTH-1:0] gen_buffer_address = i;
// always @ (posedge ctl_clk or negedge ctl_reset_n)
// begin
// if (~ctl_reset_n)
// begin
// //reset state ...
// buffer_valid_array [i] <= 0;
// end
// else
// begin
// //active state ...
// // write & read to same location won't happen on same time
// // write
// if ( (writeif_address == gen_buffer_address) & writeif_accepted)
// begin
// buffer_valid_array[i] <= 1;
// end
// // read
// if ( (readif_address== gen_buffer_address) & readif_valid)
// begin
// buffer_valid_array[i] <= 0;
// end
// end
// end
// always @ (*)
// begin
// // mano - fmax !
// if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
// begin
// mux_writeif_ready[i] = 0;
// end
// else
// begin
// mux_writeif_ready[i] = 1;
// end
// end
// end
// endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (writeif_accepted & readif_valid)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
end
else if (writeif_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
end
else if (readif_valid)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
//
// assert
//
// - write & read to same location happen on same time

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FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v
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FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v
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// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`timescale 1 ps / 1 ps
module alt_mem_ddrx_burst_tracking
# (
// module parameter port list
parameter
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 4
)
(
// port list
ctl_clk,
ctl_reset_n,
// data burst interface
burst_ready,
burst_valid,
// burstcount counter sent to data_id_manager
burst_pending_burstcount,
burst_next_pending_burstcount,
// burstcount consumed by data_id_manager
burst_consumed_valid,
burst_counsumed_burstcount
);
// -----------------------------
// local parameter declarations
// -----------------------------
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// data burst interface
input burst_ready;
input burst_valid;
// burstcount counter sent to data_id_manager
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
// burstcount consumed by data_id_manager
input burst_consumed_valid;
input [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// data burst interface
wire burst_ready;
wire burst_valid;
// burstcount counter sent to data_id_manager
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
//wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_count_accepted;
// burstcount consumed by data_id_manager
wire burst_consumed_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// signal declaration
// -----------------------------
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter_next;
wire burst_accepted;
// -----------------------------
// module definition
// -----------------------------
assign burst_pending_burstcount = burst_counter;
assign burst_next_pending_burstcount = burst_counter_next;
assign burst_accepted = burst_ready & burst_valid;
always @ (*)
begin
if (burst_accepted & burst_consumed_valid)
begin
burst_counter_next = burst_counter + 1 - burst_counsumed_burstcount;
end
else if (burst_accepted)
begin
burst_counter_next = burst_counter + 1;
end
else if (burst_consumed_valid)
begin
burst_counter_next = burst_counter - burst_counsumed_burstcount;
end
else
begin
burst_counter_next = burst_counter;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
burst_counter <= 0;
end
else
begin
burst_counter <= burst_counter_next;
end
end
endmodule

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FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v
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FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v
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FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v
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// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
//For tCL = 3 and tCWL = 2 rdwr_data_tmg block output must be registered in order to support ODT
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ddr2_odt_gen
# ( parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_ADD_LAT = 3,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_add_lat,
cfg_burst_length,
cfg_output_regd,
bg_do_write,
bg_do_read,
int_odt_l,
int_odt_h
);
//=================================================================================================//
// Local parameter definition //
//=================================================================================================//
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL; // okay to size this to 4 since max latency in DDR2 is 7+6=13
localparam CFG_TAOND = 2;
localparam CFG_TAOFD = 2.5;
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_ADD_LAT-1:0] cfg_add_lat;
input [4:0] cfg_burst_length;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
output int_odt_l;
output int_odt_h;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
wire bg_do_read;
reg [1:0] regd_output;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl_unreg;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl;
reg int_tcwl_even;
reg int_tcwl_odd;
reg [CFG_PORT_WIDTH_TCL-1:0] write_latency;
reg [CFG_PORT_WIDTH_TCL-1:0] read_latency;
wire int_odt_l;
wire int_odt_h;
reg reg_odt_l;
reg reg_odt_h;
reg combi_odt_l;
reg combi_odt_h;
reg [1:0] offset_code;
reg start_odt_write;
reg start_odt_read;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_write_pipe;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_read_pipe;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
regd_output <= 0;
end
else
begin
if (cfg_output_regd)
regd_output <= (CFG_DWIDTH_RATIO / 2) * cfg_output_regd;
else
regd_output <= 2'd0;
end
end
always @ (*)
begin
int_tcwl_unreg = cfg_tcl + cfg_add_lat + regd_output - 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_tcwl <= 0;
else
int_tcwl <= int_tcwl_unreg;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b0;
end
else
begin
if (int_tcwl % 2 == 0)
begin
int_tcwl_even <= 1'b1;
int_tcwl_odd <= 1'b0;
end
else
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
write_latency <= 0;
read_latency <= 0;
end
else
begin
write_latency <= (int_tcwl - 4) / (CFG_DWIDTH_RATIO / 2);
read_latency <= (int_tcwl - 3) / (CFG_DWIDTH_RATIO / 2);
end
end
//=================================================================================================//
// Delay ODT signal to match READ DQ/DQS //
//=================================================================================================//
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_read_pipe <= 0;
else
if (bg_do_read)
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_read};
else
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 3)
start_odt_read = bg_do_read;
else
start_odt_read = do_read_pipe[read_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_read_count <= 0; end
else
begin
if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_read_count <= 1;
else
doing_read_count <= 0;
end
else if (doing_read_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_read_count <= 0;
end
else if (doing_read_count > 0)
begin
doing_read_count <= doing_read_count + 1'b1;
end
end
end
//=================================================================================================//
// Delay ODT signal to match WRITE DQ/DQS //
//=================================================================================================//
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_write_pipe <= 0;
else
if (bg_do_write)
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_write};
else
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 4)
start_odt_write = bg_do_write;
else
start_odt_write = do_write_pipe[write_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write_count <= 0;
else
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_write_count <= 1;
else
doing_write_count <= 0;
end
else if (doing_write_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_write_count <= 0;
end
else if (doing_write_count > 0)
begin
doing_write_count <= doing_write_count + 1'b1;
end
end
//=================================================================================================//
// ODT signal generation block //
//=================================================================================================//
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
if (start_odt_write || start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else // half and quarter rate
begin
if (int_tcwl_even)
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
else
begin
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
if (start_odt_write || start_odt_read)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
else // half and quarter rate
begin
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_write_count > 0)
begin
if (doing_write_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_read_count > 0)
begin
if (doing_read_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
end
end
generate
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_h | reg_odt_h;
end
else if (CFG_DWIDTH_RATIO == 4) // half rate
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_l | reg_odt_l;
end
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
begin
end
endgenerate
endmodule

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FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v
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// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036 10230
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ddr3_odt_gen
# (parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4,
CFG_PORT_WIDTH_CAS_WR_LAT = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_cas_wr_lat,
cfg_output_regd,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
int_odt_l,
int_odt_h,
int_odt_i_1,
int_odt_i_2
);
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL;
//=================================================================================================//
// DDR3 ODT timing parameters //
//=================================================================================================//
localparam integer CFG_ODTH8 = 6; //Indicates No. of cycles ODT signal should stay high
localparam integer CFG_ODTH4 = 4; //Indicates No. of cycles ODT signal should stay high
localparam integer CFG_ODTPIPE_THRESHOLD = CFG_DWIDTH_RATIO / 2;
// AL also applies to ODT signal so ODT logic is AL agnostic
// also regdimm because ODT is registered too
// ODTLon = CWL + AL - 2
// ODTLoff = CWL + AL - 2
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_CAS_WR_LAT-1:0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
input bg_do_burst_chop;
output int_odt_l;
output int_odt_h;
output int_odt_i_1;
output int_odt_i_2;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
reg int_do_read;
reg int_do_write_burst_chop;
reg int_do_read_burst_chop;
reg int_do_read_burst_chop_c;
reg do_read_r;
wire [3:0] diff_unreg; // difference between CL and CWL
reg [3:0] diff;
wire [3:0] diff_modulo_unreg;
reg [3:0] diff_modulo;
wire [3:0] sel_do_read_pipe_unreg;
reg [3:0] sel_do_read_pipe;
reg diff_modulo_not_zero;
reg diff_modulo_one;
reg diff_modulo_two;
reg diff_modulo_three;
reg int_odt_l_int;
reg int_odt_l_int_r1;
reg int_odt_l_int_r2;
reg premux_odt_h;
reg premux_odt_h_r;
reg int_odt_h_int;
reg int_odt_h_int_r1;
reg int_odt_h_int_r2;
reg int_odt_i_1_int;
reg int_odt_i_2_int;
reg int_odt_i_1_int_r1;
reg int_odt_i_2_int_r1;
reg int_odt_i_1_int_r2;
reg int_odt_i_2_int_r2;
wire int_odt_l;
wire int_odt_h;
wire int_odt_i_1;
wire int_odt_i_2;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
wire doing_read_count_not_zero;
reg doing_read_count_not_zero_r;
wire [3:0] doing_write_count_limit;
wire [3:0] doing_read_count_limit;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_read_pipe;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_burst_chop_pipe;
//=================================================================================================//
// Define ODT pulse width during READ operation //
//=================================================================================================//
//ODTLon/ODTLoff are calculated based on CWL, Below logic is to compensate for that timing during read, Needs to delay ODT signal by cfg_tcl - cfg_cas_wr_lat
assign diff_unreg = cfg_tcl - cfg_cas_wr_lat;
assign diff_modulo_unreg = (diff % CFG_ODTPIPE_THRESHOLD);
assign sel_do_read_pipe_unreg = (diff / CFG_ODTPIPE_THRESHOLD) + diff_modulo_not_zero;
//assign diff_modulo_not_zero = (|diff_modulo);
//assign sel_do_read_pipe = diff - CFG_ODTPIPE_THRESHOLD;
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff <= 0;
diff_modulo <= 0;
sel_do_read_pipe <= 0;
end
else
begin
diff <= diff_unreg;
diff_modulo <= diff_modulo_unreg;
sel_do_read_pipe <= (sel_do_read_pipe_unreg > 0) ? (sel_do_read_pipe_unreg - 1'b1) : 0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff_modulo_not_zero <= 1'b0;
diff_modulo_one <= 1'b0;
diff_modulo_two <= 1'b0;
diff_modulo_three <= 1'b0;
end
else
begin
diff_modulo_not_zero <= |diff_modulo;
diff_modulo_one <= (diff_modulo == 1) ? 1'b1 : 1'b0;
diff_modulo_two <= (diff_modulo == 2) ? 1'b1 : 1'b0;
diff_modulo_three <= (diff_modulo == 3) ? 1'b1 : 1'b0;
end
end
always @ (*)
begin
int_do_read = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_read : do_read_pipe [sel_do_read_pipe] ;
int_do_read_burst_chop_c = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_burst_chop : do_burst_chop_pipe [sel_do_read_pipe] ;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_read_burst_chop <= 1'b0;
end
else
begin
if (int_do_read)
begin
int_do_read_burst_chop <= int_do_read_burst_chop_c;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_read_pipe <= 0;
end
else
begin
do_read_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0], bg_do_read};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_burst_chop_pipe <= 0;
end
else
begin
do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-2:0], bg_do_burst_chop};
end
end
assign doing_read_count_limit = int_do_read_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
assign doing_read_count_not_zero = (|doing_read_count);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_read_count <= 0;
end
else
begin
if (int_do_read)
begin
doing_read_count <= 1;
end
else if (doing_read_count >= doing_read_count_limit)
begin
doing_read_count <= 0;
end
else if (doing_read_count > 0)
begin
doing_read_count <= doing_read_count + 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
doing_read_count_not_zero_r <= 1'b0;
end
else
begin
doing_read_count_not_zero_r <= doing_read_count_not_zero;
end
end
//=================================================================================================//
// Define ODT pulse width during WRITE operation //
//=================================================================================================//
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_write_burst_chop <= 1'b0;
end
else
begin
if (bg_do_write)
begin
int_do_write_burst_chop <= bg_do_burst_chop;
end
end
end
assign doing_write_count_limit = int_do_write_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_count <= 0;
end
else
begin
if (bg_do_write)
begin
doing_write_count <= 1;
end
else if (doing_write_count >= doing_write_count_limit)
begin
doing_write_count <= 0;
end
else if (doing_write_count > 0)
begin
doing_write_count <= doing_write_count + 1'b1;
end
end
end
//=================================================================================================//
// ODT signal generation block //
//=================================================================================================//
always @ (*)
begin
if (bg_do_write || int_do_read)
begin
premux_odt_h = 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
premux_odt_h = 1'b1;
end
else
begin
premux_odt_h = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
premux_odt_h_r <= 1'b0;
end
else
begin
if (int_do_read)
begin
premux_odt_h_r <= 1'b1;
end
else if ((doing_read_count > 1 && ((diff_modulo_one && CFG_ODTPIPE_THRESHOLD == 4) || diff_modulo_two)) || (doing_read_count > 0 && ((diff_modulo_one && CFG_ODTPIPE_THRESHOLD == 2) || diff_modulo_three)))
begin
premux_odt_h_r <= 1'b1;
end
else
begin
premux_odt_h_r <= 1'b0;
end
end
end
always @ (*)
begin
if (diff_modulo_not_zero & (int_do_read|doing_read_count_not_zero_r))
begin
int_odt_h_int = premux_odt_h_r;
end
else // write, read with normal odt
begin
int_odt_h_int = premux_odt_h;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_l_int <= 1'b0;
end
else
begin
if (bg_do_write || (int_do_read && !diff_modulo_two && !diff_modulo_three))
begin
int_odt_l_int <= 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
int_odt_l_int <= 1'b1;
end
else
begin
int_odt_l_int <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_i_1_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin
int_odt_i_1_int <= 1'b1;
end
else if (doing_write_count > 1 || (doing_read_count > 1 && !diff_modulo_not_zero) || (doing_read_count > 0 && diff_modulo_not_zero))
begin
int_odt_i_1_int <= 1'b1;
end
else
begin
int_odt_i_1_int <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_i_2_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin
int_odt_i_2_int <= 1'b1;
end
else if (doing_write_count > 1 || (doing_read_count > 1 && (!diff_modulo_not_zero || diff_modulo_one)) || (doing_read_count > 0 && (diff_modulo_two || diff_modulo_three)))
begin
int_odt_i_2_int <= 1'b1;
end
else
begin
int_odt_i_2_int <= 1'b0;
end
end
end
//Generate registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_h_int_r1 <= 1'b0;
int_odt_l_int_r1 <= 1'b0;
int_odt_i_1_int_r1 <= 1'b0;
int_odt_i_2_int_r1 <= 1'b0;
int_odt_h_int_r2 <= 1'b0;
int_odt_l_int_r2 <= 1'b0;
int_odt_i_1_int_r2 <= 1'b0;
int_odt_i_2_int_r2 <= 1'b0;
end
else
begin
int_odt_h_int_r1 <= int_odt_h_int;
int_odt_l_int_r1 <= int_odt_l_int;
int_odt_i_1_int_r1 <= int_odt_i_1_int;
int_odt_i_2_int_r1 <= int_odt_i_2_int;
int_odt_h_int_r2 <= int_odt_h_int_r1;
int_odt_l_int_r2 <= int_odt_l_int_r1;
int_odt_i_1_int_r2 <= int_odt_i_1_int_r1;
int_odt_i_2_int_r2 <= int_odt_i_2_int_r1;
end
end
generate
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = (cfg_output_regd == 2) ? int_odt_h_int_r2 : ((cfg_output_regd == 1) ? int_odt_h_int_r1 : int_odt_h_int);
assign int_odt_l = (cfg_output_regd == 2) ? int_odt_h_int_r2 : ((cfg_output_regd == 1) ? int_odt_h_int_r1 : int_odt_h_int);
assign int_odt_i_1 = 1'b0;
assign int_odt_i_2 = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 4) // half rate
begin
assign int_odt_h = (cfg_output_regd == 2) ? int_odt_h_int_r2 : ((cfg_output_regd == 1) ? int_odt_h_int_r1 : int_odt_h_int);
assign int_odt_l = (cfg_output_regd == 2) ? int_odt_l_int_r2 : ((cfg_output_regd == 1) ? int_odt_l_int_r1 : int_odt_l_int);
assign int_odt_i_1 = 1'b0;
assign int_odt_i_2 = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
begin
assign int_odt_h = (cfg_output_regd == 2) ? int_odt_h_int_r2 : ((cfg_output_regd == 1) ? int_odt_h_int_r1 : int_odt_h_int );
assign int_odt_l = (cfg_output_regd == 2) ? int_odt_l_int_r2 : ((cfg_output_regd == 1) ? int_odt_l_int_r1 : int_odt_l_int );
assign int_odt_i_1 = (cfg_output_regd == 2) ? int_odt_i_1_int_r2 : ((cfg_output_regd == 1) ? int_odt_i_1_int_r1 : int_odt_i_1_int);
assign int_odt_i_2 = (cfg_output_regd == 2) ? int_odt_i_2_int_r2 : ((cfg_output_regd == 1) ? int_odt_i_2_int_r1 : int_odt_i_2_int);
end
endgenerate
endmodule

41
FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv
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@ -1,41 +0,0 @@
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//--------------------------------------------------------------------------------------------------------
//
// [START] MMR - Memory Mapped Register Definition
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Generic Signals
//----------------------------------------------------------------------------------------------------
// cfg_type
`define MMR_TYPE_DDR1 3'b000
`define MMR_TYPE_DDR2 3'b001
`define MMR_TYPE_DDR3 3'b010
`define MMR_TYPE_LPDDR1 3'b011
`define MMR_TYPE_LPDDR2 3'b100
//----------------------------------------------------------------------------------------------------
// Address Mapping Signals
//----------------------------------------------------------------------------------------------------
// cfg_addr_order
`define MMR_ADDR_ORDER_CS_ROW_BA_COL 2'b00
`define MMR_ADDR_ORDER_CS_BA_ROW_COL 2'b01
`define MMR_ADDR_ORDER_ROW_CS_BA_COL 2'b10
//--------------------------------------------------------------------------------------------------------
//
// [END] MMR - Memory Mapped Register Definition
//
//--------------------------------------------------------------------------------------------------------

427
FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v
View File

@ -1,427 +0,0 @@
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ecc_decoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_DEC_REG = 1,
CFG_ECC_DECODER_REG = 0,
CFG_ECC_RDATA_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_data_valid,
output_data,
output_data_valid,
output_ecc_code,
err_corrected,
err_detected,
err_fatal,
err_sbe
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input input_data_valid;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
output output_data_valid;
output [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] or_int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg output_data_valid;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
reg err_corrected;
reg err_detected;
reg err_fatal;
reg err_sbe;
wire int_err_corrected;
wire int_err_detected;
wire int_err_fatal;
wire int_err_sbe;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] decoder_output_ecc_code;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] decoder_output_ecc_code_r;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] decoder_output_ecc_code_r_r;
wire [CFG_DATA_WIDTH - 1 : 0] decoder_input;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output;
reg decoder_output_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output_r;
reg decoder_output_valid_r;
reg decoder_output_valid_r_r;
reg int_err_corrected_r;
reg int_err_detected_r;
reg int_err_fatal_r;
reg int_err_sbe_r;
wire zero = 1'b0;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data splitting/masking logic:
// change
// <Empty data> - <ECC code> - <Data>
// into
// <ECC code> - <Empty data> - <Data>
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : decoder_input_per_data_width
always @ (*)
begin
int_decoder_input_data [i_data] = input_data [i_data];
end
end
endgenerate
generate
if (CFG_ECC_RDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_decoder_input <= 0;
end
else
begin
int_decoder_input <= int_decoder_input_data;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
decoder_output_valid <= 0;
decoder_output_ecc_code <= 0;
end
else
begin
decoder_output_valid <= input_data_valid;
decoder_output_ecc_code <= int_output_ecc_code;
end
end
end
else
begin
always @ (*)
begin
int_decoder_input = int_decoder_input_data;
end
always @ (*)
begin
decoder_output_valid = input_data_valid;
decoder_output_ecc_code = int_output_ecc_code;
end
end
endgenerate
// Decoder input assignment
assign decoder_input = int_decoder_input;
// Decoder output, registered
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
decoder_output_r <= {CFG_ECC_DATA_WIDTH{1'b0}};
decoder_output_valid_r <= 1'b0;
decoder_output_valid_r_r <= 1'b0;
int_err_corrected_r <= 1'b0;
int_err_detected_r <= 1'b0;
int_err_fatal_r <= 1'b0;
int_err_sbe_r <= 1'b0;
decoder_output_ecc_code_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
decoder_output_ecc_code_r_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
end
else
begin
decoder_output_r <= decoder_output;
decoder_output_valid_r <= decoder_output_valid;
decoder_output_valid_r_r <= decoder_output_valid_r;
int_err_corrected_r <= int_err_corrected;
int_err_detected_r <= int_err_detected;
int_err_fatal_r <= int_err_fatal;
int_err_sbe_r <= int_err_sbe;
decoder_output_ecc_code_r <= decoder_output_ecc_code;
decoder_output_ecc_code_r_r <= decoder_output_ecc_code_r;
end
end
// Decoder output ecc code
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
int_output_ecc_code = {CFG_ECC_CODE_WIDTH{zero}};
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
int_output_ecc_code = int_decoder_input_data [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
else
int_output_ecc_code = 0;
end
end
endgenerate
// Decoder wrapper output assignment
generate
begin : gen_decoder_output_reg_select
if (CFG_ECC_DEC_REG)
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output_r}; // Assign '0' to ECC code portions
output_data_valid = (CFG_ECC_DECODER_REG == 1) ? decoder_output_valid_r_r : decoder_output_valid_r;
err_corrected = int_err_corrected_r;
err_detected = int_err_detected_r;
err_fatal = int_err_fatal_r;
err_sbe = int_err_sbe_r;
output_ecc_code = (CFG_ECC_DECODER_REG == 1) ? decoder_output_ecc_code_r_r : decoder_output_ecc_code_r;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = decoder_output_ecc_code;
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output}; // Assign '0' to ECC code portions
output_data_valid = (CFG_ECC_DECODER_REG == 1) ? decoder_output_valid_r : decoder_output_valid;
err_corrected = int_err_corrected;
err_detected = int_err_detected;
err_fatal = int_err_fatal;
err_sbe = int_err_sbe;
output_ecc_code = decoder_output_ecc_code;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = decoder_output_ecc_code;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] internal_decoder_input;
wire [31 : 0] internal_decoder_output;
// Assign decoder output
assign internal_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 24'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = internal_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
decoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (internal_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (internal_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] internal_decoder_input;
wire [31 : 0] internal_decoder_output;
// Assign decoder output
assign internal_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 16'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = internal_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
decoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (internal_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (internal_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
decoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_64
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
decoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (decoder_input ),
.err_corrected (int_err_corrected),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
else
begin
assign int_err_corrected = 1'b0;
assign int_err_detected = 1'b0;
assign int_err_fatal = 1'b0;
assign int_err_sbe = 1'b0;
assign decoder_output = {CFG_ECC_DATA_WIDTH{1'b0}};
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule

496
FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v
View File

@ -1,496 +0,0 @@
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_decoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_decoder_32.v
// Megafunction Name(s):
// altecc_decoder
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Internal Build 257 07/26/2010 SP 1 PN Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_decoder device_family="Stratix III" lpm_pipeline=0 width_codeword=39 width_dataword=32 data err_corrected err_detected err_fatal q
//VERSION_BEGIN 10.0SP1 cbx_altecc_decoder 2010:07:26:21:21:15:PN cbx_cycloneii 2010:07:26:21:21:15:PN cbx_lpm_add_sub 2010:07:26:21:21:15:PN cbx_lpm_compare 2010:07:26:21:21:15:PN cbx_lpm_decode 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN cbx_stratix 2010:07:26:21:21:16:PN cbx_stratixii 2010:07:26:21:21:16:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//lpm_decode DEVICE_FAMILY="Stratix III" LPM_DECODES=64 LPM_WIDTH=6 data eq
//VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:07:26:21:21:15:PN cbx_lpm_add_sub 2010:07:26:21:21:15:PN cbx_lpm_compare 2010:07:26:21:21:15:PN cbx_lpm_decode 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN cbx_stratix 2010:07:26:21:21:16:PN cbx_stratixii 2010:07:26:21:21:16:PN VERSION_END
//synthesis_resources = lut 72
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_32_decode
(
data,
eq) /* synthesis synthesis_clearbox=1 */;
input [5:0] data;
output [63:0] eq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [5:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] data_wire;
wire [63:0] eq_node;
wire [63:0] eq_wire;
wire [3:0] w_anode1000w;
wire [3:0] w_anode1010w;
wire [3:0] w_anode1020w;
wire [3:0] w_anode1030w;
wire [3:0] w_anode1041w;
wire [3:0] w_anode1053w;
wire [3:0] w_anode1064w;
wire [3:0] w_anode1074w;
wire [3:0] w_anode1084w;
wire [3:0] w_anode1094w;
wire [3:0] w_anode1104w;
wire [3:0] w_anode1114w;
wire [3:0] w_anode1124w;
wire [3:0] w_anode1135w;
wire [3:0] w_anode1147w;
wire [3:0] w_anode1158w;
wire [3:0] w_anode1168w;
wire [3:0] w_anode1178w;
wire [3:0] w_anode1188w;
wire [3:0] w_anode1198w;
wire [3:0] w_anode1208w;
wire [3:0] w_anode1218w;
wire [3:0] w_anode464w;
wire [3:0] w_anode482w;
wire [3:0] w_anode499w;
wire [3:0] w_anode509w;
wire [3:0] w_anode519w;
wire [3:0] w_anode529w;
wire [3:0] w_anode539w;
wire [3:0] w_anode549w;
wire [3:0] w_anode559w;
wire [3:0] w_anode571w;
wire [3:0] w_anode583w;
wire [3:0] w_anode594w;
wire [3:0] w_anode604w;
wire [3:0] w_anode614w;
wire [3:0] w_anode624w;
wire [3:0] w_anode634w;
wire [3:0] w_anode644w;
wire [3:0] w_anode654w;
wire [3:0] w_anode665w;
wire [3:0] w_anode677w;
wire [3:0] w_anode688w;
wire [3:0] w_anode698w;
wire [3:0] w_anode708w;
wire [3:0] w_anode718w;
wire [3:0] w_anode728w;
wire [3:0] w_anode738w;
wire [3:0] w_anode748w;
wire [3:0] w_anode759w;
wire [3:0] w_anode771w;
wire [3:0] w_anode782w;
wire [3:0] w_anode792w;
wire [3:0] w_anode802w;
wire [3:0] w_anode812w;
wire [3:0] w_anode822w;
wire [3:0] w_anode832w;
wire [3:0] w_anode842w;
wire [3:0] w_anode853w;
wire [3:0] w_anode865w;
wire [3:0] w_anode876w;
wire [3:0] w_anode886w;
wire [3:0] w_anode896w;
wire [3:0] w_anode906w;
wire [3:0] w_anode916w;
wire [3:0] w_anode926w;
wire [3:0] w_anode936w;
wire [3:0] w_anode947w;
wire [3:0] w_anode959w;
wire [3:0] w_anode970w;
wire [3:0] w_anode980w;
wire [3:0] w_anode990w;
wire [2:0] w_data462w;
assign
data_wire = data,
eq = eq_node,
eq_node = eq_wire[63:0],
eq_wire = {{w_anode1218w[3], w_anode1208w[3], w_anode1198w[3], w_anode1188w[3], w_anode1178w[3], w_anode1168w[3], w_anode1158w[3], w_anode1147w[3]}, {w_anode1124w[3], w_anode1114w[3], w_anode1104w[3], w_anode1094w[3], w_anode1084w[3], w_anode1074w[3], w_anode1064w[3], w_anode1053w[3]}, {w_anode1030w[3], w_anode1020w[3], w_anode1010w[3], w_anode1000w[3], w_anode990w[3], w_anode980w[3], w_anode970w[3], w_anode959w[3]}, {w_anode936w[3], w_anode926w[3], w_anode916w[3], w_anode906w[3], w_anode896w[3], w_anode886w[3], w_anode876w[3], w_anode865w[3]}, {w_anode842w[3], w_anode832w[3], w_anode822w[3], w_anode812w[3], w_anode802w[3], w_anode792w[3], w_anode782w[3], w_anode771w[3]}, {w_anode748w[3], w_anode738w[3], w_anode728w[3], w_anode718w[3], w_anode708w[3], w_anode698w[3], w_anode688w[3], w_anode677w[3]}, {w_anode654w[3], w_anode644w[3], w_anode634w[3], w_anode624w[3], w_anode614w[3], w_anode604w[3], w_anode594w[3], w_anode583w[3]}, {w_anode559w[3], w_anode549w[3], w_anode539w[3], w_anode529w[3], w_anode519w[3], w_anode509w[3], w_anode499w[3], w_anode482w[3]}},
w_anode1000w = {(w_anode1000w[2] & w_data462w[2]), (w_anode1000w[1] & (~ w_data462w[1])), (w_anode1000w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode1010w = {(w_anode1010w[2] & w_data462w[2]), (w_anode1010w[1] & (~ w_data462w[1])), (w_anode1010w[0] & w_data462w[0]), w_anode947w[3]},
w_anode1020w = {(w_anode1020w[2] & w_data462w[2]), (w_anode1020w[1] & w_data462w[1]), (w_anode1020w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode1030w = {(w_anode1030w[2] & w_data462w[2]), (w_anode1030w[1] & w_data462w[1]), (w_anode1030w[0] & w_data462w[0]), w_anode947w[3]},
w_anode1041w = {(w_anode1041w[2] & data_wire[5]), (w_anode1041w[1] & data_wire[4]), (w_anode1041w[0] & (~ data_wire[3])), 1'b1},
w_anode1053w = {(w_anode1053w[2] & (~ w_data462w[2])), (w_anode1053w[1] & (~ w_data462w[1])), (w_anode1053w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1064w = {(w_anode1064w[2] & (~ w_data462w[2])), (w_anode1064w[1] & (~ w_data462w[1])), (w_anode1064w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1074w = {(w_anode1074w[2] & (~ w_data462w[2])), (w_anode1074w[1] & w_data462w[1]), (w_anode1074w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1084w = {(w_anode1084w[2] & (~ w_data462w[2])), (w_anode1084w[1] & w_data462w[1]), (w_anode1084w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1094w = {(w_anode1094w[2] & w_data462w[2]), (w_anode1094w[1] & (~ w_data462w[1])), (w_anode1094w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1104w = {(w_anode1104w[2] & w_data462w[2]), (w_anode1104w[1] & (~ w_data462w[1])), (w_anode1104w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1114w = {(w_anode1114w[2] & w_data462w[2]), (w_anode1114w[1] & w_data462w[1]), (w_anode1114w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1124w = {(w_anode1124w[2] & w_data462w[2]), (w_anode1124w[1] & w_data462w[1]), (w_anode1124w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1135w = {(w_anode1135w[2] & data_wire[5]), (w_anode1135w[1] & data_wire[4]), (w_anode1135w[0] & data_wire[3]), 1'b1},
w_anode1147w = {(w_anode1147w[2] & (~ w_data462w[2])), (w_anode1147w[1] & (~ w_data462w[1])), (w_anode1147w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1158w = {(w_anode1158w[2] & (~ w_data462w[2])), (w_anode1158w[1] & (~ w_data462w[1])), (w_anode1158w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode1168w = {(w_anode1168w[2] & (~ w_data462w[2])), (w_anode1168w[1] & w_data462w[1]), (w_anode1168w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1178w = {(w_anode1178w[2] & (~ w_data462w[2])), (w_anode1178w[1] & w_data462w[1]), (w_anode1178w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode1188w = {(w_anode1188w[2] & w_data462w[2]), (w_anode1188w[1] & (~ w_data462w[1])), (w_anode1188w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1198w = {(w_anode1198w[2] & w_data462w[2]), (w_anode1198w[1] & (~ w_data462w[1])), (w_anode1198w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode1208w = {(w_anode1208w[2] & w_data462w[2]), (w_anode1208w[1] & w_data462w[1]), (w_anode1208w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1218w = {(w_anode1218w[2] & w_data462w[2]), (w_anode1218w[1] & w_data462w[1]), (w_anode1218w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode464w = {(w_anode464w[2] & (~ data_wire[5])), (w_anode464w[1] & (~ data_wire[4])), (w_anode464w[0] & (~ data_wire[3])), 1'b1},
w_anode482w = {(w_anode482w[2] & (~ w_data462w[2])), (w_anode482w[1] & (~ w_data462w[1])), (w_anode482w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode499w = {(w_anode499w[2] & (~ w_data462w[2])), (w_anode499w[1] & (~ w_data462w[1])), (w_anode499w[0] & w_data462w[0]), w_anode464w[3]},
w_anode509w = {(w_anode509w[2] & (~ w_data462w[2])), (w_anode509w[1] & w_data462w[1]), (w_anode509w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode519w = {(w_anode519w[2] & (~ w_data462w[2])), (w_anode519w[1] & w_data462w[1]), (w_anode519w[0] & w_data462w[0]), w_anode464w[3]},
w_anode529w = {(w_anode529w[2] & w_data462w[2]), (w_anode529w[1] & (~ w_data462w[1])), (w_anode529w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode539w = {(w_anode539w[2] & w_data462w[2]), (w_anode539w[1] & (~ w_data462w[1])), (w_anode539w[0] & w_data462w[0]), w_anode464w[3]},
w_anode549w = {(w_anode549w[2] & w_data462w[2]), (w_anode549w[1] & w_data462w[1]), (w_anode549w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode559w = {(w_anode559w[2] & w_data462w[2]), (w_anode559w[1] & w_data462w[1]), (w_anode559w[0] & w_data462w[0]), w_anode464w[3]},
w_anode571w = {(w_anode571w[2] & (~ data_wire[5])), (w_anode571w[1] & (~ data_wire[4])), (w_anode571w[0] & data_wire[3]), 1'b1},
w_anode583w = {(w_anode583w[2] & (~ w_data462w[2])), (w_anode583w[1] & (~ w_data462w[1])), (w_anode583w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode594w = {(w_anode594w[2] & (~ w_data462w[2])), (w_anode594w[1] & (~ w_data462w[1])), (w_anode594w[0] & w_data462w[0]), w_anode571w[3]},
w_anode604w = {(w_anode604w[2] & (~ w_data462w[2])), (w_anode604w[1] & w_data462w[1]), (w_anode604w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode614w = {(w_anode614w[2] & (~ w_data462w[2])), (w_anode614w[1] & w_data462w[1]), (w_anode614w[0] & w_data462w[0]), w_anode571w[3]},
w_anode624w = {(w_anode624w[2] & w_data462w[2]), (w_anode624w[1] & (~ w_data462w[1])), (w_anode624w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode634w = {(w_anode634w[2] & w_data462w[2]), (w_anode634w[1] & (~ w_data462w[1])), (w_anode634w[0] & w_data462w[0]), w_anode571w[3]},
w_anode644w = {(w_anode644w[2] & w_data462w[2]), (w_anode644w[1] & w_data462w[1]), (w_anode644w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode654w = {(w_anode654w[2] & w_data462w[2]), (w_anode654w[1] & w_data462w[1]), (w_anode654w[0] & w_data462w[0]), w_anode571w[3]},
w_anode665w = {(w_anode665w[2] & (~ data_wire[5])), (w_anode665w[1] & data_wire[4]), (w_anode665w[0] & (~ data_wire[3])), 1'b1},
w_anode677w = {(w_anode677w[2] & (~ w_data462w[2])), (w_anode677w[1] & (~ w_data462w[1])), (w_anode677w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode688w = {(w_anode688w[2] & (~ w_data462w[2])), (w_anode688w[1] & (~ w_data462w[1])), (w_anode688w[0] & w_data462w[0]), w_anode665w[3]},
w_anode698w = {(w_anode698w[2] & (~ w_data462w[2])), (w_anode698w[1] & w_data462w[1]), (w_anode698w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode708w = {(w_anode708w[2] & (~ w_data462w[2])), (w_anode708w[1] & w_data462w[1]), (w_anode708w[0] & w_data462w[0]), w_anode665w[3]},
w_anode718w = {(w_anode718w[2] & w_data462w[2]), (w_anode718w[1] & (~ w_data462w[1])), (w_anode718w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode728w = {(w_anode728w[2] & w_data462w[2]), (w_anode728w[1] & (~ w_data462w[1])), (w_anode728w[0] & w_data462w[0]), w_anode665w[3]},
w_anode738w = {(w_anode738w[2] & w_data462w[2]), (w_anode738w[1] & w_data462w[1]), (w_anode738w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode748w = {(w_anode748w[2] & w_data462w[2]), (w_anode748w[1] & w_data462w[1]), (w_anode748w[0] & w_data462w[0]), w_anode665w[3]},
w_anode759w = {(w_anode759w[2] & (~ data_wire[5])), (w_anode759w[1] & data_wire[4]), (w_anode759w[0] & data_wire[3]), 1'b1},
w_anode771w = {(w_anode771w[2] & (~ w_data462w[2])), (w_anode771w[1] & (~ w_data462w[1])), (w_anode771w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode782w = {(w_anode782w[2] & (~ w_data462w[2])), (w_anode782w[1] & (~ w_data462w[1])), (w_anode782w[0] & w_data462w[0]), w_anode759w[3]},
w_anode792w = {(w_anode792w[2] & (~ w_data462w[2])), (w_anode792w[1] & w_data462w[1]), (w_anode792w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode802w = {(w_anode802w[2] & (~ w_data462w[2])), (w_anode802w[1] & w_data462w[1]), (w_anode802w[0] & w_data462w[0]), w_anode759w[3]},
w_anode812w = {(w_anode812w[2] & w_data462w[2]), (w_anode812w[1] & (~ w_data462w[1])), (w_anode812w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode822w = {(w_anode822w[2] & w_data462w[2]), (w_anode822w[1] & (~ w_data462w[1])), (w_anode822w[0] & w_data462w[0]), w_anode759w[3]},
w_anode832w = {(w_anode832w[2] & w_data462w[2]), (w_anode832w[1] & w_data462w[1]), (w_anode832w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode842w = {(w_anode842w[2] & w_data462w[2]), (w_anode842w[1] & w_data462w[1]), (w_anode842w[0] & w_data462w[0]), w_anode759w[3]},
w_anode853w = {(w_anode853w[2] & data_wire[5]), (w_anode853w[1] & (~ data_wire[4])), (w_anode853w[0] & (~ data_wire[3])), 1'b1},
w_anode865w = {(w_anode865w[2] & (~ w_data462w[2])), (w_anode865w[1] & (~ w_data462w[1])), (w_anode865w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode876w = {(w_anode876w[2] & (~ w_data462w[2])), (w_anode876w[1] & (~ w_data462w[1])), (w_anode876w[0] & w_data462w[0]), w_anode853w[3]},
w_anode886w = {(w_anode886w[2] & (~ w_data462w[2])), (w_anode886w[1] & w_data462w[1]), (w_anode886w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode896w = {(w_anode896w[2] & (~ w_data462w[2])), (w_anode896w[1] & w_data462w[1]), (w_anode896w[0] & w_data462w[0]), w_anode853w[3]},
w_anode906w = {(w_anode906w[2] & w_data462w[2]), (w_anode906w[1] & (~ w_data462w[1])), (w_anode906w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode916w = {(w_anode916w[2] & w_data462w[2]), (w_anode916w[1] & (~ w_data462w[1])), (w_anode916w[0] & w_data462w[0]), w_anode853w[3]},
w_anode926w = {(w_anode926w[2] & w_data462w[2]), (w_anode926w[1] & w_data462w[1]), (w_anode926w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode936w = {(w_anode936w[2] & w_data462w[2]), (w_anode936w[1] & w_data462w[1]), (w_anode936w[0] & w_data462w[0]), w_anode853w[3]},
w_anode947w = {(w_anode947w[2] & data_wire[5]), (w_anode947w[1] & (~ data_wire[4])), (w_anode947w[0] & data_wire[3]), 1'b1},
w_anode959w = {(w_anode959w[2] & (~ w_data462w[2])), (w_anode959w[1] & (~ w_data462w[1])), (w_anode959w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode970w = {(w_anode970w[2] & (~ w_data462w[2])), (w_anode970w[1] & (~ w_data462w[1])), (w_anode970w[0] & w_data462w[0]), w_anode947w[3]},
w_anode980w = {(w_anode980w[2] & (~ w_data462w[2])), (w_anode980w[1] & w_data462w[1]), (w_anode980w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode990w = {(w_anode990w[2] & (~ w_data462w[2])), (w_anode990w[1] & w_data462w[1]), (w_anode990w[0] & w_data462w[0]), w_anode947w[3]},
w_data462w = data_wire[2:0];
endmodule //alt_mem_ddrx_ecc_decoder_32_decode
//synthesis_resources = lut 72 mux21 32
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_32_altecc_decoder
(
clk,
reset_n,
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q) /* synthesis synthesis_clearbox=1 */;
parameter CFG_ECC_DECODER_REG = 0;
input clk;
input reset_n;
input [38:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [31:0] q;
wire [63:0] wire_error_bit_decoder_eq;
wire wire_mux21_0_dataout;
wire wire_mux21_1_dataout;
wire wire_mux21_10_dataout;
wire wire_mux21_11_dataout;
wire wire_mux21_12_dataout;
wire wire_mux21_13_dataout;
wire wire_mux21_14_dataout;
wire wire_mux21_15_dataout;
wire wire_mux21_16_dataout;
wire wire_mux21_17_dataout;
wire wire_mux21_18_dataout;
wire wire_mux21_19_dataout;
wire wire_mux21_2_dataout;
wire wire_mux21_20_dataout;
wire wire_mux21_21_dataout;
wire wire_mux21_22_dataout;
wire wire_mux21_23_dataout;
wire wire_mux21_24_dataout;
wire wire_mux21_25_dataout;
wire wire_mux21_26_dataout;
wire wire_mux21_27_dataout;
wire wire_mux21_28_dataout;
wire wire_mux21_29_dataout;
wire wire_mux21_3_dataout;
wire wire_mux21_30_dataout;
wire wire_mux21_31_dataout;
wire wire_mux21_4_dataout;
wire wire_mux21_5_dataout;
wire wire_mux21_6_dataout;
wire wire_mux21_7_dataout;
wire wire_mux21_8_dataout;
wire wire_mux21_9_dataout;
wire data_bit;
wire [31:0] data_t;
wire [38:0] data_wire;
wire [63:0] decode_output;
wire err_corrected_wire;
wire err_detected_wire;
wire err_fatal_wire;
wire [18:0] parity_01_wire;
wire [9:0] parity_02_wire;
wire [4:0] parity_03_wire;
wire [1:0] parity_04_wire;
wire [0:0] parity_05_wire;
wire [5:0] parity_06_wire;
wire parity_bit;
wire [37:0] parity_final_wire;
wire [5:0] parity_t;
wire [31:0] q_wire;
wire syn_bit;
wire syn_e;
wire [4:0] syn_t;
wire [6:0] syndrome_wire;
reg [6:0] syndrome;
reg [38:0] data_reg;
generate
if (CFG_ECC_DECODER_REG == 1)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
syndrome <= {7{1'b0}};
data_reg <= {39{1'b0}};
end else
begin
syndrome <= syndrome_wire;
data_reg <= data_wire;
end
end
end else
begin
always @ (*)
begin
syndrome = syndrome_wire;
data_reg = data_wire;
end
end
endgenerate
alt_mem_ddrx_ecc_decoder_32_decode error_bit_decoder
(
.data(syndrome[5:0]),
.eq(wire_error_bit_decoder_eq));
assign wire_mux21_0_dataout = (syndrome[6] == 1'b1) ? (decode_output[3] ^ data_reg[0]) : data_reg[0];
assign wire_mux21_1_dataout = (syndrome[6] == 1'b1) ? (decode_output[5] ^ data_reg[1]) : data_reg[1];
assign wire_mux21_10_dataout = (syndrome[6] == 1'b1) ? (decode_output[15] ^ data_reg[10]) : data_reg[10];
assign wire_mux21_11_dataout = (syndrome[6] == 1'b1) ? (decode_output[17] ^ data_reg[11]) : data_reg[11];
assign wire_mux21_12_dataout = (syndrome[6] == 1'b1) ? (decode_output[18] ^ data_reg[12]) : data_reg[12];
assign wire_mux21_13_dataout = (syndrome[6] == 1'b1) ? (decode_output[19] ^ data_reg[13]) : data_reg[13];
assign wire_mux21_14_dataout = (syndrome[6] == 1'b1) ? (decode_output[20] ^ data_reg[14]) : data_reg[14];
assign wire_mux21_15_dataout = (syndrome[6] == 1'b1) ? (decode_output[21] ^ data_reg[15]) : data_reg[15];
assign wire_mux21_16_dataout = (syndrome[6] == 1'b1) ? (decode_output[22] ^ data_reg[16]) : data_reg[16];
assign wire_mux21_17_dataout = (syndrome[6] == 1'b1) ? (decode_output[23] ^ data_reg[17]) : data_reg[17];
assign wire_mux21_18_dataout = (syndrome[6] == 1'b1) ? (decode_output[24] ^ data_reg[18]) : data_reg[18];
assign wire_mux21_19_dataout = (syndrome[6] == 1'b1) ? (decode_output[25] ^ data_reg[19]) : data_reg[19];
assign wire_mux21_2_dataout = (syndrome[6] == 1'b1) ? (decode_output[6] ^ data_reg[2]) : data_reg[2];
assign wire_mux21_20_dataout = (syndrome[6] == 1'b1) ? (decode_output[26] ^ data_reg[20]) : data_reg[20];
assign wire_mux21_21_dataout = (syndrome[6] == 1'b1) ? (decode_output[27] ^ data_reg[21]) : data_reg[21];
assign wire_mux21_22_dataout = (syndrome[6] == 1'b1) ? (decode_output[28] ^ data_reg[22]) : data_reg[22];
assign wire_mux21_23_dataout = (syndrome[6] == 1'b1) ? (decode_output[29] ^ data_reg[23]) : data_reg[23];
assign wire_mux21_24_dataout = (syndrome[6] == 1'b1) ? (decode_output[30] ^ data_reg[24]) : data_reg[24];
assign wire_mux21_25_dataout = (syndrome[6] == 1'b1) ? (decode_output[31] ^ data_reg[25]) : data_reg[25];
assign wire_mux21_26_dataout = (syndrome[6] == 1'b1) ? (decode_output[33] ^ data_reg[26]) : data_reg[26];
assign wire_mux21_27_dataout = (syndrome[6] == 1'b1) ? (decode_output[34] ^ data_reg[27]) : data_reg[27];
assign wire_mux21_28_dataout = (syndrome[6] == 1'b1) ? (decode_output[35] ^ data_reg[28]) : data_reg[28];
assign wire_mux21_29_dataout = (syndrome[6] == 1'b1) ? (decode_output[36] ^ data_reg[29]) : data_reg[29];
assign wire_mux21_3_dataout = (syndrome[6] == 1'b1) ? (decode_output[7] ^ data_reg[3]) : data_reg[3];
assign wire_mux21_30_dataout = (syndrome[6] == 1'b1) ? (decode_output[37] ^ data_reg[30]) : data_reg[30];
assign wire_mux21_31_dataout = (syndrome[6] == 1'b1) ? (decode_output[38] ^ data_reg[31]) : data_reg[31];
assign wire_mux21_4_dataout = (syndrome[6] == 1'b1) ? (decode_output[9] ^ data_reg[4]) : data_reg[4];
assign wire_mux21_5_dataout = (syndrome[6] == 1'b1) ? (decode_output[10] ^ data_reg[5]) : data_reg[5];
assign wire_mux21_6_dataout = (syndrome[6] == 1'b1) ? (decode_output[11] ^ data_reg[6]) : data_reg[6];
assign wire_mux21_7_dataout = (syndrome[6] == 1'b1) ? (decode_output[12] ^ data_reg[7]) : data_reg[7];
assign wire_mux21_8_dataout = (syndrome[6] == 1'b1) ? (decode_output[13] ^ data_reg[8]) : data_reg[8];
assign wire_mux21_9_dataout = (syndrome[6] == 1'b1) ? (decode_output[14] ^ data_reg[9]) : data_reg[9];
assign
data_bit = data_t[31],
data_t = {(data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2] | decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
data_wire = data,
decode_output = wire_error_bit_decoder_eq,
err_corrected = err_corrected_wire,
err_corrected_wire = ((syn_bit & syn_e) & data_bit),
err_detected = err_detected_wire,
err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
err_fatal = err_fatal_wire,
err_sbe = syn_e,
err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
parity_01_wire = {(data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[32]},
parity_02_wire = {(data_wire[31] ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[33] ^ data_wire[0])},
parity_03_wire = {(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[34] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[35] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {(((((((((((((((data_wire[36] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[37] ^ data_wire[26])},
parity_bit = parity_t[5],
parity_final_wire = {(data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^ parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[38] ^ data_wire[0])},
parity_t = {(parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
q = q_wire,
q_wire = {wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
syn_bit = syn_t[4],
syn_e = syndrome[6],
syn_t = {(syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
syndrome_wire = {parity_final_wire[37], parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[18]};
endmodule //alt_mem_ddrx_ecc_decoder_32_altecc_decoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_decoder_32
# (
parameter
CFG_ECC_DECODER_REG = 1
)
(
clk,
reset_n,
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [38:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [31:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire4;
wire [31:0] sub_wire3;
wire err_detected = sub_wire0;
wire err_fatal = sub_wire1;
wire err_corrected = sub_wire2;
wire err_sbe = sub_wire4;
wire [31:0] q = sub_wire3[31:0];
alt_mem_ddrx_ecc_decoder_32_altecc_decoder
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
alt_mem_ddrx_ecc_decoder_32_altecc_decoder_component (
.clk (clk),
.reset_n (reset_n),
.data (data),
.err_detected (sub_wire0),
.err_fatal (sub_wire1),
.err_corrected (sub_wire2),
.err_sbe (sub_wire4),
.q (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
// Retrieval info: USED_PORT: data 0 0 39 0 INPUT NODEFVAL "data[38..0]"
// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @data 0 0 39 0 data 0 0 39 0
// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_syn.v TRUE
// Retrieval info: LIB_FILE: lpm

721
FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v
View File

@ -1,721 +0,0 @@
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_decoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_decoder_64.v
// Megafunction Name(s):
// altecc_decoder
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_decoder device_family="Stratix III" lpm_pipeline=0 width_codeword=72 width_dataword=64 data err_corrected err_detected err_fatal q
//VERSION_BEGIN 10.0SP1 cbx_altecc_decoder 2010:08:18:21:16:35:SJ cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//lpm_decode DEVICE_FAMILY="Stratix III" LPM_DECODES=128 LPM_WIDTH=7 data eq
//VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
//synthesis_resources = lut 144
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_decode
(
data,
eq) /* synthesis synthesis_clearbox=1 */;
input [6:0] data;
output [127:0] eq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [6:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] data_wire;
wire enable_wire1;
wire enable_wire2;
wire [127:0] eq_node;
wire [63:0] eq_wire1;
wire [63:0] eq_wire2;
wire [3:0] w_anode1006w;
wire [3:0] w_anode1018w;
wire [3:0] w_anode1029w;
wire [3:0] w_anode1040w;
wire [3:0] w_anode1050w;
wire [3:0] w_anode1060w;
wire [3:0] w_anode1070w;
wire [3:0] w_anode1080w;
wire [3:0] w_anode1090w;
wire [3:0] w_anode1100w;
wire [3:0] w_anode1111w;
wire [3:0] w_anode1122w;
wire [3:0] w_anode1133w;
wire [3:0] w_anode1143w;
wire [3:0] w_anode1153w;
wire [3:0] w_anode1163w;
wire [3:0] w_anode1173w;
wire [3:0] w_anode1183w;
wire [3:0] w_anode1193w;
wire [3:0] w_anode1204w;
wire [3:0] w_anode1215w;
wire [3:0] w_anode1226w;
wire [3:0] w_anode1236w;
wire [3:0] w_anode1246w;
wire [3:0] w_anode1256w;
wire [3:0] w_anode1266w;
wire [3:0] w_anode1276w;
wire [3:0] w_anode1286w;
wire [3:0] w_anode1297w;
wire [3:0] w_anode1308w;
wire [3:0] w_anode1319w;
wire [3:0] w_anode1329w;
wire [3:0] w_anode1339w;
wire [3:0] w_anode1349w;
wire [3:0] w_anode1359w;
wire [3:0] w_anode1369w;
wire [3:0] w_anode1379w;
wire [3:0] w_anode1390w;
wire [3:0] w_anode1401w;
wire [3:0] w_anode1412w;
wire [3:0] w_anode1422w;
wire [3:0] w_anode1432w;
wire [3:0] w_anode1442w;
wire [3:0] w_anode1452w;
wire [3:0] w_anode1462w;
wire [3:0] w_anode1472w;
wire [3:0] w_anode1483w;
wire [3:0] w_anode1494w;
wire [3:0] w_anode1505w;
wire [3:0] w_anode1515w;
wire [3:0] w_anode1525w;
wire [3:0] w_anode1535w;
wire [3:0] w_anode1545w;
wire [3:0] w_anode1555w;
wire [3:0] w_anode1565w;
wire [3:0] w_anode1576w;
wire [3:0] w_anode1587w;
wire [3:0] w_anode1598w;
wire [3:0] w_anode1608w;
wire [3:0] w_anode1618w;
wire [3:0] w_anode1628w;
wire [3:0] w_anode1638w;
wire [3:0] w_anode1648w;
wire [3:0] w_anode1658w;
wire [3:0] w_anode1670w;
wire [3:0] w_anode1681w;
wire [3:0] w_anode1698w;
wire [3:0] w_anode1708w;
wire [3:0] w_anode1718w;
wire [3:0] w_anode1728w;
wire [3:0] w_anode1738w;
wire [3:0] w_anode1748w;
wire [3:0] w_anode1758w;
wire [3:0] w_anode1770w;
wire [3:0] w_anode1781w;
wire [3:0] w_anode1792w;
wire [3:0] w_anode1802w;
wire [3:0] w_anode1812w;
wire [3:0] w_anode1822w;
wire [3:0] w_anode1832w;
wire [3:0] w_anode1842w;
wire [3:0] w_anode1852w;
wire [3:0] w_anode1863w;
wire [3:0] w_anode1874w;
wire [3:0] w_anode1885w;
wire [3:0] w_anode1895w;
wire [3:0] w_anode1905w;
wire [3:0] w_anode1915w;
wire [3:0] w_anode1925w;
wire [3:0] w_anode1935w;
wire [3:0] w_anode1945w;
wire [3:0] w_anode1956w;
wire [3:0] w_anode1967w;
wire [3:0] w_anode1978w;
wire [3:0] w_anode1988w;
wire [3:0] w_anode1998w;
wire [3:0] w_anode2008w;
wire [3:0] w_anode2018w;
wire [3:0] w_anode2028w;
wire [3:0] w_anode2038w;
wire [3:0] w_anode2049w;
wire [3:0] w_anode2060w;
wire [3:0] w_anode2071w;
wire [3:0] w_anode2081w;
wire [3:0] w_anode2091w;
wire [3:0] w_anode2101w;
wire [3:0] w_anode2111w;
wire [3:0] w_anode2121w;
wire [3:0] w_anode2131w;
wire [3:0] w_anode2142w;
wire [3:0] w_anode2153w;
wire [3:0] w_anode2164w;
wire [3:0] w_anode2174w;
wire [3:0] w_anode2184w;
wire [3:0] w_anode2194w;
wire [3:0] w_anode2204w;
wire [3:0] w_anode2214w;
wire [3:0] w_anode2224w;
wire [3:0] w_anode2235w;
wire [3:0] w_anode2246w;
wire [3:0] w_anode2257w;
wire [3:0] w_anode2267w;
wire [3:0] w_anode2277w;
wire [3:0] w_anode2287w;
wire [3:0] w_anode2297w;
wire [3:0] w_anode2307w;
wire [3:0] w_anode2317w;
wire [3:0] w_anode2328w;
wire [3:0] w_anode2339w;
wire [3:0] w_anode2350w;
wire [3:0] w_anode2360w;
wire [3:0] w_anode2370w;
wire [3:0] w_anode2380w;
wire [3:0] w_anode2390w;
wire [3:0] w_anode2400w;
wire [3:0] w_anode2410w;
wire [3:0] w_anode912w;
wire [3:0] w_anode929w;
wire [3:0] w_anode946w;
wire [3:0] w_anode956w;
wire [3:0] w_anode966w;
wire [3:0] w_anode976w;
wire [3:0] w_anode986w;
wire [3:0] w_anode996w;
wire [2:0] w_data1669w;
wire [2:0] w_data910w;
assign
data_wire = data[5:0],
enable_wire1 = (~ data[6]),
enable_wire2 = data[6],
eq = eq_node,
eq_node = {eq_wire2[63:0], eq_wire1},
eq_wire1 = {{w_anode1658w[3], w_anode1648w[3], w_anode1638w[3], w_anode1628w[3], w_anode1618w[3], w_anode1608w[3], w_anode1598w[3], w_anode1587w[3]}, {w_anode1565w[3], w_anode1555w[3], w_anode1545w[3], w_anode1535w[3], w_anode1525w[3], w_anode1515w[3], w_anode1505w[3], w_anode1494w[3]}, {w_anode1472w[3], w_anode1462w[3], w_anode1452w[3], w_anode1442w[3], w_anode1432w[3], w_anode1422w[3], w_anode1412w[3], w_anode1401w[3]}, {w_anode1379w[3], w_anode1369w[3], w_anode1359w[3], w_anode1349w[3], w_anode1339w[3], w_anode1329w[3], w_anode1319w[3], w_anode1308w[3]}, {w_anode1286w[3], w_anode1276w[3], w_anode1266w[3], w_anode1256w[3], w_anode1246w[3], w_anode1236w[3], w_anode1226w[3], w_anode1215w[3]}, {w_anode1193w[3], w_anode1183w[3], w_anode1173w[3], w_anode1163w[3], w_anode1153w[3], w_anode1143w[3], w_anode1133w[3], w_anode1122w[3]}, {w_anode1100w[3], w_anode1090w[3], w_anode1080w[3], w_anode1070w[3], w_anode1060w[3], w_anode1050w[3], w_anode1040w[3], w_anode1029w[3]}, {w_anode1006w[3], w_anode996w[3], w_anode986w[3], w_anode976w[3], w_anode966w[3], w_anode956w[3], w_anode946w[3], w_anode929w[3]}},
eq_wire2 = {{w_anode2410w[3], w_anode2400w[3], w_anode2390w[3], w_anode2380w[3], w_anode2370w[3], w_anode2360w[3], w_anode2350w[3], w_anode2339w[3]}, {w_anode2317w[3], w_anode2307w[3], w_anode2297w[3], w_anode2287w[3], w_anode2277w[3], w_anode2267w[3], w_anode2257w[3], w_anode2246w[3]}, {w_anode2224w[3], w_anode2214w[3], w_anode2204w[3], w_anode2194w[3], w_anode2184w[3], w_anode2174w[3], w_anode2164w[3], w_anode2153w[3]}, {w_anode2131w[3], w_anode2121w[3], w_anode2111w[3], w_anode2101w[3], w_anode2091w[3], w_anode2081w[3], w_anode2071w[3], w_anode2060w[3]}, {w_anode2038w[3], w_anode2028w[3], w_anode2018w[3], w_anode2008w[3], w_anode1998w[3], w_anode1988w[3], w_anode1978w[3], w_anode1967w[3]}, {w_anode1945w[3], w_anode1935w[3], w_anode1925w[3], w_anode1915w[3], w_anode1905w[3], w_anode1895w[3], w_anode1885w[3], w_anode1874w[3]}, {w_anode1852w[3], w_anode1842w[3], w_anode1832w[3], w_anode1822w[3], w_anode1812w[3], w_anode1802w[3], w_anode1792w[3], w_anode1781w[3]}, {w_anode1758w[3], w_anode1748w[3], w_anode1738w[3], w_anode1728w[3], w_anode1718w[3], w_anode1708w[3], w_anode1698w[3], w_anode1681w[3]}},
w_anode1006w = {(w_anode1006w[2] & w_data910w[2]), (w_anode1006w[1] & w_data910w[1]), (w_anode1006w[0] & w_data910w[0]), w_anode912w[3]},
w_anode1018w = {(w_anode1018w[2] & (~ data_wire[5])), (w_anode1018w[1] & (~ data_wire[4])), (w_anode1018w[0] & data_wire[3]), enable_wire1},
w_anode1029w = {(w_anode1029w[2] & (~ w_data910w[2])), (w_anode1029w[1] & (~ w_data910w[1])), (w_anode1029w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1040w = {(w_anode1040w[2] & (~ w_data910w[2])), (w_anode1040w[1] & (~ w_data910w[1])), (w_anode1040w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1050w = {(w_anode1050w[2] & (~ w_data910w[2])), (w_anode1050w[1] & w_data910w[1]), (w_anode1050w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1060w = {(w_anode1060w[2] & (~ w_data910w[2])), (w_anode1060w[1] & w_data910w[1]), (w_anode1060w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1070w = {(w_anode1070w[2] & w_data910w[2]), (w_anode1070w[1] & (~ w_data910w[1])), (w_anode1070w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1080w = {(w_anode1080w[2] & w_data910w[2]), (w_anode1080w[1] & (~ w_data910w[1])), (w_anode1080w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1090w = {(w_anode1090w[2] & w_data910w[2]), (w_anode1090w[1] & w_data910w[1]), (w_anode1090w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1100w = {(w_anode1100w[2] & w_data910w[2]), (w_anode1100w[1] & w_data910w[1]), (w_anode1100w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1111w = {(w_anode1111w[2] & (~ data_wire[5])), (w_anode1111w[1] & data_wire[4]), (w_anode1111w[0] & (~ data_wire[3])), enable_wire1},
w_anode1122w = {(w_anode1122w[2] & (~ w_data910w[2])), (w_anode1122w[1] & (~ w_data910w[1])), (w_anode1122w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1133w = {(w_anode1133w[2] & (~ w_data910w[2])), (w_anode1133w[1] & (~ w_data910w[1])), (w_anode1133w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1143w = {(w_anode1143w[2] & (~ w_data910w[2])), (w_anode1143w[1] & w_data910w[1]), (w_anode1143w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1153w = {(w_anode1153w[2] & (~ w_data910w[2])), (w_anode1153w[1] & w_data910w[1]), (w_anode1153w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1163w = {(w_anode1163w[2] & w_data910w[2]), (w_anode1163w[1] & (~ w_data910w[1])), (w_anode1163w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1173w = {(w_anode1173w[2] & w_data910w[2]), (w_anode1173w[1] & (~ w_data910w[1])), (w_anode1173w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1183w = {(w_anode1183w[2] & w_data910w[2]), (w_anode1183w[1] & w_data910w[1]), (w_anode1183w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1193w = {(w_anode1193w[2] & w_data910w[2]), (w_anode1193w[1] & w_data910w[1]), (w_anode1193w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1204w = {(w_anode1204w[2] & (~ data_wire[5])), (w_anode1204w[1] & data_wire[4]), (w_anode1204w[0] & data_wire[3]), enable_wire1},
w_anode1215w = {(w_anode1215w[2] & (~ w_data910w[2])), (w_anode1215w[1] & (~ w_data910w[1])), (w_anode1215w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1226w = {(w_anode1226w[2] & (~ w_data910w[2])), (w_anode1226w[1] & (~ w_data910w[1])), (w_anode1226w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1236w = {(w_anode1236w[2] & (~ w_data910w[2])), (w_anode1236w[1] & w_data910w[1]), (w_anode1236w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1246w = {(w_anode1246w[2] & (~ w_data910w[2])), (w_anode1246w[1] & w_data910w[1]), (w_anode1246w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1256w = {(w_anode1256w[2] & w_data910w[2]), (w_anode1256w[1] & (~ w_data910w[1])), (w_anode1256w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1266w = {(w_anode1266w[2] & w_data910w[2]), (w_anode1266w[1] & (~ w_data910w[1])), (w_anode1266w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1276w = {(w_anode1276w[2] & w_data910w[2]), (w_anode1276w[1] & w_data910w[1]), (w_anode1276w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1286w = {(w_anode1286w[2] & w_data910w[2]), (w_anode1286w[1] & w_data910w[1]), (w_anode1286w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1297w = {(w_anode1297w[2] & data_wire[5]), (w_anode1297w[1] & (~ data_wire[4])), (w_anode1297w[0] & (~ data_wire[3])), enable_wire1},
w_anode1308w = {(w_anode1308w[2] & (~ w_data910w[2])), (w_anode1308w[1] & (~ w_data910w[1])), (w_anode1308w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1319w = {(w_anode1319w[2] & (~ w_data910w[2])), (w_anode1319w[1] & (~ w_data910w[1])), (w_anode1319w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1329w = {(w_anode1329w[2] & (~ w_data910w[2])), (w_anode1329w[1] & w_data910w[1]), (w_anode1329w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1339w = {(w_anode1339w[2] & (~ w_data910w[2])), (w_anode1339w[1] & w_data910w[1]), (w_anode1339w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1349w = {(w_anode1349w[2] & w_data910w[2]), (w_anode1349w[1] & (~ w_data910w[1])), (w_anode1349w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1359w = {(w_anode1359w[2] & w_data910w[2]), (w_anode1359w[1] & (~ w_data910w[1])), (w_anode1359w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1369w = {(w_anode1369w[2] & w_data910w[2]), (w_anode1369w[1] & w_data910w[1]), (w_anode1369w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1379w = {(w_anode1379w[2] & w_data910w[2]), (w_anode1379w[1] & w_data910w[1]), (w_anode1379w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1390w = {(w_anode1390w[2] & data_wire[5]), (w_anode1390w[1] & (~ data_wire[4])), (w_anode1390w[0] & data_wire[3]), enable_wire1},
w_anode1401w = {(w_anode1401w[2] & (~ w_data910w[2])), (w_anode1401w[1] & (~ w_data910w[1])), (w_anode1401w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1412w = {(w_anode1412w[2] & (~ w_data910w[2])), (w_anode1412w[1] & (~ w_data910w[1])), (w_anode1412w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1422w = {(w_anode1422w[2] & (~ w_data910w[2])), (w_anode1422w[1] & w_data910w[1]), (w_anode1422w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1432w = {(w_anode1432w[2] & (~ w_data910w[2])), (w_anode1432w[1] & w_data910w[1]), (w_anode1432w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1442w = {(w_anode1442w[2] & w_data910w[2]), (w_anode1442w[1] & (~ w_data910w[1])), (w_anode1442w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1452w = {(w_anode1452w[2] & w_data910w[2]), (w_anode1452w[1] & (~ w_data910w[1])), (w_anode1452w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1462w = {(w_anode1462w[2] & w_data910w[2]), (w_anode1462w[1] & w_data910w[1]), (w_anode1462w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1472w = {(w_anode1472w[2] & w_data910w[2]), (w_anode1472w[1] & w_data910w[1]), (w_anode1472w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1483w = {(w_anode1483w[2] & data_wire[5]), (w_anode1483w[1] & data_wire[4]), (w_anode1483w[0] & (~ data_wire[3])), enable_wire1},
w_anode1494w = {(w_anode1494w[2] & (~ w_data910w[2])), (w_anode1494w[1] & (~ w_data910w[1])), (w_anode1494w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1505w = {(w_anode1505w[2] & (~ w_data910w[2])), (w_anode1505w[1] & (~ w_data910w[1])), (w_anode1505w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1515w = {(w_anode1515w[2] & (~ w_data910w[2])), (w_anode1515w[1] & w_data910w[1]), (w_anode1515w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1525w = {(w_anode1525w[2] & (~ w_data910w[2])), (w_anode1525w[1] & w_data910w[1]), (w_anode1525w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1535w = {(w_anode1535w[2] & w_data910w[2]), (w_anode1535w[1] & (~ w_data910w[1])), (w_anode1535w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1545w = {(w_anode1545w[2] & w_data910w[2]), (w_anode1545w[1] & (~ w_data910w[1])), (w_anode1545w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1555w = {(w_anode1555w[2] & w_data910w[2]), (w_anode1555w[1] & w_data910w[1]), (w_anode1555w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1565w = {(w_anode1565w[2] & w_data910w[2]), (w_anode1565w[1] & w_data910w[1]), (w_anode1565w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1576w = {(w_anode1576w[2] & data_wire[5]), (w_anode1576w[1] & data_wire[4]), (w_anode1576w[0] & data_wire[3]), enable_wire1},
w_anode1587w = {(w_anode1587w[2] & (~ w_data910w[2])), (w_anode1587w[1] & (~ w_data910w[1])), (w_anode1587w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1598w = {(w_anode1598w[2] & (~ w_data910w[2])), (w_anode1598w[1] & (~ w_data910w[1])), (w_anode1598w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1608w = {(w_anode1608w[2] & (~ w_data910w[2])), (w_anode1608w[1] & w_data910w[1]), (w_anode1608w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1618w = {(w_anode1618w[2] & (~ w_data910w[2])), (w_anode1618w[1] & w_data910w[1]), (w_anode1618w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1628w = {(w_anode1628w[2] & w_data910w[2]), (w_anode1628w[1] & (~ w_data910w[1])), (w_anode1628w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1638w = {(w_anode1638w[2] & w_data910w[2]), (w_anode1638w[1] & (~ w_data910w[1])), (w_anode1638w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1648w = {(w_anode1648w[2] & w_data910w[2]), (w_anode1648w[1] & w_data910w[1]), (w_anode1648w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1658w = {(w_anode1658w[2] & w_data910w[2]), (w_anode1658w[1] & w_data910w[1]), (w_anode1658w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1670w = {(w_anode1670w[2] & (~ data_wire[5])), (w_anode1670w[1] & (~ data_wire[4])), (w_anode1670w[0] & (~ data_wire[3])), enable_wire2},
w_anode1681w = {(w_anode1681w[2] & (~ w_data1669w[2])), (w_anode1681w[1] & (~ w_data1669w[1])), (w_anode1681w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1698w = {(w_anode1698w[2] & (~ w_data1669w[2])), (w_anode1698w[1] & (~ w_data1669w[1])), (w_anode1698w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1708w = {(w_anode1708w[2] & (~ w_data1669w[2])), (w_anode1708w[1] & w_data1669w[1]), (w_anode1708w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1718w = {(w_anode1718w[2] & (~ w_data1669w[2])), (w_anode1718w[1] & w_data1669w[1]), (w_anode1718w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1728w = {(w_anode1728w[2] & w_data1669w[2]), (w_anode1728w[1] & (~ w_data1669w[1])), (w_anode1728w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1738w = {(w_anode1738w[2] & w_data1669w[2]), (w_anode1738w[1] & (~ w_data1669w[1])), (w_anode1738w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1748w = {(w_anode1748w[2] & w_data1669w[2]), (w_anode1748w[1] & w_data1669w[1]), (w_anode1748w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1758w = {(w_anode1758w[2] & w_data1669w[2]), (w_anode1758w[1] & w_data1669w[1]), (w_anode1758w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1770w = {(w_anode1770w[2] & (~ data_wire[5])), (w_anode1770w[1] & (~ data_wire[4])), (w_anode1770w[0] & data_wire[3]), enable_wire2},
w_anode1781w = {(w_anode1781w[2] & (~ w_data1669w[2])), (w_anode1781w[1] & (~ w_data1669w[1])), (w_anode1781w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1792w = {(w_anode1792w[2] & (~ w_data1669w[2])), (w_anode1792w[1] & (~ w_data1669w[1])), (w_anode1792w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1802w = {(w_anode1802w[2] & (~ w_data1669w[2])), (w_anode1802w[1] & w_data1669w[1]), (w_anode1802w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1812w = {(w_anode1812w[2] & (~ w_data1669w[2])), (w_anode1812w[1] & w_data1669w[1]), (w_anode1812w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1822w = {(w_anode1822w[2] & w_data1669w[2]), (w_anode1822w[1] & (~ w_data1669w[1])), (w_anode1822w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1832w = {(w_anode1832w[2] & w_data1669w[2]), (w_anode1832w[1] & (~ w_data1669w[1])), (w_anode1832w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1842w = {(w_anode1842w[2] & w_data1669w[2]), (w_anode1842w[1] & w_data1669w[1]), (w_anode1842w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1852w = {(w_anode1852w[2] & w_data1669w[2]), (w_anode1852w[1] & w_data1669w[1]), (w_anode1852w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1863w = {(w_anode1863w[2] & (~ data_wire[5])), (w_anode1863w[1] & data_wire[4]), (w_anode1863w[0] & (~ data_wire[3])), enable_wire2},
w_anode1874w = {(w_anode1874w[2] & (~ w_data1669w[2])), (w_anode1874w[1] & (~ w_data1669w[1])), (w_anode1874w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1885w = {(w_anode1885w[2] & (~ w_data1669w[2])), (w_anode1885w[1] & (~ w_data1669w[1])), (w_anode1885w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1895w = {(w_anode1895w[2] & (~ w_data1669w[2])), (w_anode1895w[1] & w_data1669w[1]), (w_anode1895w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1905w = {(w_anode1905w[2] & (~ w_data1669w[2])), (w_anode1905w[1] & w_data1669w[1]), (w_anode1905w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1915w = {(w_anode1915w[2] & w_data1669w[2]), (w_anode1915w[1] & (~ w_data1669w[1])), (w_anode1915w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1925w = {(w_anode1925w[2] & w_data1669w[2]), (w_anode1925w[1] & (~ w_data1669w[1])), (w_anode1925w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1935w = {(w_anode1935w[2] & w_data1669w[2]), (w_anode1935w[1] & w_data1669w[1]), (w_anode1935w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1945w = {(w_anode1945w[2] & w_data1669w[2]), (w_anode1945w[1] & w_data1669w[1]), (w_anode1945w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1956w = {(w_anode1956w[2] & (~ data_wire[5])), (w_anode1956w[1] & data_wire[4]), (w_anode1956w[0] & data_wire[3]), enable_wire2},
w_anode1967w = {(w_anode1967w[2] & (~ w_data1669w[2])), (w_anode1967w[1] & (~ w_data1669w[1])), (w_anode1967w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1978w = {(w_anode1978w[2] & (~ w_data1669w[2])), (w_anode1978w[1] & (~ w_data1669w[1])), (w_anode1978w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode1988w = {(w_anode1988w[2] & (~ w_data1669w[2])), (w_anode1988w[1] & w_data1669w[1]), (w_anode1988w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1998w = {(w_anode1998w[2] & (~ w_data1669w[2])), (w_anode1998w[1] & w_data1669w[1]), (w_anode1998w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2008w = {(w_anode2008w[2] & w_data1669w[2]), (w_anode2008w[1] & (~ w_data1669w[1])), (w_anode2008w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2018w = {(w_anode2018w[2] & w_data1669w[2]), (w_anode2018w[1] & (~ w_data1669w[1])), (w_anode2018w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2028w = {(w_anode2028w[2] & w_data1669w[2]), (w_anode2028w[1] & w_data1669w[1]), (w_anode2028w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2038w = {(w_anode2038w[2] & w_data1669w[2]), (w_anode2038w[1] & w_data1669w[1]), (w_anode2038w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2049w = {(w_anode2049w[2] & data_wire[5]), (w_anode2049w[1] & (~ data_wire[4])), (w_anode2049w[0] & (~ data_wire[3])), enable_wire2},
w_anode2060w = {(w_anode2060w[2] & (~ w_data1669w[2])), (w_anode2060w[1] & (~ w_data1669w[1])), (w_anode2060w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2071w = {(w_anode2071w[2] & (~ w_data1669w[2])), (w_anode2071w[1] & (~ w_data1669w[1])), (w_anode2071w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2081w = {(w_anode2081w[2] & (~ w_data1669w[2])), (w_anode2081w[1] & w_data1669w[1]), (w_anode2081w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2091w = {(w_anode2091w[2] & (~ w_data1669w[2])), (w_anode2091w[1] & w_data1669w[1]), (w_anode2091w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2101w = {(w_anode2101w[2] & w_data1669w[2]), (w_anode2101w[1] & (~ w_data1669w[1])), (w_anode2101w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2111w = {(w_anode2111w[2] & w_data1669w[2]), (w_anode2111w[1] & (~ w_data1669w[1])), (w_anode2111w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2121w = {(w_anode2121w[2] & w_data1669w[2]), (w_anode2121w[1] & w_data1669w[1]), (w_anode2121w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2131w = {(w_anode2131w[2] & w_data1669w[2]), (w_anode2131w[1] & w_data1669w[1]), (w_anode2131w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2142w = {(w_anode2142w[2] & data_wire[5]), (w_anode2142w[1] & (~ data_wire[4])), (w_anode2142w[0] & data_wire[3]), enable_wire2},
w_anode2153w = {(w_anode2153w[2] & (~ w_data1669w[2])), (w_anode2153w[1] & (~ w_data1669w[1])), (w_anode2153w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2164w = {(w_anode2164w[2] & (~ w_data1669w[2])), (w_anode2164w[1] & (~ w_data1669w[1])), (w_anode2164w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2174w = {(w_anode2174w[2] & (~ w_data1669w[2])), (w_anode2174w[1] & w_data1669w[1]), (w_anode2174w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2184w = {(w_anode2184w[2] & (~ w_data1669w[2])), (w_anode2184w[1] & w_data1669w[1]), (w_anode2184w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2194w = {(w_anode2194w[2] & w_data1669w[2]), (w_anode2194w[1] & (~ w_data1669w[1])), (w_anode2194w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2204w = {(w_anode2204w[2] & w_data1669w[2]), (w_anode2204w[1] & (~ w_data1669w[1])), (w_anode2204w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2214w = {(w_anode2214w[2] & w_data1669w[2]), (w_anode2214w[1] & w_data1669w[1]), (w_anode2214w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2224w = {(w_anode2224w[2] & w_data1669w[2]), (w_anode2224w[1] & w_data1669w[1]), (w_anode2224w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2235w = {(w_anode2235w[2] & data_wire[5]), (w_anode2235w[1] & data_wire[4]), (w_anode2235w[0] & (~ data_wire[3])), enable_wire2},
w_anode2246w = {(w_anode2246w[2] & (~ w_data1669w[2])), (w_anode2246w[1] & (~ w_data1669w[1])), (w_anode2246w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2257w = {(w_anode2257w[2] & (~ w_data1669w[2])), (w_anode2257w[1] & (~ w_data1669w[1])), (w_anode2257w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2267w = {(w_anode2267w[2] & (~ w_data1669w[2])), (w_anode2267w[1] & w_data1669w[1]), (w_anode2267w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2277w = {(w_anode2277w[2] & (~ w_data1669w[2])), (w_anode2277w[1] & w_data1669w[1]), (w_anode2277w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2287w = {(w_anode2287w[2] & w_data1669w[2]), (w_anode2287w[1] & (~ w_data1669w[1])), (w_anode2287w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2297w = {(w_anode2297w[2] & w_data1669w[2]), (w_anode2297w[1] & (~ w_data1669w[1])), (w_anode2297w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2307w = {(w_anode2307w[2] & w_data1669w[2]), (w_anode2307w[1] & w_data1669w[1]), (w_anode2307w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2317w = {(w_anode2317w[2] & w_data1669w[2]), (w_anode2317w[1] & w_data1669w[1]), (w_anode2317w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2328w = {(w_anode2328w[2] & data_wire[5]), (w_anode2328w[1] & data_wire[4]), (w_anode2328w[0] & data_wire[3]), enable_wire2},
w_anode2339w = {(w_anode2339w[2] & (~ w_data1669w[2])), (w_anode2339w[1] & (~ w_data1669w[1])), (w_anode2339w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2350w = {(w_anode2350w[2] & (~ w_data1669w[2])), (w_anode2350w[1] & (~ w_data1669w[1])), (w_anode2350w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2360w = {(w_anode2360w[2] & (~ w_data1669w[2])), (w_anode2360w[1] & w_data1669w[1]), (w_anode2360w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2370w = {(w_anode2370w[2] & (~ w_data1669w[2])), (w_anode2370w[1] & w_data1669w[1]), (w_anode2370w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2380w = {(w_anode2380w[2] & w_data1669w[2]), (w_anode2380w[1] & (~ w_data1669w[1])), (w_anode2380w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2390w = {(w_anode2390w[2] & w_data1669w[2]), (w_anode2390w[1] & (~ w_data1669w[1])), (w_anode2390w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2400w = {(w_anode2400w[2] & w_data1669w[2]), (w_anode2400w[1] & w_data1669w[1]), (w_anode2400w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2410w = {(w_anode2410w[2] & w_data1669w[2]), (w_anode2410w[1] & w_data1669w[1]), (w_anode2410w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode912w = {(w_anode912w[2] & (~ data_wire[5])), (w_anode912w[1] & (~ data_wire[4])), (w_anode912w[0] & (~ data_wire[3])), enable_wire1},
w_anode929w = {(w_anode929w[2] & (~ w_data910w[2])), (w_anode929w[1] & (~ w_data910w[1])), (w_anode929w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode946w = {(w_anode946w[2] & (~ w_data910w[2])), (w_anode946w[1] & (~ w_data910w[1])), (w_anode946w[0] & w_data910w[0]), w_anode912w[3]},
w_anode956w = {(w_anode956w[2] & (~ w_data910w[2])), (w_anode956w[1] & w_data910w[1]), (w_anode956w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode966w = {(w_anode966w[2] & (~ w_data910w[2])), (w_anode966w[1] & w_data910w[1]), (w_anode966w[0] & w_data910w[0]), w_anode912w[3]},
w_anode976w = {(w_anode976w[2] & w_data910w[2]), (w_anode976w[1] & (~ w_data910w[1])), (w_anode976w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode986w = {(w_anode986w[2] & w_data910w[2]), (w_anode986w[1] & (~ w_data910w[1])), (w_anode986w[0] & w_data910w[0]), w_anode912w[3]},
w_anode996w = {(w_anode996w[2] & w_data910w[2]), (w_anode996w[1] & w_data910w[1]), (w_anode996w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_data1669w = data_wire[2:0],
w_data910w = data_wire[2:0];
endmodule //alt_mem_ddrx_ecc_decoder_64_decode
//synthesis_resources = lut 144 mux21 64
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_altecc_decoder
(
clk,
reset_n,
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q) /* synthesis synthesis_clearbox=1 */;
input clk;
input reset_n;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
parameter CFG_ECC_DECODER_REG = 0;
wire [127:0] wire_error_bit_decoder_eq;
wire wire_mux21_0_dataout;
wire wire_mux21_1_dataout;
wire wire_mux21_10_dataout;
wire wire_mux21_11_dataout;
wire wire_mux21_12_dataout;
wire wire_mux21_13_dataout;
wire wire_mux21_14_dataout;
wire wire_mux21_15_dataout;
wire wire_mux21_16_dataout;
wire wire_mux21_17_dataout;
wire wire_mux21_18_dataout;
wire wire_mux21_19_dataout;
wire wire_mux21_2_dataout;
wire wire_mux21_20_dataout;
wire wire_mux21_21_dataout;
wire wire_mux21_22_dataout;
wire wire_mux21_23_dataout;
wire wire_mux21_24_dataout;
wire wire_mux21_25_dataout;
wire wire_mux21_26_dataout;
wire wire_mux21_27_dataout;
wire wire_mux21_28_dataout;
wire wire_mux21_29_dataout;
wire wire_mux21_3_dataout;
wire wire_mux21_30_dataout;
wire wire_mux21_31_dataout;
wire wire_mux21_32_dataout;
wire wire_mux21_33_dataout;
wire wire_mux21_34_dataout;
wire wire_mux21_35_dataout;
wire wire_mux21_36_dataout;
wire wire_mux21_37_dataout;
wire wire_mux21_38_dataout;
wire wire_mux21_39_dataout;
wire wire_mux21_4_dataout;
wire wire_mux21_40_dataout;
wire wire_mux21_41_dataout;
wire wire_mux21_42_dataout;
wire wire_mux21_43_dataout;
wire wire_mux21_44_dataout;
wire wire_mux21_45_dataout;
wire wire_mux21_46_dataout;
wire wire_mux21_47_dataout;
wire wire_mux21_48_dataout;
wire wire_mux21_49_dataout;
wire wire_mux21_5_dataout;
wire wire_mux21_50_dataout;
wire wire_mux21_51_dataout;
wire wire_mux21_52_dataout;
wire wire_mux21_53_dataout;
wire wire_mux21_54_dataout;
wire wire_mux21_55_dataout;
wire wire_mux21_56_dataout;
wire wire_mux21_57_dataout;
wire wire_mux21_58_dataout;
wire wire_mux21_59_dataout;
wire wire_mux21_6_dataout;
wire wire_mux21_60_dataout;
wire wire_mux21_61_dataout;
wire wire_mux21_62_dataout;
wire wire_mux21_63_dataout;
wire wire_mux21_7_dataout;
wire wire_mux21_8_dataout;
wire wire_mux21_9_dataout;
wire data_bit;
wire [63:0] data_t;
wire [71:0] data_wire;
wire [127:0] decode_output;
wire err_corrected_wire;
wire err_detected_wire;
wire err_fatal_wire;
wire [35:0] parity_01_wire;
wire [17:0] parity_02_wire;
wire [8:0] parity_03_wire;
wire [3:0] parity_04_wire;
wire [1:0] parity_05_wire;
wire [30:0] parity_06_wire;
wire [6:0] parity_07_wire;
wire parity_bit;
wire [70:0] parity_final_wire;
wire [6:0] parity_t;
wire [63:0] q_wire;
wire syn_bit;
wire syn_e;
wire [5:0] syn_t;
wire [7:0] syndrome_wire;
reg [7:0] syndrome;
reg [71:0] data_reg;
generate
if (CFG_ECC_DECODER_REG == 1)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
syndrome <= {8{1'b0}};
data_reg <= {72{1'b0}};
end else
begin
syndrome <= syndrome_wire;
data_reg <= data_wire;
end
end
end else
begin
always @ (*)
begin
syndrome = syndrome_wire;
data_reg = data_wire;
end
end
endgenerate
alt_mem_ddrx_ecc_decoder_64_decode error_bit_decoder
(
.data(syndrome[6:0]),
.eq(wire_error_bit_decoder_eq));
assign wire_mux21_0_dataout = (syndrome[7] == 1'b1) ? (decode_output[3] ^ data_reg[0]) : data_reg[0];
assign wire_mux21_1_dataout = (syndrome[7] == 1'b1) ? (decode_output[5] ^ data_reg[1]) : data_reg[1];
assign wire_mux21_10_dataout = (syndrome[7] == 1'b1) ? (decode_output[15] ^ data_reg[10]) : data_reg[10];
assign wire_mux21_11_dataout = (syndrome[7] == 1'b1) ? (decode_output[17] ^ data_reg[11]) : data_reg[11];
assign wire_mux21_12_dataout = (syndrome[7] == 1'b1) ? (decode_output[18] ^ data_reg[12]) : data_reg[12];
assign wire_mux21_13_dataout = (syndrome[7] == 1'b1) ? (decode_output[19] ^ data_reg[13]) : data_reg[13];
assign wire_mux21_14_dataout = (syndrome[7] == 1'b1) ? (decode_output[20] ^ data_reg[14]) : data_reg[14];
assign wire_mux21_15_dataout = (syndrome[7] == 1'b1) ? (decode_output[21] ^ data_reg[15]) : data_reg[15];
assign wire_mux21_16_dataout = (syndrome[7] == 1'b1) ? (decode_output[22] ^ data_reg[16]) : data_reg[16];
assign wire_mux21_17_dataout = (syndrome[7] == 1'b1) ? (decode_output[23] ^ data_reg[17]) : data_reg[17];
assign wire_mux21_18_dataout = (syndrome[7] == 1'b1) ? (decode_output[24] ^ data_reg[18]) : data_reg[18];
assign wire_mux21_19_dataout = (syndrome[7] == 1'b1) ? (decode_output[25] ^ data_reg[19]) : data_reg[19];
assign wire_mux21_2_dataout = (syndrome[7] == 1'b1) ? (decode_output[6] ^ data_reg[2]) : data_reg[2];
assign wire_mux21_20_dataout = (syndrome[7] == 1'b1) ? (decode_output[26] ^ data_reg[20]) : data_reg[20];
assign wire_mux21_21_dataout = (syndrome[7] == 1'b1) ? (decode_output[27] ^ data_reg[21]) : data_reg[21];
assign wire_mux21_22_dataout = (syndrome[7] == 1'b1) ? (decode_output[28] ^ data_reg[22]) : data_reg[22];
assign wire_mux21_23_dataout = (syndrome[7] == 1'b1) ? (decode_output[29] ^ data_reg[23]) : data_reg[23];
assign wire_mux21_24_dataout = (syndrome[7] == 1'b1) ? (decode_output[30] ^ data_reg[24]) : data_reg[24];
assign wire_mux21_25_dataout = (syndrome[7] == 1'b1) ? (decode_output[31] ^ data_reg[25]) : data_reg[25];
assign wire_mux21_26_dataout = (syndrome[7] == 1'b1) ? (decode_output[33] ^ data_reg[26]) : data_reg[26];
assign wire_mux21_27_dataout = (syndrome[7] == 1'b1) ? (decode_output[34] ^ data_reg[27]) : data_reg[27];
assign wire_mux21_28_dataout = (syndrome[7] == 1'b1) ? (decode_output[35] ^ data_reg[28]) : data_reg[28];
assign wire_mux21_29_dataout = (syndrome[7] == 1'b1) ? (decode_output[36] ^ data_reg[29]) : data_reg[29];
assign wire_mux21_3_dataout = (syndrome[7] == 1'b1) ? (decode_output[7] ^ data_reg[3]) : data_reg[3];
assign wire_mux21_30_dataout = (syndrome[7] == 1'b1) ? (decode_output[37] ^ data_reg[30]) : data_reg[30];
assign wire_mux21_31_dataout = (syndrome[7] == 1'b1) ? (decode_output[38] ^ data_reg[31]) : data_reg[31];
assign wire_mux21_32_dataout = (syndrome[7] == 1'b1) ? (decode_output[39] ^ data_reg[32]) : data_reg[32];
assign wire_mux21_33_dataout = (syndrome[7] == 1'b1) ? (decode_output[40] ^ data_reg[33]) : data_reg[33];
assign wire_mux21_34_dataout = (syndrome[7] == 1'b1) ? (decode_output[41] ^ data_reg[34]) : data_reg[34];
assign wire_mux21_35_dataout = (syndrome[7] == 1'b1) ? (decode_output[42] ^ data_reg[35]) : data_reg[35];
assign wire_mux21_36_dataout = (syndrome[7] == 1'b1) ? (decode_output[43] ^ data_reg[36]) : data_reg[36];
assign wire_mux21_37_dataout = (syndrome[7] == 1'b1) ? (decode_output[44] ^ data_reg[37]) : data_reg[37];
assign wire_mux21_38_dataout = (syndrome[7] == 1'b1) ? (decode_output[45] ^ data_reg[38]) : data_reg[38];
assign wire_mux21_39_dataout = (syndrome[7] == 1'b1) ? (decode_output[46] ^ data_reg[39]) : data_reg[39];
assign wire_mux21_4_dataout = (syndrome[7] == 1'b1) ? (decode_output[9] ^ data_reg[4]) : data_reg[4];
assign wire_mux21_40_dataout = (syndrome[7] == 1'b1) ? (decode_output[47] ^ data_reg[40]) : data_reg[40];
assign wire_mux21_41_dataout = (syndrome[7] == 1'b1) ? (decode_output[48] ^ data_reg[41]) : data_reg[41];
assign wire_mux21_42_dataout = (syndrome[7] == 1'b1) ? (decode_output[49] ^ data_reg[42]) : data_reg[42];
assign wire_mux21_43_dataout = (syndrome[7] == 1'b1) ? (decode_output[50] ^ data_reg[43]) : data_reg[43];
assign wire_mux21_44_dataout = (syndrome[7] == 1'b1) ? (decode_output[51] ^ data_reg[44]) : data_reg[44];
assign wire_mux21_45_dataout = (syndrome[7] == 1'b1) ? (decode_output[52] ^ data_reg[45]) : data_reg[45];
assign wire_mux21_46_dataout = (syndrome[7] == 1'b1) ? (decode_output[53] ^ data_reg[46]) : data_reg[46];
assign wire_mux21_47_dataout = (syndrome[7] == 1'b1) ? (decode_output[54] ^ data_reg[47]) : data_reg[47];
assign wire_mux21_48_dataout = (syndrome[7] == 1'b1) ? (decode_output[55] ^ data_reg[48]) : data_reg[48];
assign wire_mux21_49_dataout = (syndrome[7] == 1'b1) ? (decode_output[56] ^ data_reg[49]) : data_reg[49];
assign wire_mux21_5_dataout = (syndrome[7] == 1'b1) ? (decode_output[10] ^ data_reg[5]) : data_reg[5];
assign wire_mux21_50_dataout = (syndrome[7] == 1'b1) ? (decode_output[57] ^ data_reg[50]) : data_reg[50];
assign wire_mux21_51_dataout = (syndrome[7] == 1'b1) ? (decode_output[58] ^ data_reg[51]) : data_reg[51];
assign wire_mux21_52_dataout = (syndrome[7] == 1'b1) ? (decode_output[59] ^ data_reg[52]) : data_reg[52];
assign wire_mux21_53_dataout = (syndrome[7] == 1'b1) ? (decode_output[60] ^ data_reg[53]) : data_reg[53];
assign wire_mux21_54_dataout = (syndrome[7] == 1'b1) ? (decode_output[61] ^ data_reg[54]) : data_reg[54];
assign wire_mux21_55_dataout = (syndrome[7] == 1'b1) ? (decode_output[62] ^ data_reg[55]) : data_reg[55];
assign wire_mux21_56_dataout = (syndrome[7] == 1'b1) ? (decode_output[63] ^ data_reg[56]) : data_reg[56];
assign wire_mux21_57_dataout = (syndrome[7] == 1'b1) ? (decode_output[65] ^ data_reg[57]) : data_reg[57];
assign wire_mux21_58_dataout = (syndrome[7] == 1'b1) ? (decode_output[66] ^ data_reg[58]) : data_reg[58];
assign wire_mux21_59_dataout = (syndrome[7] == 1'b1) ? (decode_output[67] ^ data_reg[59]) : data_reg[59];
assign wire_mux21_6_dataout = (syndrome[7] == 1'b1) ? (decode_output[11] ^ data_reg[6]) : data_reg[6];
assign wire_mux21_60_dataout = (syndrome[7] == 1'b1) ? (decode_output[68] ^ data_reg[60]) : data_reg[60];
assign wire_mux21_61_dataout = (syndrome[7] == 1'b1) ? (decode_output[69] ^ data_reg[61]) : data_reg[61];
assign wire_mux21_62_dataout = (syndrome[7] == 1'b1) ? (decode_output[70] ^ data_reg[62]) : data_reg[62];
assign wire_mux21_63_dataout = (syndrome[7] == 1'b1) ? (decode_output[71] ^ data_reg[63]) : data_reg[63];
assign wire_mux21_7_dataout = (syndrome[7] == 1'b1) ? (decode_output[12] ^ data_reg[7]) : data_reg[7];
assign wire_mux21_8_dataout = (syndrome[7] == 1'b1) ? (decode_output[13] ^ data_reg[8]) : data_reg[8];
assign wire_mux21_9_dataout = (syndrome[7] == 1'b1) ? (decode_output[14] ^ data_reg[9]) : data_reg[9];
assign
data_bit = data_t[63],
data_t = {(data_t[62] | decode_output[71]), (data_t[61] | decode_output[70]), (data_t[60] | decode_output[69]), (data_t[59] | decode_output[68]), (data_t[58] | decode_output[67]), (data_t[57] | decode_output[66]), (data_t[56] | decode_output[65]), (data_t[55] | decode_output[63]), (data_t[54] | decode_output[62]), (data_t[53] | decode_output[61]), (data_t[52] | decode_output[60]), (data_t[51] | decode_output[59]), (data_t[50] | decode_output[58]), (data_t[49] | decode_output[57]), (data_t[48] | decode_output[56]), (data_t[47] | decode_output[55]), (data_t[46] | decode_output[54]), (data_t[45] | decode_output[53]), (data_t[44] | decode_output[52]), (data_t[43] | decode_output[51]), (data_t[42] | decode_output[50]), (data_t[41] | decode_output[49]), (data_t[40] | decode_output[48]), (data_t[39] | decode_output[47]), (data_t[38] | decode_output[46]), (data_t[37] | decode_output[45]), (data_t[36] | decode_output[44]), (data_t[35] | decode_output[43]), (data_t[34] | decode_output[42]), (data_t[33] | decode_output[41]), (data_t[32] | decode_output[40]), (data_t[31] | decode_output[39]), (data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2]
| decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
data_wire = data,
decode_output = wire_error_bit_decoder_eq,
err_corrected = err_corrected_wire,
err_corrected_wire = ((syn_bit & syn_e) & data_bit),
err_detected = err_detected_wire,
err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
err_fatal = err_fatal_wire,
err_sbe = syn_e,
err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
parity_01_wire = {(data_wire[63] ^ parity_01_wire[34]), (data_wire[61] ^ parity_01_wire[33]), (data_wire[59] ^ parity_01_wire[32]), (data_wire[57] ^ parity_01_wire[31]), (data_wire[56] ^ parity_01_wire[30]), (data_wire[54] ^ parity_01_wire[29]), (data_wire[52] ^ parity_01_wire[28]), (data_wire[50] ^ parity_01_wire[27]), (data_wire[48] ^ parity_01_wire[26]), (data_wire[46] ^ parity_01_wire[25]), (data_wire[44] ^ parity_01_wire[24]), (data_wire[42] ^ parity_01_wire[23]), (data_wire[40] ^ parity_01_wire[22]), (data_wire[38] ^ parity_01_wire[21]), (data_wire[36] ^ parity_01_wire[20]), (data_wire[34] ^ parity_01_wire[19]), (data_wire[32] ^ parity_01_wire[18]), (data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[64]},
parity_02_wire = {((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]), ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]), ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]), ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]), ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]), ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]), ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]), ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]), ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[65] ^ data_wire[0])},
parity_03_wire = {((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]), ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]), ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]), ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]), ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[66] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]), ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]), ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[67] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]), (((((((((((((((data_wire[68] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[56] ^ parity_06_wire[29]), (data_wire[55] ^ parity_06_wire[28]), (data_wire[54] ^ parity_06_wire[27]), (data_wire[53] ^ parity_06_wire[26]), (data_wire[52] ^ parity_06_wire[25]), (data_wire[51] ^ parity_06_wire[24]), (data_wire[50] ^ parity_06_wire[23]), (data_wire[49] ^ parity_06_wire[22]), (data_wire[48] ^ parity_06_wire[21]), (data_wire[47] ^ parity_06_wire[20]), (data_wire[46] ^ parity_06_wire[19]), (data_wire[45] ^ parity_06_wire[18]), (data_wire[44] ^ parity_06_wire[17]), (data_wire[43] ^ parity_06_wire[16]), (data_wire[42] ^ parity_06_wire[15]), (data_wire[41] ^ parity_06_wire[14]), (data_wire[40] ^ parity_06_wire[13]), (data_wire[39] ^ parity_06_wire[12]), (data_wire[38] ^ parity_06_wire[11]), (data_wire[37] ^ parity_06_wire[10]), (data_wire[36] ^ parity_06_wire[9]), (data_wire[35] ^ parity_06_wire[8]), (data_wire[34] ^ parity_06_wire[7]), (data_wire[33] ^ parity_06_wire[6]), (data_wire[32] ^ parity_06_wire[5]), (data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[69] ^ data_wire[26])},
parity_07_wire = {(data_wire[63] ^ parity_07_wire[5]), (data_wire[62] ^ parity_07_wire[4]), (data_wire[61] ^ parity_07_wire[3]), (data_wire[60] ^ parity_07_wire[2]), (data_wire[59] ^ parity_07_wire[1]), (data_wire[58] ^ parity_07_wire[0]), (data_wire[70] ^ data_wire[57])},
parity_bit = parity_t[6],
parity_final_wire = {(data_wire[70] ^ parity_final_wire[69]), (data_wire[69] ^ parity_final_wire[68]), (data_wire[68] ^ parity_final_wire[67]), (data_wire[67] ^ parity_final_wire[66]), (data_wire[66] ^ parity_final_wire[65]), (data_wire[65] ^ parity_final_wire[64]), (data_wire[64] ^ parity_final_wire[63]), (data_wire[63] ^ parity_final_wire[62]), (data_wire[62] ^ parity_final_wire[61]), (data_wire[61] ^ parity_final_wire[60]), (data_wire[60] ^ parity_final_wire[59]), (data_wire[59] ^ parity_final_wire[58]), (data_wire[58] ^ parity_final_wire[57]), (data_wire[57] ^ parity_final_wire[56]), (data_wire[56] ^ parity_final_wire[55]), (data_wire[55] ^ parity_final_wire[54]), (data_wire[54] ^ parity_final_wire[53]), (data_wire[53] ^ parity_final_wire[52]), (data_wire[52] ^ parity_final_wire[51]), (data_wire[51] ^ parity_final_wire[50]), (data_wire[50] ^ parity_final_wire[49]), (data_wire[49] ^ parity_final_wire[48]), (data_wire[48] ^ parity_final_wire[47]), (data_wire[47] ^ parity_final_wire[46]), (data_wire[46] ^ parity_final_wire[45]), (data_wire[45] ^ parity_final_wire[44]), (data_wire[44] ^ parity_final_wire[43]), (data_wire[43] ^ parity_final_wire[42]), (data_wire[42] ^ parity_final_wire[41]), (data_wire[41] ^ parity_final_wire[40]), (data_wire[40] ^ parity_final_wire[39]), (data_wire[39] ^ parity_final_wire[38]), (data_wire[38] ^ parity_final_wire[37]), (data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^
parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[71] ^ data_wire[0])},
parity_t = {(parity_t[5] | decode_output[64]), (parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
q = q_wire,
q_wire = {wire_mux21_63_dataout, wire_mux21_62_dataout, wire_mux21_61_dataout, wire_mux21_60_dataout, wire_mux21_59_dataout, wire_mux21_58_dataout, wire_mux21_57_dataout, wire_mux21_56_dataout, wire_mux21_55_dataout, wire_mux21_54_dataout, wire_mux21_53_dataout, wire_mux21_52_dataout, wire_mux21_51_dataout, wire_mux21_50_dataout, wire_mux21_49_dataout, wire_mux21_48_dataout, wire_mux21_47_dataout, wire_mux21_46_dataout, wire_mux21_45_dataout, wire_mux21_44_dataout, wire_mux21_43_dataout, wire_mux21_42_dataout, wire_mux21_41_dataout, wire_mux21_40_dataout, wire_mux21_39_dataout, wire_mux21_38_dataout, wire_mux21_37_dataout, wire_mux21_36_dataout, wire_mux21_35_dataout, wire_mux21_34_dataout, wire_mux21_33_dataout, wire_mux21_32_dataout, wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
syn_bit = syn_t[5],
syn_e = syndrome[7],
syn_t = {(syn_t[4] | syndrome[6]), (syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
syndrome_wire = {parity_final_wire[70], parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[35]};
endmodule //alt_mem_ddrx_ecc_decoder_64_altecc_decoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64
#(
parameter
CFG_ECC_DECODER_REG = 1
)
(
clk,
reset_n,
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire4;
wire [63:0] sub_wire3;
wire err_detected = sub_wire0;
wire err_fatal = sub_wire1;
wire err_corrected = sub_wire2;
wire err_sbe = sub_wire4;
wire [63:0] q = sub_wire3[63:0];
alt_mem_ddrx_ecc_decoder_64_altecc_decoder
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
alt_mem_ddrx_ecc_decoder_64_altecc_decoder_component (
.clk (clk),
.reset_n (reset_n),
.data (data),
.err_detected (sub_wire0),
.err_fatal (sub_wire1),
.err_corrected (sub_wire2),
.err_sbe (sub_wire4),
.q (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_syn.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_syn.v TRUE
// Retrieval info: LIB_FILE: lpm

295
FPGA_firmware/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v
View File

@ -1,295 +0,0 @@
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ecc_encoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_ENC_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_ecc_code,
input_ecc_code_overwrite,
output_data
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code;
input input_ecc_code_overwrite;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_input_data;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_input_ecc_code;
reg int_input_ecc_code_overwrite;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output_modified;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_input;
wire [CFG_DATA_WIDTH - 1 : 0] encoder_output;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : encoder_input_per_data_width
always @ (*)
begin
int_encoder_input [i_data] = input_data [i_data];
end
end
endgenerate
// Encoder input assignment
assign encoder_input = int_encoder_input [CFG_ECC_DATA_WIDTH - 1 : 0];
// Output data merging logic
// change
// <ECC code> - <Empty data> - <Data>
// into
// <Empty data> - <ECC code> - <Data>
always @ (*)
begin
int_encoder_output = encoder_output;
end
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
// Write data only
int_encoder_output_modified = int_encoder_output;
end
end
else
begin
always @ (*)
begin
// Write data
int_encoder_output_modified [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// Ecc code
if (int_input_ecc_code_overwrite)
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_input_ecc_code;
end
else
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
end
end
end
endgenerate
// Encoder output assignment
always @ (*)
begin
if (cfg_enable_ecc)
output_data = int_encoder_output_modified;
else
output_data = int_input_data;
end
generate
if (CFG_ECC_ENC_REG)
begin
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_input_data <= 0;
int_input_ecc_code <= 0;
int_input_ecc_code_overwrite <= 0;
end
else
begin
int_input_data <= input_data;
int_input_ecc_code <= input_ecc_code;
int_input_ecc_code_overwrite <= input_ecc_code_overwrite;
end
end
end
else
begin
// Non-registered version
always @ (*)
begin
int_input_data = input_data;
int_input_ecc_code = input_ecc_code;
int_input_ecc_code_overwrite = input_ecc_code_overwrite;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] internal_encoder_output;
// Assign bit 39 to '0'
assign internal_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = internal_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = internal_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({24'd0, encoder_input} ),
.q (internal_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] internal_encoder_output;
// Assign bit 39 to '0'
assign internal_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = internal_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = internal_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({16'd0, encoder_input} ),
.q (internal_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// Assign bit 39 to '0'
assign encoder_output [39] = 1'b0;
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 64/72 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_64 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output )
);
end
else
begin
assign encoder_output = {CFG_DATA_WIDTH{1'b0}};
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule

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