113 lines
3.5 KiB
Tcl
113 lines
3.5 KiB
Tcl
## Generated SDC file "sum_peak.out.sdc"
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## Copyright (C) 2019 Intel Corporation. All rights reserved.
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## Your use of Intel Corporation's design tools, logic functions
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## and other software and tools, and any partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Intel Program License
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## Subscription Agreement, the Intel Quartus Prime License Agreement,
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## the Intel FPGA IP License Agreement, or other applicable license
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## agreement, including, without limitation, that your use is for
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## the sole purpose of programming logic devices manufactured by
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## Intel and sold by Intel or its authorized distributors. Please
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## refer to the applicable agreement for further details, at
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## https://fpgasoftware.intel.com/eula.
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## VENDOR "Altera"
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## PROGRAM "Quartus Prime"
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## VERSION "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition"
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## DATE "Mon Jul 31 13:54:17 2023"
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##
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## DEVICE "10M50DAF484C6GES"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {clk_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk_clk}]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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set_clock_uncertainty -rise_from [get_clocks {clk_clk}] -rise_to [get_clocks {clk_clk}] 0.020
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set_clock_uncertainty -rise_from [get_clocks {clk_clk}] -fall_to [get_clocks {clk_clk}] 0.020
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set_clock_uncertainty -fall_from [get_clocks {clk_clk}] -rise_to [get_clocks {clk_clk}] 0.020
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set_clock_uncertainty -fall_from [get_clocks {clk_clk}] -fall_to [get_clocks {clk_clk}] 0.020
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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