115 lines
4.0 KiB
Verilog
115 lines
4.0 KiB
Verilog
//altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="MAX 10" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
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//VERSION_BEGIN 19.1 cbx_altclkbuf 2019:09:22:08:02:34:SJ cbx_cycloneii 2019:09:22:08:02:34:SJ cbx_lpm_add_sub 2019:09:22:08:02:34:SJ cbx_lpm_compare 2019:09:22:08:02:34:SJ cbx_lpm_decode 2019:09:22:08:02:34:SJ cbx_lpm_mux 2019:09:22:08:02:34:SJ cbx_mgl 2019:09:22:09:26:20:SJ cbx_nadder 2019:09:22:08:02:34:SJ cbx_stratix 2019:09:22:08:02:34:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_stratixiii 2019:09:22:08:02:34:SJ cbx_stratixv 2019:09:22:08:02:34:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// Copyright (C) 2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details, at
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// https://fpgasoftware.intel.com/eula.
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//synthesis_resources = clkctrl 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module clkctrl_altclkctrl_0_sub
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(
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ena,
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inclk,
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outclk) /* synthesis synthesis_clearbox=1 */;
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input ena;
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input [3:0] inclk;
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output outclk;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 ena;
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tri0 [3:0] inclk;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire wire_clkctrl1_outclk;
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wire [1:0] clkselect;
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wire [1:0] clkselect_wire;
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wire [3:0] inclk_wire;
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fiftyfivenm_clkctrl clkctrl1
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(
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.clkselect(clkselect_wire),
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.ena(ena),
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.inclk(inclk_wire),
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.outclk(wire_clkctrl1_outclk)
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// synopsys translate_off
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,
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.devclrn(1'b1),
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.devpor(1'b1)
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// synopsys translate_on
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);
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defparam
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clkctrl1.clock_type = "Global Clock",
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clkctrl1.ena_register_mode = "falling edge",
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clkctrl1.lpm_type = "fiftyfivenm_clkctrl";
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assign
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clkselect = {2{1'b0}},
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clkselect_wire = {clkselect},
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inclk_wire = {inclk},
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outclk = wire_clkctrl1_outclk;
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endmodule //clkctrl_altclkctrl_0_sub
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//VALID FILE // (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module clkctrl_altclkctrl_0 (
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inclk,
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outclk);
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input inclk;
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output outclk;
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wire sub_wire0;
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wire outclk;
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wire sub_wire1;
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wire sub_wire2;
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wire [3:0] sub_wire3;
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wire [2:0] sub_wire4;
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assign outclk = sub_wire0;
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assign sub_wire1 = 1'h1;
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assign sub_wire2 = inclk;
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assign sub_wire3[3:0] = {sub_wire4, sub_wire2};
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assign sub_wire4[2:0] = 3'h0;
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clkctrl_altclkctrl_0_sub clkctrl_altclkctrl_0_sub_component (
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.ena (sub_wire1),
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.inclk (sub_wire3),
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.outclk (sub_wire0));
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endmodule |