769 lines
39 KiB
XML
769 lines
39 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
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<name>q_sys</name>
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<peripherals>
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<peripheral>
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<name>q_sys_sysid_control_slave_altera_avalon_sysid</name><baseAddress>0x00000000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>8</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>ID</name>
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<displayName>System ID</displayName>
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<description>A unique 32-bit value that is based on the contents of the QSys system. The id is similar to a check-sum value; QSys systems with different components, different configuration options, or both, produce different id values.</description>
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<addressOffset>0x0</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>${sysid_id_value}</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field><name>id</name>
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<bitOffset>0x0</bitOffset>
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<bitWidth>32</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>TIMESTAMP</name>
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<displayName>Time stamp</displayName>
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<description>A unique 32-bit value that is based on the system generation time. The value is equivalent to the number of seconds after Jan. 1, 1970.</description>
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<addressOffset>0x4</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>${sysid_timestamp_value}</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field><name>timestamp</name>
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<bitOffset>0x0</bitOffset>
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<bitWidth>32</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>q_sys_sys_clk_timer_s1_altera_avalon_timer</name><baseAddress>0x00000000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>16</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>status</name>
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<displayName>Status</displayName>
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<description>The status register has two defined bits. TO (timeout), RUN</description>
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<addressOffset>0x0</addressOffset>
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<size>16</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<resetMask>0xffff</resetMask>
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<fields>
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<field><name>TO</name>
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<description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description>
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<bitOffset>0x0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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<readAction>clear</readAction>
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</field>
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<field><name>RUN</name>
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<description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by
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a write operation to the status register.</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>Reserved</name>
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<description>Reserved</description>
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<bitOffset>2</bitOffset>
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<bitWidth>14</bitWidth>
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<access>read-write</access>
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<parameters>
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<parameter>
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<name>Reserved</name>
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<value>true</value>
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</parameter>
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</parameters>
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</field>
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</fields>
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</register>
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<register>
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<name>control</name>
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<description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description>
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<addressOffset>0x1</addressOffset>
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<size>16</size>
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<access>read-write</access>
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<reset>
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<value>0x0</value>
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</reset>
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<field>
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<name>ITO</name>
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<description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>CONT</name>
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<description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>START</name>
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<description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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<field>
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<name>STOP</name>
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<description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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<field>
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<name>Reserved</name>
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<description>Reserved</description>
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<bitOffset>4</bitOffset>
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<bitWidth>12</bitWidth>
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<access>read-write</access>
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<parameters>
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<parameter>
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<name>Reserved</name>
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<value>true</value>
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</parameter>
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</parameters>
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</field>
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</register>
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<register>
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<name>${period_name_0}</name>
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<description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description>
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<addressOffset>0x2</addressOffset>
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<size>16</size>
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<access>read-write</access>
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<resetValue>${period_name_0_reset_value}</resetValue>
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<resetMask>0xffff</resetMask>
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</register>
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<register>
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<name>${period_name_1}</name>
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<description></description>
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<addressOffset>0x3</addressOffset>
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<size>16</size>
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<access>read-write</access>
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<resetValue>${period_name_1_reset_value}</resetValue>
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<resetMask>0xffff</resetMask>
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</register>
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<register>
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<name>${period_snap_0}</name>
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<description></description>
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<addressOffset>0x4</addressOffset>
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<size>16</size>
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<access>read-write</access>
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<resetValue>${period_snap_0_reset_value}</resetValue>
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<resetMask>0xffff</resetMask>
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</register>
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<register>
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<name>${period_snap_1}</name>
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<description></description>
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<addressOffset>0x5</addressOffset>
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<size>16</size>
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<access>read-write</access>
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<resetValue>${period_snap_1_reset_value}</resetValue>
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<resetMask>0xffff</resetMask>
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</register>
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<register>
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<name>${snap_0}</name>
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<description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description>
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<addressOffset>0x6</addressOffset>
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<size>16</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<resetMask>0xffff</resetMask>
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</register>
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<register>
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<name>${snap_1}</name>
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<description></description>
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<addressOffset>0x7</addressOffset>
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<size>16</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<resetMask>0xffff</resetMask>
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</register>
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<register>
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<name>${snap_2}</name>
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<description></description>
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<addressOffset>0x8</addressOffset>
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<size>16</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<resetMask>0xffff</resetMask>
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</register>
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<register>
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<name>${snap_3}</name>
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<description></description>
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<addressOffset>0x9</addressOffset>
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<size>16</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<resetMask>0xffff</resetMask>
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>q_sys_output_pio_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>32</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>DATA</name>
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<displayName>Data</displayName>
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<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
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<addressOffset>0x0</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field><name>data</name>
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<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
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<bitOffset>0x0</bitOffset>
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<bitWidth>32</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>DIRECTION</name>
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<displayName>Direction</displayName>
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<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
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<addressOffset>0x4</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field><name>direction</name>
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<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
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<bitOffset>0x0</bitOffset>
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<bitWidth>32</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>IRQ_MASK</name>
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<displayName>Interrupt mask</displayName>
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<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
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<addressOffset>0x8</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field><name>interruptmask</name>
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<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
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<bitOffset>0x0</bitOffset>
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<bitWidth>32</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>EDGE_CAP</name>
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<displayName>Edge capture</displayName>
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<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
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<addressOffset>0xc</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field><name>edgecapture</name>
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<description>Edge detection for each input port.</description>
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<bitOffset>0x0</bitOffset>
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<bitWidth>32</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>SET_BIT</name>
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<displayName>Outset</displayName>
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<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
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<addressOffset>0x10</addressOffset>
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<size>32</size>
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<access>write-only</access>
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<resetValue>0x0</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field><name>outset</name>
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<description>Specifies which bit of the output port to set.</description>
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<bitOffset>0x0</bitOffset>
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<bitWidth>32</bitWidth>
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<access>write-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>CLEAR_BITS</name>
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<displayName>Outclear</displayName>
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<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
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<addressOffset>0x14</addressOffset>
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<size>32</size>
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<access>write-only</access>
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<resetValue>0x0</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field><name>outclear</name>
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<description>Specifies which output bit to clear.</description>
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<bitOffset>0x0</bitOffset>
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<bitWidth>32</bitWidth>
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<access>write-only</access>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>q_sys_frame_timer_s1_altera_avalon_timer</name><baseAddress>0x00000000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>16</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>status</name>
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<displayName>Status</displayName>
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<description>The status register has two defined bits. TO (timeout), RUN</description>
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<addressOffset>0x0</addressOffset>
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<size>16</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
|
|
<resetMask>0xffff</resetMask>
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|
<fields>
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<field><name>TO</name>
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<description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description>
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<bitOffset>0x0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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<readAction>clear</readAction>
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</field>
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<field><name>RUN</name>
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<description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by
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a write operation to the status register.</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
|
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<name>Reserved</name>
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<description>Reserved</description>
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<bitOffset>2</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
<parameters>
|
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<parameter>
|
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<name>Reserved</name>
|
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<value>true</value>
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</parameter>
|
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</parameters>
|
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</field>
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</fields>
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</register>
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<register>
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<name>control</name>
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<description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description>
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<addressOffset>0x1</addressOffset>
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<size>16</size>
|
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<access>read-write</access>
|
|
<reset>
|
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<value>0x0</value>
|
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</reset>
|
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<field>
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<name>ITO</name>
|
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<description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
|
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</field>
|
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<field>
|
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<name>CONT</name>
|
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<description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
|
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</field>
|
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<field>
|
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<name>START</name>
|
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<description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description>
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<bitOffset>2</bitOffset>
|
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<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>Reserved</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
<parameters>
|
|
<parameter>
|
|
<name>Reserved</name>
|
|
<value>true</value>
|
|
</parameter>
|
|
</parameters>
|
|
</field>
|
|
</register>
|
|
<register>
|
|
<name>${period_name_0}</name>
|
|
<description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>${period_name_0_reset_value}</resetValue>
|
|
<resetMask>0xffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>${period_name_1}</name>
|
|
<description></description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>${period_name_1_reset_value}</resetValue>
|
|
<resetMask>0xffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>${period_snap_0}</name>
|
|
<description></description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>${period_snap_0_reset_value}</resetValue>
|
|
<resetMask>0xffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>${period_snap_1}</name>
|
|
<description></description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>${period_snap_1_reset_value}</resetValue>
|
|
<resetMask>0xffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>${snap_0}</name>
|
|
<description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>${snap_1}</name>
|
|
<description></description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>${snap_2}</name>
|
|
<description></description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffff</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>${snap_3}</name>
|
|
<description></description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffff</resetMask>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<baseAddress>0x00000000</baseAddress>
|
|
<name>q_sys_ext_flash_avl_csr_altera_generic_quad_spi_controller</name>
|
|
<description>altera_generic_quad_spi_controller</description>
|
|
<registers>
|
|
<register>
|
|
<access>read-only</access>
|
|
<addressOffset>0x0</addressOffset>
|
|
<displayName>flash_rd_status</displayName>
|
|
<description>Perform read operation on flash device status register and store the read back data. </description>
|
|
<name>flash_rd_status</name>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<resetValue>0x00000000</resetValue>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<access>read-only</access>
|
|
<addressOffset>0x4</addressOffset>
|
|
<displayName>flash_rd_sid</displayName>
|
|
<description>Perform read operation to extract flash device silicon ID and store the read back data. Only support in EPCS16 and EPCS64 flash devices. </description>
|
|
<name>flash_rd_sid</name>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<resetValue>0x00000000</resetValue>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<access>read-only</access>
|
|
<addressOffset>0x8</addressOffset>
|
|
<displayName>flash_rd_rdid</displayName>
|
|
<description>Perform read operation to extract flash device memory capacity and store the read back data. </description>
|
|
<name>flash_rd_rdid</name>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<resetValue>0x00000000</resetValue>
|
|
<size>32</size>
|
|
</register>
|
|
<register>
|
|
<access>write-only</access>
|
|
<addressOffset>0xc</addressOffset>
|
|
<displayName>flash_mem_op</displayName>
|
|
<description>To protect and erase memory </description>
|
|
<name>flash_mem_op</name>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<resetValue>0x00000000</resetValue>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<access>write-only</access>
|
|
<bitRange>[1:0]</bitRange>
|
|
<modifiedWriteValues>modify</modifiedWriteValues>
|
|
<name>memory_operation</name>
|
|
</field>
|
|
<field>
|
|
<access>write-only</access>
|
|
<bitRange>[23:8]</bitRange>
|
|
<modifiedWriteValues>modify</modifiedWriteValues>
|
|
<name>sector_value</name>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<access>read-write</access>
|
|
<addressOffset>0x10</addressOffset>
|
|
<displayName>flash_isr</displayName>
|
|
<description>Interrupt status register </description>
|
|
<name>flash_isr</name>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<resetValue>0x00000000</resetValue>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<access>read-write</access>
|
|
<bitRange>[0:0]</bitRange>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<name>illegal_erase</name>
|
|
</field>
|
|
<field>
|
|
<access>read-write</access>
|
|
<bitRange>[1:1]</bitRange>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<name>illegal_write</name>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<access>read-write</access>
|
|
<addressOffset>0x14</addressOffset>
|
|
<displayName>flash_imr</displayName>
|
|
<description>To mask of interrupt status register </description>
|
|
<name>flash_imr</name>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<resetValue>0x00000000</resetValue>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<access>read-write</access>
|
|
<bitRange>[0:0]</bitRange>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<name>m_illegal_erase</name>
|
|
</field>
|
|
<field>
|
|
<access>read-write</access>
|
|
<bitRange>[1:1]</bitRange>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<name>m_illegal_write</name>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<access>write-only</access>
|
|
<addressOffset>0x18</addressOffset>
|
|
<displayName>flash_chip_select</displayName>
|
|
<description>Chip select values </description>
|
|
<name>flash_chip_select</name>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<resetValue>0x00000000</resetValue>
|
|
<size>32</size>
|
|
<fields>
|
|
<field>
|
|
<access>write-only</access>
|
|
<bitRange>[0:0]</bitRange>
|
|
<modifiedWriteValues>modify</modifiedWriteValues>
|
|
<name>chip_select_bit_1</name>
|
|
</field>
|
|
<field>
|
|
<access>write-only</access>
|
|
<bitRange>[1:1]</bitRange>
|
|
<modifiedWriteValues>modify</modifiedWriteValues>
|
|
<name>chip_select_bit_2</name>
|
|
</field>
|
|
<field>
|
|
<access>write-only</access>
|
|
<bitRange>[2:2]</bitRange>
|
|
<modifiedWriteValues>modify</modifiedWriteValues>
|
|
<name>chip_select_bit_3</name>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>q_sys_button_pio_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>32</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>Data</displayName>
|
|
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>data</name>
|
|
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRECTION</name>
|
|
<displayName>Direction</displayName>
|
|
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>direction</name>
|
|
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ_MASK</name>
|
|
<displayName>Interrupt mask</displayName>
|
|
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>interruptmask</name>
|
|
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EDGE_CAP</name>
|
|
<displayName>Edge capture</displayName>
|
|
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
|
<addressOffset>0xc</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>edgecapture</name>
|
|
<description>Edge detection for each input port.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_BIT</name>
|
|
<displayName>Outset</displayName>
|
|
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>outset</name>
|
|
<description>Specifies which bit of the output port to set.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLEAR_BITS</name>
|
|
<displayName>Outclear</displayName>
|
|
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field><name>outclear</name>
|
|
<description>Specifies which output bit to clear.</description>
|
|
<bitOffset>0x0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device> |