q_sys q_sys_sysid_control_slave_altera_avalon_sysid0x00000000 0x0 8 registers ID System ID A unique 32-bit value that is based on the contents of the QSys system. The id is similar to a check-sum value; QSys systems with different components, different configuration options, or both, produce different id values. 0x0 32 read-only ${sysid_id_value} 0xffffffff id 0x0 32 read-only TIMESTAMP Time stamp A unique 32-bit value that is based on the system generation time. The value is equivalent to the number of seconds after Jan. 1, 1970. 0x4 32 read-only ${sysid_timestamp_value} 0xffffffff timestamp 0x0 32 read-only q_sys_sys_clk_timer_s1_altera_avalon_timer0x00000000 0x0 16 registers status Status The status register has two defined bits. TO (timeout), RUN 0x0 16 read-write 0x0 0xffff TO The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit. 0x0 1 read-only clear RUN The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by a write operation to the status register. 1 1 read-only Reserved Reserved 2 14 read-write Reserved true control The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP 0x1 16 read-write 0x0 ITO If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs. 0 1 read-write CONT The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit. 1 1 read-write START Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect. 2 1 write-only STOP Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect. 3 1 write-only Reserved Reserved 4 12 read-write Reserved true ${period_name_0} The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time. 0x2 16 read-write ${period_name_0_reset_value} 0xffff ${period_name_1} 0x3 16 read-write ${period_name_1_reset_value} 0xffff ${period_snap_0} 0x4 16 read-write ${period_snap_0_reset_value} 0xffff ${period_snap_1} 0x5 16 read-write ${period_snap_1_reset_value} 0xffff ${snap_0} A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation. 0x6 16 read-write 0x0 0xffff ${snap_1} 0x7 16 read-write 0x0 0xffff ${snap_2} 0x8 16 read-write 0x0 0xffff ${snap_3} 0x9 16 read-write 0x0 0xffff q_sys_output_pio_s1_altera_avalon_pio0x00000000 0x0 32 registers DATA Data Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output). 0x0 32 read-write 0x0 0xffffffff data Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs. 0x0 32 read-write DIRECTION Direction The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register. 0x4 32 read-write 0x0 0xffffffff direction Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output. 0x0 32 read-write IRQ_MASK Interrupt mask Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports. 0x8 32 read-write 0x0 0xffffffff interruptmask IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port. 0x0 32 read-write EDGE_CAP Edge capture Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect. 0xc 32 read-write 0x0 0xffffffff edgecapture Edge detection for each input port. 0x0 32 read-write SET_BIT Outset You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on. 0x10 32 write-only 0x0 0xffffffff outset Specifies which bit of the output port to set. 0x0 32 write-only CLEAR_BITS Outclear You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on. 0x14 32 write-only 0x0 0xffffffff outclear Specifies which output bit to clear. 0x0 32 write-only q_sys_frame_timer_s1_altera_avalon_timer0x00000000 0x0 16 registers status Status The status register has two defined bits. TO (timeout), RUN 0x0 16 read-write 0x0 0xffff TO The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit. 0x0 1 read-only clear RUN The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by a write operation to the status register. 1 1 read-only Reserved Reserved 2 14 read-write Reserved true control The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP 0x1 16 read-write 0x0 ITO If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs. 0 1 read-write CONT The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit. 1 1 read-write START Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect. 2 1 write-only STOP Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect. 3 1 write-only Reserved Reserved 4 12 read-write Reserved true ${period_name_0} The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time. 0x2 16 read-write ${period_name_0_reset_value} 0xffff ${period_name_1} 0x3 16 read-write ${period_name_1_reset_value} 0xffff ${period_snap_0} 0x4 16 read-write ${period_snap_0_reset_value} 0xffff ${period_snap_1} 0x5 16 read-write ${period_snap_1_reset_value} 0xffff ${snap_0} A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation. 0x6 16 read-write 0x0 0xffff ${snap_1} 0x7 16 read-write 0x0 0xffff ${snap_2} 0x8 16 read-write 0x0 0xffff ${snap_3} 0x9 16 read-write 0x0 0xffff 0x00000000 q_sys_ext_flash_avl_csr_altera_generic_quad_spi_controller altera_generic_quad_spi_controller read-only 0x0 flash_rd_status Perform read operation on flash device status register and store the read back data. flash_rd_status 0xffffffff 0x00000000 32 read-only 0x4 flash_rd_sid Perform read operation to extract flash device silicon ID and store the read back data. Only support in EPCS16 and EPCS64 flash devices. flash_rd_sid 0xffffffff 0x00000000 32 read-only 0x8 flash_rd_rdid Perform read operation to extract flash device memory capacity and store the read back data. flash_rd_rdid 0xffffffff 0x00000000 32 write-only 0xc flash_mem_op To protect and erase memory flash_mem_op 0xffffffff 0x00000000 32 write-only [1:0] modify memory_operation write-only [23:8] modify sector_value read-write 0x10 flash_isr Interrupt status register flash_isr 0xffffffff 0x00000000 32 read-write [0:0] oneToClear illegal_erase read-write [1:1] oneToClear illegal_write read-write 0x14 flash_imr To mask of interrupt status register flash_imr 0xffffffff 0x00000000 32 read-write [0:0] oneToClear m_illegal_erase read-write [1:1] oneToClear m_illegal_write write-only 0x18 flash_chip_select Chip select values flash_chip_select 0xffffffff 0x00000000 32 write-only [0:0] modify chip_select_bit_1 write-only [1:1] modify chip_select_bit_2 write-only [2:2] modify chip_select_bit_3 q_sys_button_pio_s1_altera_avalon_pio0x00000000 0x0 32 registers DATA Data Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output). 0x0 32 read-write 0x0 0xffffffff data Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs. 0x0 32 read-write DIRECTION Direction The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register. 0x4 32 read-write 0x0 0xffffffff direction Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output. 0x0 32 read-write IRQ_MASK Interrupt mask Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports. 0x8 32 read-write 0x0 0xffffffff interruptmask IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port. 0x0 32 read-write EDGE_CAP Edge capture Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect. 0xc 32 read-write 0x0 0xffffffff edgecapture Edge detection for each input port. 0x0 32 read-write SET_BIT Outset You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on. 0x10 32 write-only 0x0 0xffffffff outset Specifies which bit of the output port to set. 0x0 32 write-only CLEAR_BITS Outclear You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on. 0x14 32 write-only 0x0 0xffffffff outclear Specifies which output bit to clear. 0x0 32 write-only