132 lines
5.9 KiB
XML
132 lines
5.9 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<deploy
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date="2023.06.07.19:47:52"
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outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/">
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<perimeter>
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<parameter
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name="AUTO_GENERATION_ID"
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type="Integer"
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defaultValue="0"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_UNIQUE_ID"
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type="String"
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defaultValue=""
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_FAMILY"
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type="String"
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defaultValue="MAX 10"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE"
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type="String"
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defaultValue="10M50DAF484C6GES"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_SPEEDGRADE"
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type="String"
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defaultValue="6"
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onHdl="0"
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affectsHdl="1" />
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<interface name="altclkctrl_input" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port name="inclk" direction="input" role="inclk" width="1" />
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</interface>
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<interface name="altclkctrl_output" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port name="outclk" direction="output" role="outclk" width="1" />
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</interface>
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</perimeter>
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<entity
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path=""
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parameterizationKey="clkctrl:1.0:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1686160072,AUTO_UNIQUE_ID=(altclkctrl:19.1:CLOCK_TYPE=1,DEVICE_FAMILY=MAX 10,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false)"
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instancePathKey="clkctrl"
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kind="clkctrl"
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version="1.0"
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name="clkctrl">
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<parameter name="AUTO_GENERATION_ID" value="1686160072" />
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<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
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<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
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<parameter name="AUTO_UNIQUE_ID" value="" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
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<generatedFiles>
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/synthesis/clkctrl.v"
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type="VERILOG" />
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</generatedFiles>
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<childGeneratedFiles>
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v"
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type="VERILOG"
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attributes="" />
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</childGeneratedFiles>
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<sourceFiles>
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<file path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl.qsys" />
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</sourceFiles>
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<childSourceFiles>
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
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</childSourceFiles>
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<messages>
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<message level="Debug" culprit="clkctrl">queue size: 0 starting:clkctrl "clkctrl"</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug">Transform: CustomInstructionTransform</message>
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<message level="Debug">No custom instruction connections, skipping transform </message>
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<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
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<message level="Debug">Transform: MMTransform</message>
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<message level="Debug">Transform: InterruptMapperTransform</message>
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<message level="Debug">Transform: InterruptSyncTransform</message>
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<message level="Debug">Transform: InterruptFanoutTransform</message>
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<message level="Debug">Transform: AvalonStreamingTransform</message>
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<message level="Debug">Transform: ResetAdaptation</message>
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<message level="Debug" culprit="clkctrl"><![CDATA["<b>clkctrl</b>" reuses <b>altclkctrl</b> "<b>submodules/clkctrl_altclkctrl_0</b>"]]></message>
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<message level="Debug" culprit="clkctrl">queue size: 0 starting:altclkctrl "submodules/clkctrl_altclkctrl_0"</message>
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<message level="Info" culprit="altclkctrl_0">Generating top-level entity clkctrl_altclkctrl_0.</message>
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<message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/.</message>
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<message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkctrl</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
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</messages>
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</entity>
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<entity
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path="submodules/"
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parameterizationKey="altclkctrl:19.1:CLOCK_TYPE=1,DEVICE_FAMILY=MAX 10,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false"
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instancePathKey="clkctrl:.:altclkctrl_0"
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kind="altclkctrl"
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version="19.1"
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name="clkctrl_altclkctrl_0">
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<parameter name="NUMBER_OF_CLOCKS" value="1" />
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<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
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<parameter name="GUI_USE_ENA" value="false" />
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<parameter name="DEVICE_FAMILY" value="MAX 10" />
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<parameter name="ENA_REGISTER_MODE" value="1" />
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<parameter name="CLOCK_TYPE" value="1" />
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<generatedFiles>
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/clkctrl/synthesis/submodules/clkctrl_altclkctrl_0.v"
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type="VERILOG"
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attributes="" />
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</generatedFiles>
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<childGeneratedFiles/>
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<sourceFiles>
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
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</sourceFiles>
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<childSourceFiles/>
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<instantiator instantiator="clkctrl" as="altclkctrl_0" />
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<messages>
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<message level="Debug" culprit="clkctrl">queue size: 0 starting:altclkctrl "submodules/clkctrl_altclkctrl_0"</message>
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<message level="Info" culprit="altclkctrl_0">Generating top-level entity clkctrl_altclkctrl_0.</message>
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<message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/.</message>
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<message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkctrl</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
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</messages>
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</entity>
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</deploy>
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