41 lines
1016 B
Verilog
41 lines
1016 B
Verilog
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module cali_ram (
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cali_ram_s2_address,
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cali_ram_s2_chipselect,
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cali_ram_s2_clken,
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cali_ram_s2_write,
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cali_ram_s2_readdata,
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cali_ram_s2_writedata,
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cali_ram_s2_byteenable,
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cali_ram_clk2_clk,
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cali_ram_reset2_reset,
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cali_ram_reset1_reset,
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cali_ram_s1_address,
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cali_ram_s1_clken,
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cali_ram_s1_chipselect,
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cali_ram_s1_write,
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cali_ram_s1_readdata,
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cali_ram_s1_writedata,
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cali_ram_s1_byteenable,
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cali_ram_clk1_clk);
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input [8:0] cali_ram_s2_address;
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input cali_ram_s2_chipselect;
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input cali_ram_s2_clken;
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input cali_ram_s2_write;
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output [15:0] cali_ram_s2_readdata;
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input [15:0] cali_ram_s2_writedata;
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input [1:0] cali_ram_s2_byteenable;
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input cali_ram_clk2_clk;
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input cali_ram_reset2_reset;
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input cali_ram_reset1_reset;
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input [8:0] cali_ram_s1_address;
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input cali_ram_s1_clken;
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input cali_ram_s1_chipselect;
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input cali_ram_s1_write;
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output [15:0] cali_ram_s1_readdata;
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input [15:0] cali_ram_s1_writedata;
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input [1:0] cali_ram_s1_byteenable;
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input cali_ram_clk1_clk;
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endmodule
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