21599 lines
3.2 MiB
21599 lines
3.2 MiB
<?xml version="1.0" encoding="UTF-8"?>
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<deploy
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date="2024.10.11.10:10:44"
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outputDirectory="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/">
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<perimeter>
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<parameter
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name="AUTO_GENERATION_ID"
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type="Integer"
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defaultValue="0"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_UNIQUE_ID"
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type="String"
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defaultValue=""
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_FAMILY"
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type="String"
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defaultValue="MAX 10"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE"
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type="String"
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defaultValue="10M50DAF484C6GES"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_SPEEDGRADE"
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type="String"
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defaultValue="6"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_RATE"
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type="Long"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_CLOCK_BRIDGE_0_IN_CLK_RESET_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_RATE"
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type="Long"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DDR3_RAM_PLL_REF_CLK_RESET_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_RATE"
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type="Long"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_RESET_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_RATE"
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type="Long"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_RESET_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_SYS_CLK_CLOCK_RATE"
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type="Long"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_SYS_CLK_CLOCK_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_SYS_CLK_RESET_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<interface name="altpll_shift_c0" kind="clock" start="1">
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<property name="associatedDirectClock" value="" />
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<property name="clockRate" value="250000000" />
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<property name="clockRateKnown" value="true" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port name="altpll_shift_c0_clk" direction="output" role="clk" width="1" />
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</interface>
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<interface name="altpll_shift_locked_conduit" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port
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name="altpll_shift_locked_conduit_export"
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direction="output"
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role="export"
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width="1" />
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</interface>
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<interface name="button_pio_external_connection" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port
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name="button_pio_external_connection_export"
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direction="input"
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role="export"
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width="9" />
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</interface>
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<interface name="clock_bridge_0_in_clk" kind="clock" start="0">
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<property name="clockRate" value="0" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port
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name="clock_bridge_0_in_clk_clk"
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direction="input"
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role="clk"
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width="1" />
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</interface>
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<interface name="ddr3_ram_pll_ref_clk" kind="clock" start="0">
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<property name="clockRate" value="0" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port
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name="ddr3_ram_pll_ref_clk_clk"
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direction="input"
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role="clk"
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width="1" />
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</interface>
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<interface name="debug_uart_external_connection" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port
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name="debug_uart_external_connection_rxd"
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direction="input"
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role="rxd"
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width="1" />
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<port
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name="debug_uart_external_connection_txd"
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direction="output"
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role="txd"
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width="1" />
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</interface>
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<interface name="enet_pll_c0" kind="clock" start="1">
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<property name="associatedDirectClock" value="" />
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<property name="clockRate" value="125000000" />
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<property name="clockRateKnown" value="true" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port name="enet_pll_c0_clk" direction="output" role="clk" width="1" />
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</interface>
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<interface name="enet_pll_c1" kind="clock" start="1">
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<property name="associatedDirectClock" value="" />
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<property name="clockRate" value="25000000" />
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<property name="clockRateKnown" value="true" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port name="enet_pll_c1_clk" direction="output" role="clk" width="1" />
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</interface>
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<interface name="enet_pll_c2" kind="clock" start="1">
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<property name="associatedDirectClock" value="" />
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<property name="clockRate" value="2500000" />
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<property name="clockRateKnown" value="true" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port name="enet_pll_c2_clk" direction="output" role="clk" width="1" />
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</interface>
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<interface name="enet_pll_c3" kind="clock" start="1">
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<property name="associatedDirectClock" value="" />
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<property name="clockRate" value="125000000" />
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<property name="clockRateKnown" value="true" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port name="enet_pll_c3_clk" direction="output" role="clk" width="1" />
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</interface>
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<interface name="enet_pll_c4" kind="clock" start="1">
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<property name="associatedDirectClock" value="" />
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<property name="clockRate" value="25000000" />
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<property name="clockRateKnown" value="true" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port name="enet_pll_c4_clk" direction="output" role="clk" width="1" />
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</interface>
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<interface name="enet_pll_locked_conduit" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port
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name="enet_pll_locked_conduit_export"
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direction="output"
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role="export"
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width="1" />
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</interface>
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<interface name="eth_tse_mac_mdio_connection" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port
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name="eth_tse_mac_mdio_connection_mdc"
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direction="output"
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role="mdc"
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width="1" />
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<port
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name="eth_tse_mac_mdio_connection_mdio_in"
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direction="input"
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role="mdio_in"
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width="1" />
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<port
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name="eth_tse_mac_mdio_connection_mdio_out"
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direction="output"
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role="mdio_out"
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width="1" />
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<port
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name="eth_tse_mac_mdio_connection_mdio_oen"
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direction="output"
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role="mdio_oen"
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width="1" />
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</interface>
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<interface name="eth_tse_mac_rgmii_connection" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port
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name="eth_tse_mac_rgmii_connection_rgmii_in"
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direction="input"
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role="rgmii_in"
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width="4" />
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<port
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name="eth_tse_mac_rgmii_connection_rgmii_out"
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direction="output"
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role="rgmii_out"
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width="4" />
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<port
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name="eth_tse_mac_rgmii_connection_rx_control"
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direction="input"
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role="rx_control"
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width="1" />
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<port
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name="eth_tse_mac_rgmii_connection_tx_control"
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direction="output"
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role="tx_control"
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width="1" />
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</interface>
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<interface name="eth_tse_mac_status_connection" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port
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name="eth_tse_mac_status_connection_set_10"
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direction="input"
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role="set_10"
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width="1" />
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<port
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name="eth_tse_mac_status_connection_set_1000"
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direction="input"
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role="set_1000"
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width="1" />
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<port
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name="eth_tse_mac_status_connection_eth_mode"
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direction="output"
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role="eth_mode"
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width="1" />
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<port
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name="eth_tse_mac_status_connection_ena_10"
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direction="output"
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role="ena_10"
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width="1" />
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</interface>
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<interface name="eth_tse_pcs_mac_rx_clock_connection" kind="clock" start="0">
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<property name="clockRate" value="0" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port
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name="eth_tse_pcs_mac_rx_clock_connection_clk"
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direction="input"
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role="clk"
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width="1" />
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</interface>
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<interface name="eth_tse_pcs_mac_tx_clock_connection" kind="clock" start="0">
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<property name="clockRate" value="0" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port
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name="eth_tse_pcs_mac_tx_clock_connection_clk"
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direction="input"
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role="clk"
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width="1" />
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</interface>
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<interface name="ext_flash_flash_dataout" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port
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name="ext_flash_flash_dataout_conduit_dataout"
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direction="bidir"
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role="conduit_dataout"
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width="4" />
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</interface>
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<interface name="ext_flash_flash_dclk_out" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port
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name="ext_flash_flash_dclk_out_conduit_dclk_out"
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direction="output"
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role="conduit_dclk_out"
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width="1" />
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</interface>
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<interface name="ext_flash_flash_ncs" kind="conduit" start="0">
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|
<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port
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name="ext_flash_flash_ncs_conduit_ncs"
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direction="output"
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role="conduit_ncs"
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width="1" />
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</interface>
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<interface name="frame_timer" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port name="frame_timer_export" direction="output" role="export" width="1" />
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</interface>
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|
<interface name="led_pio_external_connection" kind="conduit" start="0">
|
|
<property name="associatedClock" value="" />
|
|
<property name="associatedReset" value="" />
|
|
<port
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name="led_pio_external_connection_export"
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direction="output"
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role="export"
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width="8" />
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</interface>
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|
<interface name="mem_if_ddr3_emif_0_status" kind="conduit" start="0">
|
|
<property name="associatedClock" value="" />
|
|
<property name="associatedReset" value="" />
|
|
<port
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name="mem_if_ddr3_emif_0_status_local_init_done"
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|
direction="output"
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|
role="local_init_done"
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|
width="1" />
|
|
<port
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name="mem_if_ddr3_emif_0_status_local_cal_success"
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|
direction="output"
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|
role="local_cal_success"
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|
width="1" />
|
|
<port
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name="mem_if_ddr3_emif_0_status_local_cal_fail"
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|
direction="output"
|
|
role="local_cal_fail"
|
|
width="1" />
|
|
</interface>
|
|
<interface name="mem_resetn_in_reset" kind="reset" start="0">
|
|
<property name="associatedClock" value="" />
|
|
<property name="synchronousEdges" value="NONE" />
|
|
<port
|
|
name="mem_resetn_in_reset_reset_n"
|
|
direction="input"
|
|
role="reset_n"
|
|
width="1" />
|
|
</interface>
|
|
<interface name="memory" kind="conduit" start="0">
|
|
<property name="associatedClock" value="" />
|
|
<property name="associatedReset" value="" />
|
|
<port name="memory_mem_a" direction="output" role="mem_a" width="14" />
|
|
<port name="memory_mem_ba" direction="output" role="mem_ba" width="3" />
|
|
<port name="memory_mem_ck" direction="bidir" role="mem_ck" width="1" />
|
|
<port name="memory_mem_ck_n" direction="bidir" role="mem_ck_n" width="1" />
|
|
<port name="memory_mem_cke" direction="output" role="mem_cke" width="1" />
|
|
<port name="memory_mem_cs_n" direction="output" role="mem_cs_n" width="1" />
|
|
<port name="memory_mem_dm" direction="output" role="mem_dm" width="1" />
|
|
<port name="memory_mem_ras_n" direction="output" role="mem_ras_n" width="1" />
|
|
<port name="memory_mem_cas_n" direction="output" role="mem_cas_n" width="1" />
|
|
<port name="memory_mem_we_n" direction="output" role="mem_we_n" width="1" />
|
|
<port
|
|
name="memory_mem_reset_n"
|
|
direction="output"
|
|
role="mem_reset_n"
|
|
width="1" />
|
|
<port name="memory_mem_dq" direction="bidir" role="mem_dq" width="8" />
|
|
<port name="memory_mem_dqs" direction="bidir" role="mem_dqs" width="1" />
|
|
<port name="memory_mem_dqs_n" direction="bidir" role="mem_dqs_n" width="1" />
|
|
<port name="memory_mem_odt" direction="output" role="mem_odt" width="1" />
|
|
</interface>
|
|
<interface name="reset" kind="reset" start="0">
|
|
<property name="associatedClock" value="" />
|
|
<property name="synchronousEdges" value="NONE" />
|
|
<port name="reset_reset_n" direction="input" role="reset_n" width="1" />
|
|
</interface>
|
|
<interface name="sensor" kind="conduit" start="0">
|
|
<property name="associatedClock" value="sys_clk" />
|
|
<property name="associatedReset" value="" />
|
|
<port
|
|
name="sensor_in_adc_data"
|
|
direction="input"
|
|
role="in_adc_data"
|
|
width="5" />
|
|
<port name="sensor_in_trg" direction="input" role="in_trg" width="1" />
|
|
<port
|
|
name="sensor_out_adc_clk"
|
|
direction="output"
|
|
role="out_adc_clk"
|
|
width="1" />
|
|
<port
|
|
name="sensor_out_adc_cnv"
|
|
direction="output"
|
|
role="out_adc_cnv"
|
|
width="1" />
|
|
<port
|
|
name="sensor_out_sensor_clk"
|
|
direction="output"
|
|
role="out_sensor_clk"
|
|
width="1" />
|
|
<port
|
|
name="sensor_out_sensor_gain"
|
|
direction="output"
|
|
role="out_sensor_gain"
|
|
width="1" />
|
|
<port
|
|
name="sensor_out_sensor_rst"
|
|
direction="output"
|
|
role="out_sensor_rst"
|
|
width="1" />
|
|
</interface>
|
|
<interface name="sensor_status" kind="conduit" start="0">
|
|
<property name="associatedClock" value="sys_clk" />
|
|
<property name="associatedReset" value="" />
|
|
<port
|
|
name="sensor_status_status_out"
|
|
direction="output"
|
|
role="status_out"
|
|
width="8" />
|
|
</interface>
|
|
<interface name="sensor_synchro" kind="conduit" start="0">
|
|
<property name="associatedClock" value="sys_clk" />
|
|
<property name="associatedReset" value="" />
|
|
<port
|
|
name="sensor_synchro_ext_input"
|
|
direction="input"
|
|
role="ext_input"
|
|
width="8" />
|
|
<port
|
|
name="sensor_synchro_serial_rx"
|
|
direction="input"
|
|
role="serial_rx"
|
|
width="1" />
|
|
<port
|
|
name="sensor_synchro_serial_tx"
|
|
direction="output"
|
|
role="serial_tx"
|
|
width="1" />
|
|
</interface>
|
|
<interface name="sys_clk" kind="clock" start="0">
|
|
<property name="clockRate" value="50000000" />
|
|
<property name="externallyDriven" value="false" />
|
|
<property name="ptfSchematicName" value="" />
|
|
<port name="sys_clk_clk" direction="input" role="clk" width="1" />
|
|
</interface>
|
|
</perimeter>
|
|
<entity
|
|
path=""
|
|
parameterizationKey="q_sys:1.0:AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_DOMAIN=-1,AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_RATE=-1,AUTO_CLOCK_BRIDGE_0_IN_CLK_RESET_DOMAIN=-1,AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_DOMAIN=-1,AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_RATE=-1,AUTO_DDR3_RAM_PLL_REF_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_DOMAIN=-1,AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_RATE=-1,AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_RESET_DOMAIN=-1,AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_DOMAIN=-1,AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_RATE=-1,AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_RESET_DOMAIN=-1,AUTO_GENERATION_ID=1728634208,AUTO_SYS_CLK_CLOCK_DOMAIN=-1,AUTO_SYS_CLK_CLOCK_RATE=-1,AUTO_SYS_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(altpll:19.1:AUTO_DEVICE_FAMILY=MAX 10,AUTO_INCLK_INTERFACE_CLOCK_RATE=50000000,AVALON_USE_SEPARATE_SYSCLK=NO,BANDWIDTH=,BANDWIDTH_TYPE=AUTO,CLK0_DIVIDE_BY=1,CLK0_DUTY_CYCLE=50,CLK0_MULTIPLY_BY=5,CLK0_PHASE_SHIFT=0,CLK1_DIVIDE_BY=2,CLK1_DUTY_CYCLE=50,CLK1_MULTIPLY_BY=1,CLK1_PHASE_SHIFT=15000,CLK2_DIVIDE_BY=20,CLK2_DUTY_CYCLE=50,CLK2_MULTIPLY_BY=1,CLK2_PHASE_SHIFT=0,CLK3_DIVIDE_BY=,CLK3_DUTY_CYCLE=,CLK3_MULTIPLY_BY=,CLK3_PHASE_SHIFT=,CLK4_DIVIDE_BY=,CLK4_DUTY_CYCLE=,CLK4_MULTIPLY_BY=,CLK4_PHASE_SHIFT=,CLK5_DIVIDE_BY=,CLK5_DUTY_CYCLE=,CLK5_MULTIPLY_BY=,CLK5_PHASE_SHIFT=,CLK6_DIVIDE_BY=,CLK6_DUTY_CYCLE=,CLK6_MULTIPLY_BY=,CLK6_PHASE_SHIFT=,CLK7_DIVIDE_BY=,CLK7_DUTY_CYCLE=,CLK7_MULTIPLY_BY=,CLK7_PHASE_SHIFT=,CLK8_DIVIDE_BY=,CLK8_DUTY_CYCLE=,CLK8_MULTIPLY_BY=,CLK8_PHASE_SHIFT=,CLK9_DIVIDE_BY=,CLK9_DUTY_CYCLE=,CLK9_MULTIPLY_BY=,CLK9_PHASE_SHIFT=,COMPENSATE_CLOCK=CLK0,DOWN_SPREAD=,DPA_DIVIDER=,DPA_DIVIDE_BY=,DPA_MULTIPLY_BY=,ENABLE_SWITCH_OVER_COUNTER=,EXTCLK0_DIVIDE_BY=,EXTCLK0_DUTY_CYCLE=,EXTCLK0_MULTIPLY_BY=,EXTCLK0_PHASE_SHIFT=,EXTCLK1_DIVIDE_BY=,EXTCLK1_DUTY_CYCLE=,EXTCLK1_MULTIPLY_BY=,EXTCLK1_PHASE_SHIFT=,EXTCLK2_DIVIDE_BY=,EXTCLK2_DUTY_CYCLE=,EXTCLK2_MULTIPLY_BY=,EXTCLK2_PHASE_SHIFT=,EXTCLK3_DIVIDE_BY=,EXTCLK3_DUTY_CYCLE=,EXTCLK3_MULTIPLY_BY=,EXTCLK3_PHASE_SHIFT=,FEEDBACK_SOURCE=,GATE_LOCK_COUNTER=,GATE_LOCK_SIGNAL=,HIDDEN_CONSTANTS=CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED,HIDDEN_CUSTOM_ELABORATION=altpll_avalon_elaboration,HIDDEN_CUSTOM_POST_EDIT=altpll_avalon_post_edit,HIDDEN_IF_PORTS=IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0},HIDDEN_IS_FIRST_EDIT=0,HIDDEN_IS_NUMERIC=IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1,HIDDEN_MF_PORTS=MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1,HIDDEN_PRIVATES=PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0,HIDDEN_USED_PORTS=UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used,INCLK0_INPUT_FREQUENCY=20000,INCLK1_INPUT_FREQUENCY=,INTENDED_DEVICE_FAMILY=MAX 10,INVALID_LOCK_MULTIPLIER=,LOCK_HIGH=,LOCK_LOW=,OPERATION_MODE=NORMAL,PLL_TYPE=AUTO,PORT_ACTIVECLOCK=PORT_UNUSED,PORT_ARESET=PORT_USED,PORT_CLKBAD0=PORT_UNUSED,PORT_CLKBAD1=PORT_UNUSED,PORT_CLKLOSS=PORT_UNUSED,PORT_CLKSWITCH=PORT_UNUSED,PORT_CONFIGUPDATE=PORT_UNUSED,PORT_ENABLE0=,PORT_ENABLE1=,PORT_FBIN=PORT_UNUSED,PORT_FBOUT=,PORT_INCLK0=PORT_USED,PORT_INCLK1=PORT_UNUSED,PORT_LOCKED=PORT_USED,PORT_PFDENA=PORT_UNUSED,PORT_PHASECOUNTERSELECT=PORT_UNUSED,PORT_PHASEDONE=PORT_UNUSED,PORT_PHASESTEP=PORT_UNUSED,PORT_PHASEUPDOWN=PORT_UNUSED,PORT_PLLENA=PORT_UNUSED,PORT_SCANACLR=PORT_UNUSED,PORT_SCANCLK=PORT_UNUSED,PORT_SCANCLKENA=PORT_UNUSED,PORT_SCANDATA=PORT_UNUSED,PORT_SCANDATAOUT=PORT_UNUSED,PORT_SCANDONE=PORT_UNUSED,PORT_SCANREAD=PORT_UNUSED,PORT_SCANWRITE=PORT_UNUSED,PORT_SCLKOUT0=,PORT_SCLKOUT1=,PORT_VCOOVERRANGE=,PORT_VCOUNDERRANGE=,PORT_clk0=PORT_USED,PORT_clk1=PORT_UNUSED,PORT_clk2=PORT_UNUSED,PORT_clk3=PORT_UNUSED,PORT_clk4=PORT_UNUSED,PORT_clk5=PORT_UNUSED,PORT_clk6=,PORT_clk7=,PORT_clk8=,PORT_clk9=,PORT_clkena0=PORT_UNUSED,PORT_clkena1=PORT_UNUSED,PORT_clkena2=PORT_UNUSED,PORT_clkena3=PORT_UNUSED,PORT_clkena4=PORT_UNUSED,PORT_clkena5=PORT_UNUSED,PORT_extclk0=PORT_UNUSED,PORT_extclk1=PORT_UNUSED,PORT_extclk2=PORT_UNUSED,PORT_extclk3=PORT_UNUSED,PORT_extclkena0=,PORT_extclkena1=,PORT_extclkena2=,PORT_extclkena3=,PRIMARY_CLOCK=,QUALIFY_CONF_DONE=,SCAN_CHAIN=,SCAN_CHAIN_MIF_FILE=,SCLKOUT0_PHASE_SHIFT=,SCLKOUT1_PHASE_SHIFT=,SELF_RESET_ON_GATED_LOSS_LOCK=,SELF_RESET_ON_LOSS_LOCK=,SKIP_VCO=,SPREAD_FREQUENCY=,SWITCH_OVER_COUNTER=,SWITCH_OVER_ON_GATED_LOCK=,SWITCH_OVER_ON_LOSSCLK=,SWITCH_OVER_TYPE=,USING_FBMIMICBIDIR_PORT=,VALID_LOCK_MULTIPLIER=,VCO_DIVIDE_BY=,VCO_FREQUENCY_CONTROL=,VCO_MULTIPLY_BY=,VCO_PHASE_SHIFT_STEP=,WIDTH_CLOCK=5,WIDTH_PHASECOUNTERSELECT=)(altera_avalon_pio:19.1:bitClearingEdgeCapReg=false,bitModifyingOutReg=false,captureEdge=false,clockRate=50000000,derived_capture=false,derived_do_test_bench_wiring=false,derived_edge_type=NONE,derived_has_in=true,derived_has_irq=false,derived_has_out=false,derived_has_tri=false,derived_irq_type=NONE,direction=Input,edgeType=RISING,generateIRQ=false,irqType=LEVEL,resetValue=0,simDoTestBenchWiring=false,simDrivenValue=0,width=9)(altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=q_sys_calibration_ram,blockType=AUTO,copyInitFile=false,dataWidth=16,dataWidth2=16,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=q_sys_calibration_ram.hex,derived_is_hardcopy=false,derived_set_addr_width=9,derived_set_addr_width2=9,derived_set_data_width=16,derived_set_data_width2=16,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=640,readDuringWriteMode=DONT_CARE,resetrequest_enabled=false,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true)(channel_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=1,inErrorDescriptor=,inErrorWidth=1,inMaxChannel=1,inReadyLatency=0,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,outChannelWidth=0,outMaxChannel=1)(altera_nios2_gen2:19.1:AUTO_CLK_CLOCK_DOMAIN=14,AUTO_CLK_RESET_DOMAIN=14,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,bht_ramBlockType=Automatic,breakAbsoluteAddr=406857760,breakOffset=32,breakSlave=cpu.jtag_debug_module,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,customInstSlavesSystemInfo=<info/>,customInstSlavesSystemInfo_nios_a=<info/>,customInstSlavesSystemInfo_nios_b=<info/>,customInstSlavesSystemInfo_nios_c=<info/>,dataAddrWidth=29,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='calibration_ram.s1' start='0x18403400' end='0x18403680' type='altera_avalon_onchip_memory2.s1' /><slave name='frame_timer.s1' start='0x18403C00' end='0x18403C20' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403C20' end='0x18403C40' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403C40' end='0x18403C60' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403C60' end='0x18403C80' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403C80' end='0x18403CA0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x18403CA0' end='0x18403CC0' type='altera_msgdma.prefetcher_csr' /><slave name='udp_generator.csr' start='0x18403CC0' end='0x18403CE0' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403CE0' end='0x18403D00' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403D00' end='0x18403D20' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403D20' end='0x18403D40' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403D40' end='0x18403D50' type='altera_avalon_pio.s1' /><slave name='sensor_interface.csr' start='0x18403D50' end='0x18403D60' type='sensor_recon.csr' /><slave name='onchip_flash.csr' start='0x18403D60' end='0x18403D68' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403D68' end='0x18403D70' type='altera_avalon_sysid_qsys.control_slave' /></address-map>,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_size=0,data_master_paddr_base=0,data_master_paddr_size=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=2,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=MAX 10,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=134218016,exceptionOffset=288,exceptionSlave=ddr3_ram.avl,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_size=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=2048,icache_tagramBlockType=Automatic,impl=Fast,instAddrWidth=29,instSlaveMapParam=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_size=0,instruction_master_paddr_base=0,instruction_master_paddr_size=0,internalIrqMaskSystemInfo=61,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,mul_32_impl=3,mul_64_impl=0,mul_shift_choice=0,multiplierType=mul_fast32,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=335544320,resetOffset=0,resetSlave=ext_flash.avl_mem,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=true,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=true,setting_branchpredictiontype=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=false,setting_disable_tmr_inj=false,setting_disableocitrace=false,setting_dtcm_ecc_present=false,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportHostDebugPort=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=false,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_tmr_output_disable=false,setting_usedesignware=false,shift_rot_impl=0,shifterType=fast_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_size=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_size=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_size=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_size=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_size=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_size=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_size=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_size=0,tmr_enabled=false,tracefilename=,translate_off= "synthesis translate_off" ,translate_on= "synthesis translate_on" ,userDefinedSettings=(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=50000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=1)(altera_nios2_gen2_unit:19.1:bht_ramBlockType=Automatic,breakAbsoluteAddr=406857760,breakOffset=32,breakSlave=cpu.jtag_debug_module,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,cpu_name=cpu,customInstSlavesSystemInfo=<info/>,dataAddrWidth=29,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='calibration_ram.s1' start='0x18403400' end='0x18403680' type='altera_avalon_onchip_memory2.s1' /><slave name='frame_timer.s1' start='0x18403C00' end='0x18403C20' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403C20' end='0x18403C40' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403C40' end='0x18403C60' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403C60' end='0x18403C80' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403C80' end='0x18403CA0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x18403CA0' end='0x18403CC0' type='altera_msgdma.prefetcher_csr' /><slave name='udp_generator.csr' start='0x18403CC0' end='0x18403CE0' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403CE0' end='0x18403D00' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403D00' end='0x18403D20' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403D20' end='0x18403D40' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403D40' end='0x18403D50' type='altera_avalon_pio.s1' /><slave name='sensor_interface.csr' start='0x18403D50' end='0x18403D60' type='sensor_recon.csr' /><slave name='onchip_flash.csr' start='0x18403D60' end='0x18403D68' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403D68' end='0x18403D70' type='altera_avalon_sysid_qsys.control_slave' /></address-map>,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_top=0,data_master_paddr_base=0,data_master_paddr_top=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=2,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=MAX 10,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=134218016,exceptionOffset=288,exceptionSlave=ddr3_ram.avl,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_top=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=2048,icache_tagramBlockType=Automatic,impl=Fast,instAddrWidth=29,instSlaveMapParam=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_top=0,instruction_master_paddr_base=0,instruction_master_paddr_top=0,internalIrqMaskSystemInfo=61,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,multiplierType=mul_fast32,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=335544320,resetOffset=0,resetSlave=ext_flash.avl_mem,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=true,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=true,setting_branchPredictionType=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=false,setting_disableocitrace=false,setting_dtcm_ecc_present=false,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=false,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_usedesignware=false,shifterType=fast_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_top=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_top=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_top=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_top=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_top=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_top=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_top=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_top=0,tmr_enabled=false,tracefilename=,translate_off= "synthesis translate_off" ,translate_on= "synthesis translate_on" ,userDefinedSettings=)(clock:19.1:)(clock:19.1:)(reset:19.1:))(altera_mem_if_ddr3_emif:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=true,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=true,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=100.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=NIOS,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,SPEED_GRADE_CACHE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=true,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=150000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=300000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_mem_if_ddr3_pll:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PERIOD_PS=10000,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_ddr3_phy_core:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_ddr3_afi_mux:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,CFG_TCCD=1,CFG_TCCD_NS=2.5,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEXTGEN=true,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,PRE_V_SERIES_FAMILY=false,RATE=Half,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false)(altera_mem_if_ddr3_afi_splitter:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,CFG_TCCD=1,CFG_TCCD_NS=2.5,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEXTGEN=true,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,PRE_V_SERIES_FAMILY=false,RATE=Half,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false)(altera_mem_if_ddr3_qseq:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_MAX_READ_LATENCY_COUNT_WIDTH=6,AFI_MAX_WRITE_LATENCY_COUNT_WIDTH=6,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AVL_ADDR_WIDTH=13,AVL_DATA_WIDTH=32,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_nextgen_ddr3_controller:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6(altera_mem_if_nextgen_ddr3_controller_core:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(alt_mem_ddrx_mm_st_converter:19.1:AVL_ADDR_WIDTH=25,AVL_BYTE_ENABLE=true,AVL_DATA_WIDTH=32,AVL_NUM_SYMBOLS=4,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,CFG_DWIDTH_RATIO=4,CTL_AUTOPCH_EN=false,CTL_ECC_ENABLED=false,ENABLE_CTRL_AVALON_INTERFACE=true,LOCAL_ID_WIDTH=8,MAX_PENDING_READ_TRANSACTION=32,MULTICAST_EN=false)(clock:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:))(altera_mem_if_pll_bridge:19.1:CORE_PERIPHERY_DUAL_CLOCK=false,CUT_NEW_FAMILY_TIMING=true,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DISABLE_CHILD_MESSAGING=true,DUPLICATE_PLL_FOR_PHY_CLK=false,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,NUM_PLL_SHARING_INTERFACES=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PRE_V_SERIES_FAMILY=false,RATE=Half,SEQUENCER_TYPE=NIOS,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,USE_DR_CLK=false)(clock:19.1:)(reset:19.1:)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:)(clock:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0))(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_avalon_uart:19.1:baud=115200,baudError=0.01,clockRate=50000000,dataBits=8,fixedBaud=true,parity=NONE,parityFisrtChar=N,simCharStream=,simInteractiveInputEnable=false,simInteractiveOutputEnable=false,simTrueBaud=false,stopBits=1,syncRegDepth=2,useCtsRts=false,useEopRegister=false,useRelativePathForSimFile=false)(altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=q_sys_descriptor_memory,blockType=AUTO,copyInitFile=false,dataWidth=32,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=q_sys_descriptor_memory.hex,derived_is_hardcopy=false,derived_set_addr_width=11,derived_set_addr_width2=11,derived_set_data_width=32,derived_set_data_width2=32,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=false,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex,instanceID=NONE,memorySize=8192,readDuringWriteMode=DONT_CARE,resetrequest_enabled=true,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true)(altpll:19.1:AUTO_DEVICE_FAMILY=MAX 10,AUTO_INCLK_INTERFACE_CLOCK_RATE=50000000,AVALON_USE_SEPARATE_SYSCLK=NO,BANDWIDTH=,BANDWIDTH_TYPE=AUTO,CLK0_DIVIDE_BY=2,CLK0_DUTY_CYCLE=50,CLK0_MULTIPLY_BY=5,CLK0_PHASE_SHIFT=0,CLK1_DIVIDE_BY=2,CLK1_DUTY_CYCLE=50,CLK1_MULTIPLY_BY=1,CLK1_PHASE_SHIFT=0,CLK2_DIVIDE_BY=20,CLK2_DUTY_CYCLE=50,CLK2_MULTIPLY_BY=1,CLK2_PHASE_SHIFT=0,CLK3_DIVIDE_BY=2,CLK3_DUTY_CYCLE=50,CLK3_MULTIPLY_BY=5,CLK3_PHASE_SHIFT=-3000,CLK4_DIVIDE_BY=2,CLK4_DUTY_CYCLE=50,CLK4_MULTIPLY_BY=1,CLK4_PHASE_SHIFT=-10000,CLK5_DIVIDE_BY=,CLK5_DUTY_CYCLE=,CLK5_MULTIPLY_BY=,CLK5_PHASE_SHIFT=,CLK6_DIVIDE_BY=,CLK6_DUTY_CYCLE=,CLK6_MULTIPLY_BY=,CLK6_PHASE_SHIFT=,CLK7_DIVIDE_BY=,CLK7_DUTY_CYCLE=,CLK7_MULTIPLY_BY=,CLK7_PHASE_SHIFT=,CLK8_DIVIDE_BY=,CLK8_DUTY_CYCLE=,CLK8_MULTIPLY_BY=,CLK8_PHASE_SHIFT=,CLK9_DIVIDE_BY=,CLK9_DUTY_CYCLE=,CLK9_MULTIPLY_BY=,CLK9_PHASE_SHIFT=,COMPENSATE_CLOCK=CLK0,DOWN_SPREAD=,DPA_DIVIDER=,DPA_DIVIDE_BY=,DPA_MULTIPLY_BY=,ENABLE_SWITCH_OVER_COUNTER=,EXTCLK0_DIVIDE_BY=,EXTCLK0_DUTY_CYCLE=,EXTCLK0_MULTIPLY_BY=,EXTCLK0_PHASE_SHIFT=,EXTCLK1_DIVIDE_BY=,EXTCLK1_DUTY_CYCLE=,EXTCLK1_MULTIPLY_BY=,EXTCLK1_PHASE_SHIFT=,EXTCLK2_DIVIDE_BY=,EXTCLK2_DUTY_CYCLE=,EXTCLK2_MULTIPLY_BY=,EXTCLK2_PHASE_SHIFT=,EXTCLK3_DIVIDE_BY=,EXTCLK3_DUTY_CYCLE=,EXTCLK3_MULTIPLY_BY=,EXTCLK3_PHASE_SHIFT=,FEEDBACK_SOURCE=,GATE_LOCK_COUNTER=,GATE_LOCK_SIGNAL=,HIDDEN_CONSTANTS=CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED,HIDDEN_CUSTOM_ELABORATION=altpll_avalon_elaboration,HIDDEN_CUSTOM_POST_EDIT=altpll_avalon_post_edit,HIDDEN_IF_PORTS=IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0},HIDDEN_IS_FIRST_EDIT=0,HIDDEN_IS_NUMERIC=IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1,HIDDEN_MF_PORTS=MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1,HIDDEN_PRIVATES=PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0,HIDDEN_USED_PORTS=UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used,INCLK0_INPUT_FREQUENCY=20000,INCLK1_INPUT_FREQUENCY=,INTENDED_DEVICE_FAMILY=MAX 10,INVALID_LOCK_MULTIPLIER=,LOCK_HIGH=,LOCK_LOW=,OPERATION_MODE=NO_COMPENSATION,PLL_TYPE=AUTO,PORT_ACTIVECLOCK=PORT_UNUSED,PORT_ARESET=PORT_UNUSED,PORT_CLKBAD0=PORT_UNUSED,PORT_CLKBAD1=PORT_UNUSED,PORT_CLKLOSS=PORT_UNUSED,PORT_CLKSWITCH=PORT_UNUSED,PORT_CONFIGUPDATE=PORT_UNUSED,PORT_ENABLE0=,PORT_ENABLE1=,PORT_FBIN=PORT_UNUSED,PORT_FBOUT=,PORT_INCLK0=PORT_USED,PORT_INCLK1=PORT_UNUSED,PORT_LOCKED=PORT_USED,PORT_PFDENA=PORT_UNUSED,PORT_PHASECOUNTERSELECT=PORT_UNUSED,PORT_PHASEDONE=PORT_UNUSED,PORT_PHASESTEP=PORT_UNUSED,PORT_PHASEUPDOWN=PORT_UNUSED,PORT_PLLENA=PORT_UNUSED,PORT_SCANACLR=PORT_UNUSED,PORT_SCANCLK=PORT_UNUSED,PORT_SCANCLKENA=PORT_UNUSED,PORT_SCANDATA=PORT_UNUSED,PORT_SCANDATAOUT=PORT_UNUSED,PORT_SCANDONE=PORT_UNUSED,PORT_SCANREAD=PORT_UNUSED,PORT_SCANWRITE=PORT_UNUSED,PORT_SCLKOUT0=,PORT_SCLKOUT1=,PORT_VCOOVERRANGE=,PORT_VCOUNDERRANGE=,PORT_clk0=PORT_USED,PORT_clk1=PORT_USED,PORT_clk2=PORT_USED,PORT_clk3=PORT_USED,PORT_clk4=PORT_USED,PORT_clk5=PORT_UNUSED,PORT_clk6=,PORT_clk7=,PORT_clk8=,PORT_clk9=,PORT_clkena0=PORT_UNUSED,PORT_clkena1=PORT_UNUSED,PORT_clkena2=PORT_UNUSED,PORT_clkena3=PORT_UNUSED,PORT_clkena4=PORT_UNUSED,PORT_clkena5=PORT_UNUSED,PORT_extclk0=PORT_UNUSED,PORT_extclk1=PORT_UNUSED,PORT_extclk2=PORT_UNUSED,PORT_extclk3=PORT_UNUSED,PORT_extclkena0=,PORT_extclkena1=,PORT_extclkena2=,PORT_extclkena3=,PRIMARY_CLOCK=,QUALIFY_CONF_DONE=,SCAN_CHAIN=,SCAN_CHAIN_MIF_FILE=,SCLKOUT0_PHASE_SHIFT=,SCLKOUT1_PHASE_SHIFT=,SELF_RESET_ON_GATED_LOSS_LOCK=,SELF_RESET_ON_LOSS_LOCK=,SKIP_VCO=,SPREAD_FREQUENCY=,SWITCH_OVER_COUNTER=,SWITCH_OVER_ON_GATED_LOCK=,SWITCH_OVER_ON_LOSSCLK=,SWITCH_OVER_TYPE=,USING_FBMIMICBIDIR_PORT=,VALID_LOCK_MULTIPLIER=,VCO_DIVIDE_BY=,VCO_FREQUENCY_CONTROL=,VCO_MULTIPLY_BY=,VCO_PHASE_SHIFT_STEP=,WIDTH_CLOCK=5,WIDTH_PHASECOUNTERSELECT=)(altera_eth_tse:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,XCVR_RCFG_JTAG_ENABLE=0,XCVR_SET_CAPABILITY_REG_ENABLE=0,XCVR_SET_CSR_SOFT_LOGIC_ENABLE=0,XCVR_SET_PRBS_SOFT_LOGIC_ENABLE=0,XCVR_SET_USER_IDENTIFIER=0,core_variation=MAC_ONLY,core_version=4865,dev_version=4865,deviceFamily=MAX10,deviceFamilyName=MAX 10,eg_addr=11,eg_fifo=2048,ena_hash=false,enable_alt_reconfig=false,enable_clk_sharing=false,enable_ecc=false,enable_ena=32,enable_gmii_loopback=true,enable_hd_logic=true,enable_lgth_check=true,enable_mac_flow_ctrl=false,enable_mac_vlan=false,enable_magic_detect=true,enable_padding=true,enable_ptp_1step=false,enable_sgmii=true,enable_shift16=true,enable_sup_addr=false,enable_timestamping=false,enable_use_internal_fifo=true,export_pwrdn=false,ext_stat_cnt_ena=false,gbit_only=true,ifGMII=RGMII,ing_addr=11,ing_fifo=2048,isUseMAC=true,isUsePCS=false,max_channels=1,mbit_only=true,mdio_clk_div=40,nf_lvds_iopll_num_channels=4,nf_phyip_rcfg_enable=true,phy_identifier=0,phyip_en_synce_support=false,phyip_pll_base_data_rate=1250 Mbps,phyip_pll_type=CMU,phyip_pma_bonding_mode=x1,reduced_control=false,reduced_interface_ena=true,starting_channel_number=0,stat_cnt_ena=true,synchronizer_depth=3,transceiver_type=NONE,tstamp_fp_width=4,useMDIO=true,use_mac_clken=false,use_misc_ports=true(altera_eth_tse_mac:19.1:CORE_VERSION=4865,CRC32CHECK16BIT=0,CRC32DWIDTH=8,CRC32GENDELAY=6,CRC32S1L2_EXTERN=false,CUST_VERSION=0,DEVICE_FAMILY=MAX10,EG_ADDR=11,EG_FIFO=2048,ENABLE_ECC=false,ENABLE_ENA=32,ENABLE_EXTENDED_STAT_REG=false,ENABLE_GMII_LOOPBACK=true,ENABLE_HD_LOGIC=true,ENABLE_LGTH_CHECK=true,ENABLE_MAC_FLOW_CTRL=false,ENABLE_MAC_RX_VLAN=false,ENABLE_MAC_TXADDR_SET=true,ENABLE_MAC_TX_VLAN=false,ENABLE_MAGIC_DETECT=true,ENABLE_MDIO=true,ENABLE_PADDING=true,ENABLE_SHIFT16=true,ENABLE_SUP_ADDR=false,ENA_HASH=false,GBIT_ONLY=true,ING_ADDR=11,ING_FIFO=2048,INSERT_TA=false,MBIT_ONLY=true,MDIO_CLK_DIV=40,RAM_TYPE=AUTO,REDUCED_CONTROL=false,REDUCED_INTERFACE_ENA=true,RESET_LEVEL=1,STAT_CNT_ENA=true,SYNCHRONIZER_DEPTH=3,USE_SYNC_RESET=true,connect_to_pcs=false,ifGMII=RGMII,use_mac_clken=false,use_misc_ports=true)(altera_gpio_lite:19.1:ASYNC_MODE=none,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=input,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=4,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=false,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=none,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=input,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=1,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=false,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=clear,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=output,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=4,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=true,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=clear,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=output,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=1,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=true,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0))(altera_generic_quad_spi_controller:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=Micron512,IO_MODE=QUAD,UNIQUE_ID=q_sys_ext_flash,clkFreq=0,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1(altera_generic_quad_spi_controller:19.1:CS_WIDTH=1,IO_MODE=QUAD(soft_asmiblock:19.1:CS_WIDTH=1,IO_MODE=QUAD))(altera_generic_quad_spi_controller:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_USED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_USED,PORT_ILLEGAL_ERASE=PORT_USED,PORT_ILLEGAL_WRITE=PORT_USED,PORT_RDID_OUT=PORT_USED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_USED,PORT_READ_RDID=PORT_USED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_USED,PORT_SECTOR_ERASE=PORT_USED,PORT_SECTOR_PROTECT=PORT_USED,PORT_SHIFT_BYTES=PORT_USED,PORT_WREN=PORT_USED,PORT_WRITE=PORT_USED,USE_ASMIBLOCK=OFF,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true(altera_asmi_parallel:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_USED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_USED,PORT_ILLEGAL_ERASE=PORT_USED,PORT_ILLEGAL_WRITE=PORT_USED,PORT_RDID_OUT=PORT_USED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_USED,PORT_READ_RDID=PORT_USED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_USED,PORT_SECTOR_ERASE=PORT_USED,PORT_SECTOR_PROTECT=PORT_USED,PORT_SHIFT_BYTES=PORT_USED,PORT_WREN=PORT_USED,PORT_WRITE=PORT_USED,USE_ASMIBLOCK=OFF,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true))(altera_generic_quad_spi_controller:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None(altera_epcq_controller_core:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None)))(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_avalon_timer:19.1:alwaysRun=false,counterSize=32,fixedPeriod=false,loadValue=4999,mult=2.0E-8,period=5000,periodUnits=CLOCKS,periodUnitsString=clocks,resetOutput=false,slave_address_width=3,snapshot=false,systemFrequency=50000000,ticksPerSec=10000.0,timeoutPulseOutput=true,timerPreset=CUSTOM,valueInSecond=0.0,watchdogPulse=2)(altera_msgdma:19.1:AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP=<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>,AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP=<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_MM_READ_ADDRESS_MAP=,AUTO_MM_READ_ADDRESS_WIDTH=AddressWidth = -1,AUTO_MM_WRITE_ADDRESS_MAP=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>,AUTO_MM_WRITE_ADDRESS_WIDTH=AddressWidth = 28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CHANNEL_ENABLE=0,CHANNEL_ENABLE_DERIVED=0,CHANNEL_WIDTH=8,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_FIFO_DEPTH=8,ENHANCED_FEATURES=0,ERROR_ENABLE=1,ERROR_ENABLE_DERIVED=1,ERROR_WIDTH=6,EXPOSE_ST_PORT=0,FIX_ADDRESS_WIDTH=32,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=2,PACKET_ENABLE=1,PACKET_ENABLE_DERIVED=1,PREFETCHER_DATA_WIDTH=32,PREFETCHER_ENABLE=1,PREFETCHER_MAX_READ_BURST_COUNT=2,PREFETCHER_READ_BURST_ENABLE=0,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=2,STRIDE_ENABLE=0,STRIDE_ENABLE_DERIVED=0,TRANSFER_TYPE=Aligned Accesses,USE_FIX_ADDRESS_WIDTH=0(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(modular_sgdma_dispatcher:19.1:BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CSR_ADDRESS_WIDTH=3,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_BYTEENABLE_WIDTH=16,DESCRIPTOR_FIFO_DEPTH=8,DESCRIPTOR_INTERFACE=1,DESCRIPTOR_WIDTH=128,ENHANCED_FEATURES=0,GUI_RESPONSE_PORT=2,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=2,PREFETCHER_USE_CASE=1,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=1,STRIDE_ENABLE=0,TRANSFER_TYPE=Aligned Accesses)(altera_msgdma_prefetcher:19.1:ADDRESS_WIDTH=29,AUTO_ADDRESS_WIDTH=29,DATA_BYTEENABLE_WIDTH=4,DATA_WIDTH=32,DESCRIPTOR_WIDTH=128,ENABLE_READ_BURST=0,ENHANCED_FEATURES=0,FIX_ADDRESS_WIDTH=32,GUI_DESCRIPTOR_FIFO_DEPTH=8,GUI_MAX_READ_BURST_COUNT=2,MAX_READ_BURST_COUNT=1,MAX_READ_BURST_COUNT_WIDTH=1,RESPONSE_FIFO_DEPTH=16,RESPONSE_FIFO_DEPTH_LOG2=4,USE_FIX_ADDRESS_WIDTH=0)(dma_write_master:19.1:ACTUAL_BYTES_TRANSFERRED_WIDTH=13,ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=6,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:))(altera_msgdma:19.1:AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP=<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>,AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP=<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_MM_READ_ADDRESS_MAP=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>,AUTO_MM_READ_ADDRESS_WIDTH=AddressWidth = 28,AUTO_MM_WRITE_ADDRESS_MAP=,AUTO_MM_WRITE_ADDRESS_WIDTH=AddressWidth = -1,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CHANNEL_ENABLE=0,CHANNEL_ENABLE_DERIVED=0,CHANNEL_WIDTH=8,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_FIFO_DEPTH=8,ENHANCED_FEATURES=0,ERROR_ENABLE=1,ERROR_ENABLE_DERIVED=1,ERROR_WIDTH=1,EXPOSE_ST_PORT=0,FIX_ADDRESS_WIDTH=32,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=1,PACKET_ENABLE=1,PACKET_ENABLE_DERIVED=1,PREFETCHER_DATA_WIDTH=32,PREFETCHER_ENABLE=1,PREFETCHER_MAX_READ_BURST_COUNT=2,PREFETCHER_READ_BURST_ENABLE=0,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=2,STRIDE_ENABLE=0,STRIDE_ENABLE_DERIVED=0,TRANSFER_TYPE=Aligned Accesses,USE_FIX_ADDRESS_WIDTH=0(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(modular_sgdma_dispatcher:19.1:BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CSR_ADDRESS_WIDTH=3,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_BYTEENABLE_WIDTH=16,DESCRIPTOR_FIFO_DEPTH=8,DESCRIPTOR_INTERFACE=1,DESCRIPTOR_WIDTH=128,ENHANCED_FEATURES=0,GUI_RESPONSE_PORT=2,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=1,PREFETCHER_USE_CASE=1,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=1,STRIDE_ENABLE=0,TRANSFER_TYPE=Aligned Accesses)(altera_msgdma_prefetcher:19.1:ADDRESS_WIDTH=29,AUTO_ADDRESS_WIDTH=29,DATA_BYTEENABLE_WIDTH=4,DATA_WIDTH=32,DESCRIPTOR_WIDTH=128,ENABLE_READ_BURST=0,ENHANCED_FEATURES=0,FIX_ADDRESS_WIDTH=32,GUI_DESCRIPTOR_FIFO_DEPTH=8,GUI_MAX_READ_BURST_COUNT=2,MAX_READ_BURST_COUNT=1,MAX_READ_BURST_COUNT_WIDTH=1,RESPONSE_FIFO_DEPTH=16,RESPONSE_FIFO_DEPTH_LOG2=4,USE_FIX_ADDRESS_WIDTH=0)(dma_read_master:19.1:ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,CHANNEL_ENABLE=0,CHANNEL_WIDTH=8,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=1,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:))(altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=360447,ADDR_RANGE1_OFFSET=2048,ADDR_RANGE2_END_ADDR=360447,ADDR_RANGE2_OFFSET=0,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=50000000,AVMM_DATA_ADDR_WIDTH=19,AVMM_DATA_BURSTCOUNT_WIDTH=4,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=50.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=50,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=60,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=17500000,FLASH_READ_CYCLE_MAX_INDEX=5,FLASH_RESET_CYCLE_MAX_INDEX=12,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=15250,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=114687,MAX_VALID_ADDR=360447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M50DAF484C6GES,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=8,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=8191,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=16383,SECTOR2_MAP=2,SECTOR2_START_ADDR=8192,SECTOR3_END_ADDR=114687,SECTOR3_MAP=3,SECTOR3_START_ADDR=16384,SECTOR4_END_ADDR=188415,SECTOR4_MAP=4,SECTOR4_START_ADDR=114688,SECTOR5_END_ADDR=360447,SECTOR5_MAP=5,SECTOR5_START_ADDR=188416,SECTOR_ACCESS_MODE=Read and write,Read and write,Read and write,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x07fff,0x08000 - 0x0ffff,0x10000 - 0x6ffff,0x70000 - 0xb7fff,0xb8000 - 0x15ffff,SECTOR_ID=1,2,3,4,5,SECTOR_READ_PROTECTION_MODE=0,SECTOR_STORAGE_TYPE=UFM,UFM,UFM,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=q_sys_onchip_flash,initFlashContent=false,initializationFileName=D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false)(altera_avalon_pio:19.1:bitClearingEdgeCapReg=false,bitModifyingOutReg=true,captureEdge=false,clockRate=50000000,derived_capture=false,derived_do_test_bench_wiring=false,derived_edge_type=NONE,derived_has_in=false,derived_has_irq=false,derived_has_out=true,derived_has_tri=false,derived_irq_type=NONE,direction=Output,edgeType=RISING,generateIRQ=false,irqType=LEVEL,resetValue=0,simDoTestBenchWiring=false,simDrivenValue=0,width=8)(sensor_recon:1:)(clock_source:19.1:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_avalon_timer:19.1:alwaysRun=false,counterSize=32,fixedPeriod=false,loadValue=499999,mult=0.001,period=10,periodUnits=MSEC,periodUnitsString=ms,resetOutput=false,slave_address_width=3,snapshot=true,systemFrequency=50000000,ticksPerSec=100.0,timeoutPulseOutput=false,timerPreset=FULL_FEATURED,valueInSecond=0.001,watchdogPulse=2)(altera_avalon_sysid_qsys:19.1:id=-87110914,timestamp=1728634208)(multiplexer:19.1:bitsPerSymbol=8,errorWidth=1,inErrorWidth=1,inUseEmpty=false,inUseEmptyPort=AUTO,inUsePackets=true,numInputInterfaces=2,outChannelWidth=1,packetScheduling=true,schedulingSize=512,symbolsPerBeat=4,useHighBitsOfChannel=true,usePackets=true)(udp_generator:1.0:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x08000000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d20,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x14000000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d68,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d00,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403ce0,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d60,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403cc0,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d50,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18200000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18402800,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403ca0,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403c80,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18400000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403c60,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403c40,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403d40,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403c20,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403c00,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18403400,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18400000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18400000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18400000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18400000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x08000000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x14000000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18200000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x18402800,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x08000000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x08000000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)(interrupt:19.1:irqNumber=2)(interrupt:19.1:irqNumber=3)(interrupt:19.1:irqNumber=5)(interrupt:19.1:irqNumber=0)(interrupt:19.1:irqNumber=4)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)(reset:19.1:)"
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instancePathKey="q_sys"
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kind="q_sys"
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version="1.0"
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name="q_sys">
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<parameter name="AUTO_DDR3_RAM_PLL_REF_CLK_RESET_DOMAIN" value="-1" />
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<parameter name="AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_DOMAIN" value="-1" />
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<parameter name="AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_RATE" value="-1" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="-1" />
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<parameter name="AUTO_GENERATION_ID" value="1728634208" />
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<parameter name="AUTO_DDR3_RAM_PLL_REF_CLK_CLOCK_DOMAIN" value="-1" />
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<parameter name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_RATE" value="-1" />
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<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
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<parameter
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name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_RESET_DOMAIN"
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value="-1" />
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<parameter
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name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_RESET_DOMAIN"
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value="-1" />
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<parameter
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name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_DOMAIN"
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value="-1" />
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<parameter
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name="AUTO_ETH_TSE_PCS_MAC_RX_CLOCK_CONNECTION_CLOCK_DOMAIN"
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value="-1" />
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<parameter name="AUTO_UNIQUE_ID" value="" />
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<parameter name="AUTO_CLOCK_BRIDGE_0_IN_CLK_RESET_DOMAIN" value="-1" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
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<parameter name="AUTO_CLOCK_BRIDGE_0_IN_CLK_CLOCK_RATE" value="-1" />
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<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
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<parameter name="AUTO_ETH_TSE_PCS_MAC_TX_CLOCK_CONNECTION_CLOCK_RATE" value="-1" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="-1" />
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<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="-1" />
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<generatedFiles>
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/q_sys.v"
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type="VERILOG" />
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</generatedFiles>
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<childGeneratedFiles>
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_altpll_shift.v"
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type="VERILOG" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_button_pio.v"
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type="VERILOG"
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attributes="" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_calibration_ram.v"
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type="VERILOG"
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attributes="" />
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<file
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_channel_adapter_0.sv"
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type="SYSTEM_VERILOG"
|
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attributes="" />
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<file
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu.v"
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type="VERILOG" />
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<file
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller_core/alt_mem_if_nextgen_ddr3_controller_core_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
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<file
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|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr_controller_110/rtl/alt_mem_ddrx_mm_st_converter/alt_mem_ddrx_mm_st_converter_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_uart/altera_avalon_uart_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_altpll/altera_avalon_altpll_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/ethernet/altera_eth_tse/altera_eth_tse_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/ethernet/tse_ucores/altera_eth_tse_mac/altera_eth_tse_mac_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_gpio_lite/altera_gpio_lite_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/generic_qspi_controller_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/soft_asmiblock_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_asmi_parallel/altera_asmi_parallel_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_epcq_controller/altera_epcq_controller_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/top/altera_msgdma_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/dispatcher/dispatcher_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/prefetcher/altera_msgdma_prefetcher_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/write_master/write_master_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/top/altera_msgdma_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/dispatcher/dispatcher_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/prefetcher/altera_msgdma_prefetcher_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/read_master/read_master_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/sensor_algo_qsys/sensor_recon_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_multiplexer/avalon-st_multiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/udp_generator_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
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<file
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|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" />
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<file
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|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_irq_clock_crosser/altera_irq_clock_crosser_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
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<file
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|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces ddr3_ram_avl_translator.avalon_anti_slave_0 and ddr3_ram.avl</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces ext_flash_avl_csr_translator.avalon_anti_slave_0 and ext_flash.avl_csr</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces ext_flash_avl_mem_translator.avalon_anti_slave_0 and ext_flash.avl_mem</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces eth_tse_control_port_translator.avalon_anti_slave_0 and eth_tse.control_port</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces sysid_control_slave_translator.avalon_anti_slave_0 and sysid.control_slave</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_tx_csr_translator.avalon_anti_slave_0 and msgdma_tx.csr</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_rx_csr_translator.avalon_anti_slave_0 and msgdma_rx.csr</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces onchip_flash_csr_translator.avalon_anti_slave_0 and onchip_flash.csr</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces udp_generator_csr_translator.avalon_anti_slave_0 and udp_generator.csr</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces sensor_interface_csr_translator.avalon_anti_slave_0 and sensor_interface.csr</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces onchip_flash_data_translator.avalon_anti_slave_0 and onchip_flash.data</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces cpu_debug_mem_slave_translator.avalon_anti_slave_0 and cpu.debug_mem_slave</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_tx_prefetcher_csr_translator.avalon_anti_slave_0 and msgdma_tx.prefetcher_csr</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces msgdma_rx_prefetcher_csr_translator.avalon_anti_slave_0 and msgdma_rx.prefetcher_csr</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces descriptor_memory_s1_translator.avalon_anti_slave_0 and descriptor_memory.s1</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces sys_clk_timer_s1_translator.avalon_anti_slave_0 and sys_clk_timer.s1</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces output_pio_s1_translator.avalon_anti_slave_0 and output_pio.s1</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces button_pio_s1_translator.avalon_anti_slave_0 and button_pio.s1</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces debug_uart_s1_translator.avalon_anti_slave_0 and debug_uart.s1</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces frame_timer_s1_translator.avalon_anti_slave_0 and frame_timer.s1</message>
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<message level="Debug">Transform merlin_domain_transform not run on matched interfaces calibration_ram_s1_translator.avalon_anti_slave_0 and calibration_ram.s1</message>
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<message level="Debug" culprit="merlin_domain_transform"><![CDATA[After transform: <b>103</b> modules, <b>479</b> connections]]></message>
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<message level="Debug">Transform: RouterTransform</message>
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<message level="Progress" culprit="min"></message>
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<message level="Debug" culprit="merlin_router_transform"><![CDATA[After transform: <b>132</b> modules, <b>574</b> connections]]></message>
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<message level="Debug">Transform: TrafficLimiterTransform</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug" culprit="merlin_traffic_limiter_transform"><![CDATA[After transform: <b>134</b> modules, <b>582</b> connections]]></message>
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<message level="Debug">Transform: BurstTransform</message>
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<message level="Progress" culprit="min"></message>
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<message level="Debug" culprit="merlin_burst_transform"><![CDATA[After transform: <b>136</b> modules, <b>589</b> connections]]></message>
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<message level="Debug">Transform: TreeTransform</message>
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<message level="Debug">Transform: NetworkToSwitchTransform</message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug" culprit="merlin_network_to_switch_transform"><![CDATA[After transform: <b>193</b> modules, <b>717</b> connections]]></message>
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<message level="Debug">Transform: WidthTransform</message>
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<message level="Progress" culprit="min"></message>
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<message level="Debug" culprit="merlin_width_transform"><![CDATA[After transform: <b>195</b> modules, <b>723</b> connections]]></message>
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<message level="Debug">Transform: RouterTableTransform</message>
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<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
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<message level="Debug">Transform: ClockCrossingTransform</message>
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<message level="Info">Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0</message>
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<message level="Progress" culprit="min"></message>
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<message level="Info">Inserting clock-crossing logic between cmd_demux.src1 and cmd_mux_001.sink0</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Info">Inserting clock-crossing logic between cmd_demux.src2 and cmd_mux_002.sink0</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Info">Inserting clock-crossing logic between cmd_demux_001.src0 and cmd_mux.sink1</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Info">Inserting clock-crossing logic between cmd_demux_001.src1 and cmd_mux_002.sink1</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Info">Inserting clock-crossing logic between cmd_demux_002.src0 and cmd_mux.sink2</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Info">Inserting clock-crossing logic between cmd_demux_003.src0 and cmd_mux.sink3</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Info">Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Info">Inserting clock-crossing logic between rsp_demux.src1 and rsp_mux_001.sink0</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Info">Inserting clock-crossing logic between rsp_demux.src2 and rsp_mux_002.sink0</message>
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<message level="Progress" culprit="min"></message>
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<message level="Info">Inserting clock-crossing logic between rsp_demux.src3 and rsp_mux_003.sink0</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Info">Inserting clock-crossing logic between rsp_demux_001.src0 and rsp_mux.sink1</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Info">Inserting clock-crossing logic between rsp_demux_002.src0 and rsp_mux.sink2</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Info">Inserting clock-crossing logic between rsp_demux_002.src1 and rsp_mux_001.sink1</message>
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<message level="Progress" culprit="min"></message>
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<message
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level="Debug"
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culprit="com_altera_sopcmodel_transforms_avalon_ClockCrossingTransform"><![CDATA[After transform: <b>209</b> modules, <b>807</b> connections]]></message>
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<message level="Debug">Transform: PipelineTransform</message>
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<message level="Debug">Transform: SpotPipelineTransform</message>
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<message level="Debug">Transform: PerformanceMonitorTransform</message>
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<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
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<message level="Debug" culprit="limiter_update_transform"><![CDATA[After transform: <b>209</b> modules, <b>809</b> connections]]></message>
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<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug" culprit="merlin_clock_and_reset_bridge_transform"><![CDATA[After transform: <b>217</b> modules, <b>1037</b> connections]]></message>
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<message level="Debug">Transform: InterconnectConnectionsTagger</message>
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<message level="Debug">Transform: HierarchyTransform</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>26</b> modules, <b>110</b> connections]]></message>
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<message level="Debug" culprit="merlin_mm_transform"><![CDATA[After transform: <b>26</b> modules, <b>110</b> connections]]></message>
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<message level="Debug">Transform: InterruptMapperTransform</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug" culprit="merlin_interrupt_mapper_transform"><![CDATA[After transform: <b>27</b> modules, <b>113</b> connections]]></message>
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<message level="Debug">Transform: InterruptSyncTransform</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug" culprit="merlin_interrupt_sync_transform"><![CDATA[After transform: <b>28</b> modules, <b>119</b> connections]]></message>
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<message level="Debug">Transform: InterruptFanoutTransform</message>
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<message level="Debug">Transform: AvalonStreamingTransform</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
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<message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.000s</message>
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<message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
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<message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.004s</message>
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<message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.017s/0.022s</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Info" culprit="avalon_st_adapter_001">Inserting timing_adapter: timing_adapter_0</message>
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<message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.000s</message>
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<message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
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<message level="Debug" culprit="avalon_st_adapter_001.timing_adapter_0">Timing: ELA:1/0.004s</message>
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<message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.012s/0.021s</message>
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<message
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level="Debug"
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culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>30</b> modules, <b>126</b> connections]]></message>
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<message level="Debug">Transform: ResetAdaptation</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug" culprit="reset_adaptation_transform"><![CDATA[After transform: <b>39</b> modules, <b>154</b> connections]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altpll</b> "<b>submodules/q_sys_altpll_shift</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_pio</b> "<b>submodules/q_sys_button_pio</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_onchip_memory2</b> "<b>submodules/q_sys_calibration_ram</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>channel_adapter</b> "<b>submodules/q_sys_channel_adapter_0</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_nios2_gen2</b> "<b>submodules/q_sys_cpu</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_mem_if_ddr3_emif</b> "<b>submodules/q_sys_ddr3_ram</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_uart</b> "<b>submodules/q_sys_debug_uart</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_onchip_memory2</b> "<b>submodules/q_sys_descriptor_memory</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altpll</b> "<b>submodules/q_sys_enet_pll</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_eth_tse</b> "<b>submodules/q_sys_eth_tse</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_timer</b> "<b>submodules/q_sys_frame_timer</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_msgdma</b> "<b>submodules/q_sys_msgdma_rx</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_msgdma</b> "<b>submodules/q_sys_msgdma_tx</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_onchip_flash</b> "<b>submodules/altera_onchip_flash</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_pio</b> "<b>submodules/q_sys_output_pio</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>sensor_recon</b> "<b>submodules/sensor_algo</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_timer</b> "<b>submodules/q_sys_sys_clk_timer</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_sysid_qsys</b> "<b>submodules/q_sys_sysid</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>multiplexer</b> "<b>submodules/q_sys_tx_multiplexer</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>udp_generator</b> "<b>submodules/udp_generator</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_mm_interconnect</b> "<b>submodules/q_sys_mm_interconnect_0</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_mm_interconnect</b> "<b>submodules/q_sys_mm_interconnect_1</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_irq_mapper</b> "<b>submodules/q_sys_irq_mapper</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_irq_clock_crosser</b> "<b>submodules/altera_irq_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_avalon_st_adapter_001</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
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<message level="Debug" culprit="q_sys"><![CDATA["<b>q_sys</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
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<message level="Debug" culprit="q_sys">queue size: 33 starting:altpll "submodules/q_sys_altpll_shift"</message>
|
|
<message level="Debug">set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files</message>
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<message level="Debug">Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --source=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0003_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on</message>
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<message level="Debug">Command took 1.307s</message>
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<message level="Info" culprit="altpll_shift"><![CDATA["<b>q_sys</b>" instantiated <b>altpll</b> "<b>altpll_shift</b>"]]></message>
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<message level="Debug" culprit="q_sys">queue size: 32 starting:altera_avalon_pio "submodules/q_sys_button_pio"</message>
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<message level="Info" culprit="button_pio">Starting RTL generation for module 'q_sys_button_pio'</message>
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<message level="Info" culprit="button_pio"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_button_pio --dir=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen//q_sys_button_pio_component_configuration.pl --do_build_sim=0 ]</message>
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<message level="Info" culprit="button_pio">Done RTL generation for module 'q_sys_button_pio'</message>
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<message level="Info" culprit="button_pio"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_pio</b> "<b>button_pio</b>"]]></message>
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<message level="Debug" culprit="q_sys">queue size: 31 starting:altera_avalon_onchip_memory2 "submodules/q_sys_calibration_ram"</message>
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<message level="Info" culprit="calibration_ram">Starting RTL generation for module 'q_sys_calibration_ram'</message>
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|
<message level="Info" culprit="calibration_ram"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_calibration_ram --dir=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen//q_sys_calibration_ram_component_configuration.pl --do_build_sim=0 ]</message>
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<message level="Info" culprit="calibration_ram">Done RTL generation for module 'q_sys_calibration_ram'</message>
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<message level="Info" culprit="calibration_ram"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>calibration_ram</b>"]]></message>
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<message level="Debug" culprit="q_sys">queue size: 30 starting:channel_adapter "submodules/q_sys_channel_adapter_0"</message>
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<message level="Info" culprit="channel_adapter_0"><![CDATA["<b>q_sys</b>" instantiated <b>channel_adapter</b> "<b>channel_adapter_0</b>"]]></message>
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|
<message level="Debug" culprit="q_sys">queue size: 29 starting:altera_nios2_gen2 "submodules/q_sys_cpu"</message>
|
|
<message level="Progress" culprit="min"></message>
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|
<message level="Progress" culprit="max"></message>
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|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
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|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
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<message level="Debug" culprit="cpu"><![CDATA["<b>cpu</b>" reuses <b>altera_nios2_gen2_unit</b> "<b>submodules/q_sys_cpu_cpu</b>"]]></message>
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<message level="Info" culprit="cpu"><![CDATA["<b>q_sys</b>" instantiated <b>altera_nios2_gen2</b> "<b>cpu</b>"]]></message>
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|
<message level="Debug" culprit="q_sys">queue size: 233 starting:altera_nios2_gen2_unit "submodules/q_sys_cpu_cpu"</message>
|
|
<message level="Info" culprit="cpu">Starting RTL generation for module 'q_sys_cpu_cpu'</message>
|
|
<message level="Info" culprit="cpu"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=q_sys_cpu_cpu --dir=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen/ --quartus_bindir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/ --verilog --config=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen//q_sys_cpu_cpu_processor_configuration.pl --do_build_sim=0 ]</message>
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<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Starting Nios II generation</message>
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|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Elaborating CPU configuration settings</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Creating all objects for CPU</message>
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|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Testbench</message>
|
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<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Instruction decoding</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Instruction fields</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Instruction decodes</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Signals for RTL simulation waveforms</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Instruction controls</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Pipeline frontend</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Pipeline backend</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Generating RTL from CPU objects</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Creating plain-text RTL</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Done Nios II generation</message>
|
|
<message level="Info" culprit="cpu">Done RTL generation for module 'q_sys_cpu_cpu'</message>
|
|
<message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 29 starting:altera_mem_if_ddr3_emif "submodules/q_sys_ddr3_ram"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>14</b> modules, <b>31</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_pll</b> "<b>submodules/q_sys_ddr3_ram_pll0</b>"]]></message>
|
|
<message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_phy_core</b> "<b>submodules/q_sys_ddr3_ram_p0</b>"]]></message>
|
|
<message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_afi_mux</b> "<b>submodules/afi_mux_ddr3_ddrx</b>"]]></message>
|
|
<message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_qseq</b> "<b>submodules/q_sys_ddr3_ram_s0</b>"]]></message>
|
|
<message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_nextgen_ddr3_controller</b> "<b>submodules/q_sys_ddr3_ram_c0</b>"]]></message>
|
|
<message level="Info" culprit="ddr3_ram"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>ddr3_ram</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 232 starting:altera_mem_if_ddr3_pll "submodules/q_sys_ddr3_ram_pll0"</message>
|
|
<message level="Info" culprit="pll0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 231 starting:altera_mem_if_ddr3_phy_core "submodules/q_sys_ddr3_ram_p0"</message>
|
|
<message level="Info" culprit="p0">Generating clock pair generator</message>
|
|
<message level="Info" culprit="p0">Generating altgpio</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0">*****************************</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0">Remember to run the q_sys_ddr3_ram_p0_pin_assignments.tcl</message>
|
|
<message level="Info" culprit="p0">script after running Synthesis and before Fitting.</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0">*****************************</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 230 starting:altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx"</message>
|
|
<message level="Info" culprit="m0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 229 starting:altera_mem_if_ddr3_qseq "submodules/q_sys_ddr3_ram_s0"</message>
|
|
<message level="Info" culprit="s0">Generating Qsys sequencer system</message>
|
|
<message level="Info" culprit="s0">QSYS sequencer system generated successfully</message>
|
|
<message level="Info" culprit="s0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 228 starting:altera_mem_if_nextgen_ddr3_controller "submodules/q_sys_ddr3_ram_c0"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>8</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>submodules/alt_mem_if_nextgen_ddr3_controller_core</b>"]]></message>
|
|
<message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>alt_mem_ddrx_mm_st_converter</b> "<b>submodules/alt_mem_ddrx_mm_st_converter</b>"]]></message>
|
|
<message level="Info" culprit="c0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller</b> "<b>c0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 6 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core"</message>
|
|
<message level="Info" culprit="ng0"><![CDATA["<b>c0</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>ng0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 5 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter"</message>
|
|
<message level="Info" culprit="a0"><![CDATA["<b>c0</b>" instantiated <b>alt_mem_ddrx_mm_st_converter</b> "<b>a0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 33 starting:altera_avalon_uart "submodules/q_sys_debug_uart"</message>
|
|
<message level="Info" culprit="debug_uart">Starting RTL generation for module 'q_sys_debug_uart'</message>
|
|
<message level="Info" culprit="debug_uart"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=q_sys_debug_uart --dir=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen//q_sys_debug_uart_component_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="debug_uart">Done RTL generation for module 'q_sys_debug_uart'</message>
|
|
<message level="Info" culprit="debug_uart"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_uart</b> "<b>debug_uart</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 32 starting:altera_avalon_onchip_memory2 "submodules/q_sys_descriptor_memory"</message>
|
|
<message level="Info" culprit="descriptor_memory">Starting RTL generation for module 'q_sys_descriptor_memory'</message>
|
|
<message level="Info" culprit="descriptor_memory"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_descriptor_memory --dir=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen//q_sys_descriptor_memory_component_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="descriptor_memory">Done RTL generation for module 'q_sys_descriptor_memory'</message>
|
|
<message level="Info" culprit="descriptor_memory"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>descriptor_memory</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 31 starting:altpll "submodules/q_sys_enet_pll"</message>
|
|
<message level="Debug">set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files</message>
|
|
<message level="Debug">Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --source=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0010_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on</message>
|
|
<message level="Debug">Command took 1.135s</message>
|
|
<message level="Info" culprit="enet_pll"><![CDATA["<b>q_sys</b>" instantiated <b>altpll</b> "<b>enet_pll</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 30 starting:altera_eth_tse "submodules/q_sys_eth_tse"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>14</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_eth_tse_mac</b> "<b>submodules/altera_eth_tse_mac</b>"]]></message>
|
|
<message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
|
|
<message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
|
|
<message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
|
|
<message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
|
|
<message level="Info" culprit="eth_tse"><![CDATA["<b>q_sys</b>" instantiated <b>altera_eth_tse</b> "<b>eth_tse</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 229 starting:altera_eth_tse_mac "submodules/altera_eth_tse_mac"</message>
|
|
<message level="Info" culprit="i_tse_mac"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_eth_tse_mac</b> "<b>i_tse_mac</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 228 starting:altera_gpio_lite "submodules/altera_gpio_lite"</message>
|
|
<message level="Info" culprit="rgmii_in4_0"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_gpio_lite</b> "<b>rgmii_in4_0</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 34 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash"</message>
|
|
<message level="Info" culprit="soft_asmiblock_instance_name">"Generating: soft_asmiblock_instance_name"</message>
|
|
<message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_soft_asmiblock_instance_name</b>"]]></message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name">"Generating: asmi_parallel_instance_name"</message>
|
|
<message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_asmi_parallel_instance_name</b>"]]></message>
|
|
<message level="Info" culprit="epcq_controller_instance_name">"Generating: epcq_controller_instance_name"</message>
|
|
<message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_epcq_controller_instance_name</b>"]]></message>
|
|
<message level="Info" culprit="ext_flash"><![CDATA["<b>q_sys</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>ext_flash</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_soft_asmiblock_instance_name"</message>
|
|
<message level="Debug" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" reuses <b>soft_asmiblock</b> "<b>submodules/soft_asmiblock</b>"]]></message>
|
|
<message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock"</message>
|
|
<message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" instantiated <b>soft_asmiblock</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_asmi_parallel_instance_name"</message>
|
|
<message level="Debug" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" reuses <b>altera_asmi_parallel</b> "<b>submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</b>"]]></message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>asmi_parallel_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name"</message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name">generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" instantiated <b>altera_asmi_parallel</b> "<b>asmi_parallel_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_epcq_controller_instance_name"</message>
|
|
<message level="Debug" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" reuses <b>altera_epcq_controller_core</b> "<b>submodules/altera_epcq_controller_arb</b>"]]></message>
|
|
<message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>epcq_controller_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb"</message>
|
|
<message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" instantiated <b>altera_epcq_controller_core</b> "<b>epcq_controller_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 36 starting:altera_avalon_timer "submodules/q_sys_frame_timer"</message>
|
|
<message level="Info" culprit="frame_timer">Starting RTL generation for module 'q_sys_frame_timer'</message>
|
|
<message level="Info" culprit="frame_timer"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_frame_timer --dir=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen//q_sys_frame_timer_component_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="frame_timer">Done RTL generation for module 'q_sys_frame_timer'</message>
|
|
<message level="Info" culprit="frame_timer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_timer</b> "<b>frame_timer</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 35 starting:altera_msgdma "submodules/q_sys_msgdma_rx"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>11</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>modular_sgdma_dispatcher</b> "<b>submodules/dispatcher</b>"]]></message>
|
|
<message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>altera_msgdma_prefetcher</b> "<b>submodules/altera_msgdma_prefetcher</b>"]]></message>
|
|
<message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>dma_write_master</b> "<b>submodules/write_master</b>"]]></message>
|
|
<message level="Info" culprit="msgdma_rx"><![CDATA["<b>q_sys</b>" instantiated <b>altera_msgdma</b> "<b>msgdma_rx</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher"</message>
|
|
<message level="Info" culprit="dispatcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>modular_sgdma_dispatcher</b> "<b>dispatcher_internal</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"</message>
|
|
<message level="Info" culprit="prefetcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>altera_msgdma_prefetcher</b> "<b>prefetcher_internal</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 222 starting:dma_write_master "submodules/write_master"</message>
|
|
<message level="Info" culprit="write_mstr_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>dma_write_master</b> "<b>write_mstr_internal</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 37 starting:altera_msgdma "submodules/q_sys_msgdma_tx"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>11</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>modular_sgdma_dispatcher</b> "<b>submodules/dispatcher</b>"]]></message>
|
|
<message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>altera_msgdma_prefetcher</b> "<b>submodules/altera_msgdma_prefetcher</b>"]]></message>
|
|
<message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>dma_read_master</b> "<b>submodules/read_master</b>"]]></message>
|
|
<message level="Info" culprit="msgdma_tx"><![CDATA["<b>q_sys</b>" instantiated <b>altera_msgdma</b> "<b>msgdma_tx</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher"</message>
|
|
<message level="Info" culprit="dispatcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>modular_sgdma_dispatcher</b> "<b>dispatcher_internal</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"</message>
|
|
<message level="Info" culprit="prefetcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>altera_msgdma_prefetcher</b> "<b>prefetcher_internal</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 219 starting:dma_read_master "submodules/read_master"</message>
|
|
<message level="Info" culprit="read_mstr_internal"><![CDATA["<b>msgdma_tx</b>" instantiated <b>dma_read_master</b> "<b>read_mstr_internal</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 39 starting:altera_onchip_flash "submodules/altera_onchip_flash"</message>
|
|
<message level="Info" culprit="onchip_flash">Generating top-level entity altera_onchip_flash</message>
|
|
<message level="Info" culprit="onchip_flash"><![CDATA["<b>q_sys</b>" instantiated <b>altera_onchip_flash</b> "<b>onchip_flash</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 38 starting:altera_avalon_pio "submodules/q_sys_output_pio"</message>
|
|
<message level="Info" culprit="output_pio">Starting RTL generation for module 'q_sys_output_pio'</message>
|
|
<message level="Info" culprit="output_pio"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_output_pio --dir=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen//q_sys_output_pio_component_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="output_pio">Done RTL generation for module 'q_sys_output_pio'</message>
|
|
<message level="Info" culprit="output_pio"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_pio</b> "<b>output_pio</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 37 starting:sensor_recon "submodules/sensor_algo"</message>
|
|
<message level="Info" culprit="sensor_interface"><![CDATA["<b>q_sys</b>" instantiated <b>sensor_recon</b> "<b>sensor_interface</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 36 starting:altera_avalon_timer "submodules/q_sys_sys_clk_timer"</message>
|
|
<message level="Info" culprit="sys_clk_timer">Starting RTL generation for module 'q_sys_sys_clk_timer'</message>
|
|
<message level="Info" culprit="sys_clk_timer"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_sys_clk_timer --dir=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen//q_sys_sys_clk_timer_component_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="sys_clk_timer">Done RTL generation for module 'q_sys_sys_clk_timer'</message>
|
|
<message level="Info" culprit="sys_clk_timer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_timer</b> "<b>sys_clk_timer</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 35 starting:altera_avalon_sysid_qsys "submodules/q_sys_sysid"</message>
|
|
<message level="Info" culprit="sysid"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_sysid_qsys</b> "<b>sysid</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 34 starting:multiplexer "submodules/q_sys_tx_multiplexer"</message>
|
|
<message level="Info" culprit="tx_multiplexer"><![CDATA["<b>q_sys</b>" instantiated <b>multiplexer</b> "<b>tx_multiplexer</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 33 starting:udp_generator "submodules/udp_generator"</message>
|
|
<message level="Info" culprit="udp_generator"><![CDATA["<b>q_sys</b>" instantiated <b>udp_generator</b> "<b>udp_generator</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 32 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_0"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>4</b> modules, <b>6</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>4</b> modules, <b>6</b> connections]]></message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Info" culprit="mm_interconnect_0"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
|
|
<message
|
|
level="Info"
|
|
culprit="sensor_interface_calibration_ram_interface_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>sensor_interface_calibration_ram_interface_translator</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
|
|
<message level="Info" culprit="calibration_ram_s2_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>calibration_ram_s2_translator</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 33 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_1"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.007s/0.008s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_001">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.006s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_002">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_002.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_002.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_002.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_002">Timing: COM:3/0.005s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_003">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_003.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_003.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_003.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_003">Timing: COM:3/0.007s/0.009s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_004">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_004.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_004.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_004.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_004">Timing: COM:3/0.005s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_005">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_005.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_005.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_005.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_005">Timing: COM:3/0.005s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_006">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_006.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_006.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_006.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_006">Timing: COM:3/0.006s/0.007s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_007">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_007.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_007.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_007.error_adapter_0">Timing: ELA:1/0.004s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_007">Timing: COM:3/0.006s/0.007s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_008">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_008.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_008.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_008.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_008">Timing: COM:3/0.006s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_009">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_009.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_009.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_009.error_adapter_0">Timing: ELA:1/0.004s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_009">Timing: COM:3/0.006s/0.007s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_010">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_010.clk_bridge_0">Timing: ELA:1/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_010.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_010.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_010">Timing: COM:3/0.020s/0.048s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_011">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_011.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_011.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_011.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_011">Timing: COM:3/0.005s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_012">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_012.clk_bridge_0">Timing: ELA:1/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_012.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_012.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_012">Timing: COM:3/0.006s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_013">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_013.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_013.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_013.error_adapter_0">Timing: ELA:1/0.004s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_013">Timing: COM:3/0.006s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_014">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_014.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_014.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_014.error_adapter_0">Timing: ELA:1/0.002s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_014">Timing: COM:3/0.006s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_015">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_015.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_015.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_015.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_015">Timing: COM:3/0.005s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_016">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_016.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_016.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_016.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_016">Timing: COM:3/0.006s/0.007s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_017">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_017.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_017.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_017.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_017">Timing: COM:3/0.006s/0.007s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_018">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_018.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_018.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_018.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_018">Timing: COM:3/0.006s/0.007s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_019">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_019.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_019.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_019.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_019">Timing: COM:3/0.006s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_020">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_020.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_020.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_020.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_020">Timing: COM:3/0.006s/0.006s</message>
|
|
<message
|
|
level="Debug"
|
|
culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>218</b> modules, <b>742</b> connections]]></message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_008</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_022</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_028</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_001</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_014</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_010</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_010</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_014</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020</b>"]]></message>
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<message level="Info" culprit="mm_interconnect_1"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"]]></message>
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<message level="Debug" culprit="q_sys">queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
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|
<message
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|
level="Info"
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|
culprit="sensor_interface_calibration_ram_interface_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>sensor_interface_calibration_ram_interface_translator</b>"]]></message>
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<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
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|
<message level="Debug" culprit="q_sys">queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
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|
<message level="Info" culprit="calibration_ram_s2_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>calibration_ram_s2_translator</b>"]]></message>
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<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
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|
<message level="Debug" culprit="q_sys">queue size: 187 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
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|
<message level="Info" culprit="cpu_data_master_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>cpu_data_master_agent</b>"]]></message>
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<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
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|
<message level="Debug" culprit="q_sys">queue size: 179 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
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|
<message level="Info" culprit="ddr3_ram_avl_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>ddr3_ram_avl_agent</b>"]]></message>
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<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
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|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 178 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
|
|
<message level="Info" culprit="ddr3_ram_avl_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>ddr3_ram_avl_agent_rsp_fifo</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 134 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router"</message>
|
|
<message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 133 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_001"</message>
|
|
<message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 132 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002"</message>
|
|
<message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 130 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"</message>
|
|
<message level="Info" culprit="router_004"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_004</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 126 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_008"</message>
|
|
<message level="Info" culprit="router_008"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_008</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 125 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"</message>
|
|
<message level="Info" culprit="router_009"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_009</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 124 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"</message>
|
|
<message level="Info" culprit="router_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_010</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 112 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_022"</message>
|
|
<message level="Info" culprit="router_022"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_022</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 106 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_028"</message>
|
|
<message level="Info" culprit="router_028"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_028</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 105 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"</message>
|
|
<message level="Info" culprit="cpu_data_master_limiter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>cpu_data_master_limiter</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 103 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
|
|
<message level="Info" culprit="ext_flash_avl_mem_burst_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>ext_flash_avl_mem_burst_adapter</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 101 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux"</message>
|
|
<message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 100 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_001"</message>
|
|
<message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 99 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"</message>
|
|
<message level="Info" culprit="cmd_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_002</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 93 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux"</message>
|
|
<message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 92 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"</message>
|
|
<message level="Info" culprit="cmd_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_001</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 91 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"</message>
|
|
<message level="Info" culprit="cmd_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_002</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 79 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_014"</message>
|
|
<message level="Info" culprit="cmd_mux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_014</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 72 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux"</message>
|
|
<message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 71 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_001"</message>
|
|
<message level="Info" culprit="rsp_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_001</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 70 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_002"</message>
|
|
<message level="Info" culprit="rsp_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_002</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 62 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010"</message>
|
|
<message level="Info" culprit="rsp_demux_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_010</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 58 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_014"</message>
|
|
<message level="Info" culprit="rsp_demux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_014</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 51 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux"</message>
|
|
<message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 50 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_001"</message>
|
|
<message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 49 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"</message>
|
|
<message level="Info" culprit="rsp_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_002</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 43 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
|
|
<message level="Info" culprit="calibration_ram_s1_rsp_width_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>calibration_ram_s1_rsp_width_adapter</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 41 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"</message>
|
|
<message level="Info" culprit="crosser"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_handshake_clock_crosser</b> "<b>crosser</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 27 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0</b>"]]></message>
|
|
<message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"</message>
|
|
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 8 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_020"><![CDATA["<b>avalon_st_adapter_020</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0</b>"]]></message>
|
|
<message level="Info" culprit="avalon_st_adapter_020"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_020</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0"</message>
|
|
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_020</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 242 starting:altera_irq_mapper "submodules/q_sys_irq_mapper"</message>
|
|
<message level="Info" culprit="irq_mapper"><![CDATA["<b>q_sys</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 241 starting:altera_irq_clock_crosser "submodules/altera_irq_clock_crosser"</message>
|
|
<message level="Info" culprit="irq_synchronizer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_irq_clock_crosser</b> "<b>irq_synchronizer</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_avalon_st_adapter_error_adapter_0</b>"]]></message>
|
|
<message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 8 starting:error_adapter "submodules/q_sys_avalon_st_adapter_error_adapter_0"</message>
|
|
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter_001"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_001"><![CDATA["<b>avalon_st_adapter_001</b>" reuses <b>timing_adapter</b> "<b>submodules/q_sys_avalon_st_adapter_001_timing_adapter_0</b>"]]></message>
|
|
<message level="Info" culprit="avalon_st_adapter_001"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_001</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 7 starting:timing_adapter "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0"</message>
|
|
<message level="Info" culprit="timing_adapter_0"><![CDATA["<b>avalon_st_adapter_001</b>" instantiated <b>timing_adapter</b> "<b>timing_adapter_0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 240 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
|
|
<message level="Info" culprit="rst_controller"><![CDATA["<b>q_sys</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altpll:19.1:AUTO_DEVICE_FAMILY=MAX 10,AUTO_INCLK_INTERFACE_CLOCK_RATE=50000000,AVALON_USE_SEPARATE_SYSCLK=NO,BANDWIDTH=,BANDWIDTH_TYPE=AUTO,CLK0_DIVIDE_BY=1,CLK0_DUTY_CYCLE=50,CLK0_MULTIPLY_BY=5,CLK0_PHASE_SHIFT=0,CLK1_DIVIDE_BY=2,CLK1_DUTY_CYCLE=50,CLK1_MULTIPLY_BY=1,CLK1_PHASE_SHIFT=15000,CLK2_DIVIDE_BY=20,CLK2_DUTY_CYCLE=50,CLK2_MULTIPLY_BY=1,CLK2_PHASE_SHIFT=0,CLK3_DIVIDE_BY=,CLK3_DUTY_CYCLE=,CLK3_MULTIPLY_BY=,CLK3_PHASE_SHIFT=,CLK4_DIVIDE_BY=,CLK4_DUTY_CYCLE=,CLK4_MULTIPLY_BY=,CLK4_PHASE_SHIFT=,CLK5_DIVIDE_BY=,CLK5_DUTY_CYCLE=,CLK5_MULTIPLY_BY=,CLK5_PHASE_SHIFT=,CLK6_DIVIDE_BY=,CLK6_DUTY_CYCLE=,CLK6_MULTIPLY_BY=,CLK6_PHASE_SHIFT=,CLK7_DIVIDE_BY=,CLK7_DUTY_CYCLE=,CLK7_MULTIPLY_BY=,CLK7_PHASE_SHIFT=,CLK8_DIVIDE_BY=,CLK8_DUTY_CYCLE=,CLK8_MULTIPLY_BY=,CLK8_PHASE_SHIFT=,CLK9_DIVIDE_BY=,CLK9_DUTY_CYCLE=,CLK9_MULTIPLY_BY=,CLK9_PHASE_SHIFT=,COMPENSATE_CLOCK=CLK0,DOWN_SPREAD=,DPA_DIVIDER=,DPA_DIVIDE_BY=,DPA_MULTIPLY_BY=,ENABLE_SWITCH_OVER_COUNTER=,EXTCLK0_DIVIDE_BY=,EXTCLK0_DUTY_CYCLE=,EXTCLK0_MULTIPLY_BY=,EXTCLK0_PHASE_SHIFT=,EXTCLK1_DIVIDE_BY=,EXTCLK1_DUTY_CYCLE=,EXTCLK1_MULTIPLY_BY=,EXTCLK1_PHASE_SHIFT=,EXTCLK2_DIVIDE_BY=,EXTCLK2_DUTY_CYCLE=,EXTCLK2_MULTIPLY_BY=,EXTCLK2_PHASE_SHIFT=,EXTCLK3_DIVIDE_BY=,EXTCLK3_DUTY_CYCLE=,EXTCLK3_MULTIPLY_BY=,EXTCLK3_PHASE_SHIFT=,FEEDBACK_SOURCE=,GATE_LOCK_COUNTER=,GATE_LOCK_SIGNAL=,HIDDEN_CONSTANTS=CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED,HIDDEN_CUSTOM_ELABORATION=altpll_avalon_elaboration,HIDDEN_CUSTOM_POST_EDIT=altpll_avalon_post_edit,HIDDEN_IF_PORTS=IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0},HIDDEN_IS_FIRST_EDIT=0,HIDDEN_IS_NUMERIC=IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1,HIDDEN_MF_PORTS=MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1,HIDDEN_PRIVATES=PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0,HIDDEN_USED_PORTS=UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used,INCLK0_INPUT_FREQUENCY=20000,INCLK1_INPUT_FREQUENCY=,INTENDED_DEVICE_FAMILY=MAX 10,INVALID_LOCK_MULTIPLIER=,LOCK_HIGH=,LOCK_LOW=,OPERATION_MODE=NORMAL,PLL_TYPE=AUTO,PORT_ACTIVECLOCK=PORT_UNUSED,PORT_ARESET=PORT_USED,PORT_CLKBAD0=PORT_UNUSED,PORT_CLKBAD1=PORT_UNUSED,PORT_CLKLOSS=PORT_UNUSED,PORT_CLKSWITCH=PORT_UNUSED,PORT_CONFIGUPDATE=PORT_UNUSED,PORT_ENABLE0=,PORT_ENABLE1=,PORT_FBIN=PORT_UNUSED,PORT_FBOUT=,PORT_INCLK0=PORT_USED,PORT_INCLK1=PORT_UNUSED,PORT_LOCKED=PORT_USED,PORT_PFDENA=PORT_UNUSED,PORT_PHASECOUNTERSELECT=PORT_UNUSED,PORT_PHASEDONE=PORT_UNUSED,PORT_PHASESTEP=PORT_UNUSED,PORT_PHASEUPDOWN=PORT_UNUSED,PORT_PLLENA=PORT_UNUSED,PORT_SCANACLR=PORT_UNUSED,PORT_SCANCLK=PORT_UNUSED,PORT_SCANCLKENA=PORT_UNUSED,PORT_SCANDATA=PORT_UNUSED,PORT_SCANDATAOUT=PORT_UNUSED,PORT_SCANDONE=PORT_UNUSED,PORT_SCANREAD=PORT_UNUSED,PORT_SCANWRITE=PORT_UNUSED,PORT_SCLKOUT0=,PORT_SCLKOUT1=,PORT_VCOOVERRANGE=,PORT_VCOUNDERRANGE=,PORT_clk0=PORT_USED,PORT_clk1=PORT_UNUSED,PORT_clk2=PORT_UNUSED,PORT_clk3=PORT_UNUSED,PORT_clk4=PORT_UNUSED,PORT_clk5=PORT_UNUSED,PORT_clk6=,PORT_clk7=,PORT_clk8=,PORT_clk9=,PORT_clkena0=PORT_UNUSED,PORT_clkena1=PORT_UNUSED,PORT_clkena2=PORT_UNUSED,PORT_clkena3=PORT_UNUSED,PORT_clkena4=PORT_UNUSED,PORT_clkena5=PORT_UNUSED,PORT_extclk0=PORT_UNUSED,PORT_extclk1=PORT_UNUSED,PORT_extclk2=PORT_UNUSED,PORT_extclk3=PORT_UNUSED,PORT_extclkena0=,PORT_extclkena1=,PORT_extclkena2=,PORT_extclkena3=,PRIMARY_CLOCK=,QUALIFY_CONF_DONE=,SCAN_CHAIN=,SCAN_CHAIN_MIF_FILE=,SCLKOUT0_PHASE_SHIFT=,SCLKOUT1_PHASE_SHIFT=,SELF_RESET_ON_GATED_LOSS_LOCK=,SELF_RESET_ON_LOSS_LOCK=,SKIP_VCO=,SPREAD_FREQUENCY=,SWITCH_OVER_COUNTER=,SWITCH_OVER_ON_GATED_LOCK=,SWITCH_OVER_ON_LOSSCLK=,SWITCH_OVER_TYPE=,USING_FBMIMICBIDIR_PORT=,VALID_LOCK_MULTIPLIER=,VCO_DIVIDE_BY=,VCO_FREQUENCY_CONTROL=,VCO_MULTIPLY_BY=,VCO_PHASE_SHIFT_STEP=,WIDTH_CLOCK=5,WIDTH_PHASECOUNTERSELECT="
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instancePathKey="q_sys:.:altpll_shift"
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kind="altpll"
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version="19.1"
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name="q_sys_altpll_shift">
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<parameter name="CLK3_PHASE_SHIFT" value="" />
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<parameter name="PORT_LOCKED" value="PORT_USED" />
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<parameter name="CLK2_PHASE_SHIFT" value="0" />
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<parameter name="CLK4_PHASE_SHIFT" value="" />
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<parameter name="CLK5_DUTY_CYCLE" value="" />
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<parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
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<parameter name="CLK1_PHASE_SHIFT" value="15000" />
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<parameter name="CLK5_PHASE_SHIFT" value="" />
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<parameter name="HIDDEN_CUSTOM_ELABORATION" value="altpll_avalon_elaboration" />
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<parameter name="CLK8_DUTY_CYCLE" value="" />
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<parameter name="CLK0_DIVIDE_BY" value="1" />
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<parameter name="CLK7_PHASE_SHIFT" value="" />
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<parameter name="CLK0_PHASE_SHIFT" value="0" />
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<parameter name="CLK6_PHASE_SHIFT" value="" />
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<parameter name="CLK8_PHASE_SHIFT" value="" />
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<parameter name="PORT_clk8" value="" />
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<parameter name="INVALID_LOCK_MULTIPLIER" value="" />
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<parameter name="PORT_clk9" value="" />
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<parameter name="PORT_clk6" value="" />
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<parameter name="PORT_clk7" value="" />
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<parameter name="EXTCLK2_DIVIDE_BY" value="" />
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<parameter name="PORT_clk4" value="PORT_UNUSED" />
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<parameter name="PORT_clk5" value="PORT_UNUSED" />
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<parameter name="PORT_clk2" value="PORT_UNUSED" />
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<parameter name="EXTCLK3_DUTY_CYCLE" value="" />
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<parameter name="PORT_clk3" value="PORT_UNUSED" />
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<parameter name="PORT_clk0" value="PORT_USED" />
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<parameter name="PORT_clk1" value="PORT_UNUSED" />
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<parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
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<parameter name="PORT_extclkena0" value="" />
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<parameter name="SKIP_VCO" value="" />
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<parameter name="PORT_extclkena1" value="" />
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<parameter name="PORT_extclkena2" value="" />
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<parameter name="CLK2_DUTY_CYCLE" value="50" />
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<parameter name="PORT_extclkena3" value="" />
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<parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
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<parameter name="GATE_LOCK_SIGNAL" value="" />
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<parameter name="CLK7_DIVIDE_BY" value="" />
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<parameter name="CLK8_DIVIDE_BY" value="" />
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<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
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<parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
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<parameter name="PORT_ENABLE1" value="" />
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<parameter name="PORT_VCOUNDERRANGE" value="" />
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<parameter name="GATE_LOCK_COUNTER" value="" />
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<parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
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<parameter name="SWITCH_OVER_TYPE" value="" />
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<parameter name="PORT_ENABLE0" value="" />
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<parameter name="EXTCLK3_DIVIDE_BY" value="" />
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<parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
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<parameter name="CLK1_DIVIDE_BY" value="2" />
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<parameter name="CLK9_DIVIDE_BY" value="" />
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<parameter name="FEEDBACK_SOURCE" value="" />
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<parameter name="CLK1_DUTY_CYCLE" value="50" />
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<parameter name="BANDWIDTH_TYPE" value="AUTO" />
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<parameter name="SPREAD_FREQUENCY" value="" />
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<parameter name="PORT_PLLENA" value="PORT_UNUSED" />
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<parameter name="LOCK_HIGH" value="" />
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<parameter
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name="HIDDEN_USED_PORTS"
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value="UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used" />
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<parameter name="EXTCLK1_DIVIDE_BY" value="" />
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<parameter name="DOWN_SPREAD" value="" />
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<parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
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<parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
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<parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
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<parameter name="PORT_FBOUT" value="" />
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<parameter name="VCO_FREQUENCY_CONTROL" value="" />
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<parameter
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name="HIDDEN_IF_PORTS"
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value="IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}" />
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<parameter
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name="HIDDEN_MF_PORTS"
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value="MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1" />
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<parameter name="CLK9_PHASE_SHIFT" value="" />
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<parameter name="CLK6_DIVIDE_BY" value="" />
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<parameter name="CLK3_DIVIDE_BY" value="" />
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<parameter name="EXTCLK0_MULTIPLY_BY" value="" />
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<parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
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<parameter name="BANDWIDTH" value="" />
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<parameter name="CLK0_DUTY_CYCLE" value="50" />
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<parameter name="WIDTH_CLOCK" value="5" />
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<parameter name="EXTCLK1_MULTIPLY_BY" value="" />
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<parameter name="VCO_PHASE_SHIFT_STEP" value="" />
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<parameter name="PLL_TYPE" value="AUTO" />
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<parameter name="EXTCLK2_MULTIPLY_BY" value="" />
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<parameter name="EXTCLK3_MULTIPLY_BY" value="" />
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<parameter name="CLK4_DIVIDE_BY" value="" />
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<parameter name="PORT_FBIN" value="PORT_UNUSED" />
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<parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
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<parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
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<parameter name="PORT_VCOOVERRANGE" value="" />
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<parameter name="DPA_DIVIDE_BY" value="" />
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<parameter
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name="HIDDEN_PRIVATES"
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value="PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0" />
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<parameter name="VCO_DIVIDE_BY" value="" />
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<parameter name="CLK3_DUTY_CYCLE" value="" />
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<parameter name="SCAN_CHAIN" value="" />
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<parameter name="LOCK_LOW" value="" />
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<parameter name="CLK0_MULTIPLY_BY" value="5" />
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<parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
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<parameter name="CLK1_MULTIPLY_BY" value="1" />
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<parameter name="PORT_SCLKOUT1" value="" />
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<parameter
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name="HIDDEN_IS_NUMERIC"
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value="IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1" />
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<parameter name="CLK3_MULTIPLY_BY" value="" />
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<parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
|
|
<parameter name="CLK2_MULTIPLY_BY" value="1" />
|
|
<parameter name="CLK4_MULTIPLY_BY" value="" />
|
|
<parameter name="PORT_SCLKOUT0" value="" />
|
|
<parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
|
|
<parameter name="CLK4_DUTY_CYCLE" value="" />
|
|
<parameter name="PORT_clkena0" value="PORT_UNUSED" />
|
|
<parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
|
|
<parameter name="PORT_clkena1" value="PORT_UNUSED" />
|
|
<parameter name="PORT_clkena2" value="PORT_UNUSED" />
|
|
<parameter name="PORT_PFDENA" value="PORT_UNUSED" />
|
|
<parameter name="PORT_clkena3" value="PORT_UNUSED" />
|
|
<parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
|
|
<parameter name="CLK6_MULTIPLY_BY" value="" />
|
|
<parameter name="EXTCLK0_DIVIDE_BY" value="" />
|
|
<parameter name="CLK5_MULTIPLY_BY" value="" />
|
|
<parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="OPERATION_MODE" value="NORMAL" />
|
|
<parameter name="EXTCLK2_DUTY_CYCLE" value="" />
|
|
<parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
|
|
<parameter name="SWITCH_OVER_COUNTER" value="" />
|
|
<parameter name="CLK7_MULTIPLY_BY" value="" />
|
|
<parameter name="PORT_clkena4" value="PORT_UNUSED" />
|
|
<parameter name="PORT_clkena5" value="PORT_UNUSED" />
|
|
<parameter name="SCAN_CHAIN_MIF_FILE" value="" />
|
|
<parameter name="CLK8_MULTIPLY_BY" value="" />
|
|
<parameter name="CLK9_MULTIPLY_BY" value="" />
|
|
<parameter name="EXTCLK2_PHASE_SHIFT" value="" />
|
|
<parameter name="COMPENSATE_CLOCK" value="CLK0" />
|
|
<parameter name="PORT_INCLK0" value="PORT_USED" />
|
|
<parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
|
|
<parameter name="EXTCLK3_PHASE_SHIFT" value="" />
|
|
<parameter name="PORT_INCLK1" value="PORT_UNUSED" />
|
|
<parameter name="CLK5_DIVIDE_BY" value="" />
|
|
<parameter name="CLK9_DUTY_CYCLE" value="" />
|
|
<parameter name="CLK6_DUTY_CYCLE" value="" />
|
|
<parameter name="DPA_DIVIDER" value="" />
|
|
<parameter name="VCO_MULTIPLY_BY" value="" />
|
|
<parameter name="EXTCLK1_PHASE_SHIFT" value="" />
|
|
<parameter
|
|
name="HIDDEN_CONSTANTS"
|
|
value="CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED" />
|
|
<parameter name="EXTCLK0_PHASE_SHIFT" value="" />
|
|
<parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
|
|
<parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
|
|
<parameter name="CLK2_DIVIDE_BY" value="20" />
|
|
<parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
|
|
<parameter name="USING_FBMIMICBIDIR_PORT" value="" />
|
|
<parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
|
|
<parameter name="QUALIFY_CONF_DONE" value="" />
|
|
<parameter name="PORT_ARESET" value="PORT_USED" />
|
|
<parameter name="DPA_MULTIPLY_BY" value="" />
|
|
<parameter name="INCLK1_INPUT_FREQUENCY" value="" />
|
|
<parameter name="CLK7_DUTY_CYCLE" value="" />
|
|
<parameter name="EXTCLK0_DUTY_CYCLE" value="" />
|
|
<parameter name="HIDDEN_CUSTOM_POST_EDIT" value="altpll_avalon_post_edit" />
|
|
<parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
|
|
<parameter name="VALID_LOCK_MULTIPLIER" value="" />
|
|
<parameter name="PRIMARY_CLOCK" value="" />
|
|
<parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
|
|
<parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
|
|
<parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
|
|
<parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
|
|
<parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
|
|
<parameter name="PORT_extclk3" value="PORT_UNUSED" />
|
|
<parameter name="EXTCLK1_DUTY_CYCLE" value="" />
|
|
<parameter name="PORT_extclk0" value="PORT_UNUSED" />
|
|
<parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
|
|
<parameter name="PORT_extclk2" value="PORT_UNUSED" />
|
|
<parameter name="PORT_extclk1" value="PORT_UNUSED" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_altpll_shift.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_altpll/altera_avalon_altpll_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="altpll_shift" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 33 starting:altpll "submodules/q_sys_altpll_shift"</message>
|
|
<message level="Debug">set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files</message>
|
|
<message level="Debug">Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --source=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0003_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on</message>
|
|
<message level="Debug">Command took 1.307s</message>
|
|
<message level="Info" culprit="altpll_shift"><![CDATA["<b>q_sys</b>" instantiated <b>altpll</b> "<b>altpll_shift</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_pio:19.1:bitClearingEdgeCapReg=false,bitModifyingOutReg=false,captureEdge=false,clockRate=50000000,derived_capture=false,derived_do_test_bench_wiring=false,derived_edge_type=NONE,derived_has_in=true,derived_has_irq=false,derived_has_out=false,derived_has_tri=false,derived_irq_type=NONE,direction=Input,edgeType=RISING,generateIRQ=false,irqType=LEVEL,resetValue=0,simDoTestBenchWiring=false,simDrivenValue=0,width=9"
|
|
instancePathKey="q_sys:.:button_pio"
|
|
kind="altera_avalon_pio"
|
|
version="19.1"
|
|
name="q_sys_button_pio">
|
|
<parameter name="derived_do_test_bench_wiring" value="false" />
|
|
<parameter name="generateIRQ" value="false" />
|
|
<parameter name="derived_has_irq" value="false" />
|
|
<parameter name="captureEdge" value="false" />
|
|
<parameter name="clockRate" value="50000000" />
|
|
<parameter name="derived_has_out" value="false" />
|
|
<parameter name="derived_has_in" value="true" />
|
|
<parameter name="resetValue" value="0" />
|
|
<parameter name="derived_has_tri" value="false" />
|
|
<parameter name="derived_capture" value="false" />
|
|
<parameter name="simDoTestBenchWiring" value="false" />
|
|
<parameter name="bitModifyingOutReg" value="false" />
|
|
<parameter name="simDrivenValue" value="0" />
|
|
<parameter name="derived_edge_type" value="NONE" />
|
|
<parameter name="irqType" value="LEVEL" />
|
|
<parameter name="derived_irq_type" value="NONE" />
|
|
<parameter name="edgeType" value="RISING" />
|
|
<parameter name="width" value="9" />
|
|
<parameter name="bitClearingEdgeCapReg" value="false" />
|
|
<parameter name="direction" value="Input" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_button_pio.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="button_pio" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 32 starting:altera_avalon_pio "submodules/q_sys_button_pio"</message>
|
|
<message level="Info" culprit="button_pio">Starting RTL generation for module 'q_sys_button_pio'</message>
|
|
<message level="Info" culprit="button_pio"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_button_pio --dir=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen//q_sys_button_pio_component_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="button_pio">Done RTL generation for module 'q_sys_button_pio'</message>
|
|
<message level="Info" culprit="button_pio"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_pio</b> "<b>button_pio</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=q_sys_calibration_ram,blockType=AUTO,copyInitFile=false,dataWidth=16,dataWidth2=16,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=q_sys_calibration_ram.hex,derived_is_hardcopy=false,derived_set_addr_width=9,derived_set_addr_width2=9,derived_set_data_width=16,derived_set_data_width2=16,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=true,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=640,readDuringWriteMode=DONT_CARE,resetrequest_enabled=false,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true"
|
|
instancePathKey="q_sys:.:calibration_ram"
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|
kind="altera_avalon_onchip_memory2"
|
|
version="19.1"
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|
name="q_sys_calibration_ram">
|
|
<parameter name="derived_singleClockOperation" value="false" />
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|
<parameter name="derived_is_hardcopy" value="false" />
|
|
<parameter
|
|
name="deviceFeatures"
|
|
value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
|
|
<parameter name="autoInitializationFileName" value="q_sys_calibration_ram" />
|
|
<parameter name="derived_gui_ram_block_type" value="Automatic" />
|
|
<parameter name="enPRInitMode" value="false" />
|
|
<parameter name="useShallowMemBlocks" value="false" />
|
|
<parameter name="writable" value="true" />
|
|
<parameter name="dualPort" value="true" />
|
|
<parameter name="derived_set_addr_width2" value="9" />
|
|
<parameter name="dataWidth" value="16" />
|
|
<parameter name="allowInSystemMemoryContentEditor" value="false" />
|
|
<parameter name="derived_set_addr_width" value="9" />
|
|
<parameter name="derived_init_file_name" value="q_sys_calibration_ram.hex" />
|
|
<parameter name="initializationFileName" value="onchip_mem.hex" />
|
|
<parameter name="singleClockOperation" value="false" />
|
|
<parameter name="derived_set_data_width2" value="16" />
|
|
<parameter name="readDuringWriteMode" value="DONT_CARE" />
|
|
<parameter name="blockType" value="AUTO" />
|
|
<parameter name="derived_enableDiffWidth" value="false" />
|
|
<parameter name="useNonDefaultInitFile" value="false" />
|
|
<parameter name="resetrequest_enabled" value="false" />
|
|
<parameter name="simMemInitOnlyFilename" value="0" />
|
|
<parameter name="copyInitFile" value="false" />
|
|
<parameter name="deviceFamily" value="MAX 10" />
|
|
<parameter name="simAllowMRAMContentsFile" value="false" />
|
|
<parameter name="ecc_enabled" value="false" />
|
|
<parameter name="derived_set_data_width" value="16" />
|
|
<parameter name="instanceID" value="NONE" />
|
|
<parameter name="memorySize" value="640" />
|
|
<parameter name="dataWidth2" value="16" />
|
|
<parameter name="enableDiffWidth" value="false" />
|
|
<parameter name="initMemContent" value="false" />
|
|
<parameter name="slave1Latency" value="1" />
|
|
<parameter name="slave2Latency" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_calibration_ram.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="calibration_ram" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 31 starting:altera_avalon_onchip_memory2 "submodules/q_sys_calibration_ram"</message>
|
|
<message level="Info" culprit="calibration_ram">Starting RTL generation for module 'q_sys_calibration_ram'</message>
|
|
<message level="Info" culprit="calibration_ram"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_calibration_ram --dir=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen//q_sys_calibration_ram_component_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="calibration_ram">Done RTL generation for module 'q_sys_calibration_ram'</message>
|
|
<message level="Info" culprit="calibration_ram"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>calibration_ram</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="channel_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=1,inErrorDescriptor=,inErrorWidth=1,inMaxChannel=1,inReadyLatency=0,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,outChannelWidth=0,outMaxChannel=1"
|
|
instancePathKey="q_sys:.:channel_adapter_0"
|
|
kind="channel_adapter"
|
|
version="19.1"
|
|
name="q_sys_channel_adapter_0">
|
|
<parameter name="inErrorWidth" value="1" />
|
|
<parameter name="inUseReady" value="true" />
|
|
<parameter name="inBitsPerSymbol" value="8" />
|
|
<parameter name="inChannelWidth" value="1" />
|
|
<parameter name="inSymbolsPerBeat" value="4" />
|
|
<parameter name="outChannelWidth" value="0" />
|
|
<parameter name="inUseEmptyPort" value="YES" />
|
|
<parameter name="inMaxChannel" value="1" />
|
|
<parameter name="inReadyLatency" value="0" />
|
|
<parameter name="outMaxChannel" value="1" />
|
|
<parameter name="inUseEmpty" value="false" />
|
|
<parameter name="inErrorDescriptor" value="" />
|
|
<parameter name="inUsePackets" value="true" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_channel_adapter_0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="channel_adapter_0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 30 starting:channel_adapter "submodules/q_sys_channel_adapter_0"</message>
|
|
<message level="Info" culprit="channel_adapter_0"><![CDATA["<b>q_sys</b>" instantiated <b>channel_adapter</b> "<b>channel_adapter_0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_nios2_gen2:19.1:AUTO_CLK_CLOCK_DOMAIN=14,AUTO_CLK_RESET_DOMAIN=14,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,bht_ramBlockType=Automatic,breakAbsoluteAddr=406857760,breakOffset=32,breakSlave=cpu.jtag_debug_module,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,customInstSlavesSystemInfo=<info/>,customInstSlavesSystemInfo_nios_a=<info/>,customInstSlavesSystemInfo_nios_b=<info/>,customInstSlavesSystemInfo_nios_c=<info/>,dataAddrWidth=29,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='calibration_ram.s1' start='0x18403400' end='0x18403680' type='altera_avalon_onchip_memory2.s1' /><slave name='frame_timer.s1' start='0x18403C00' end='0x18403C20' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403C20' end='0x18403C40' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403C40' end='0x18403C60' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403C60' end='0x18403C80' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403C80' end='0x18403CA0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x18403CA0' end='0x18403CC0' type='altera_msgdma.prefetcher_csr' /><slave name='udp_generator.csr' start='0x18403CC0' end='0x18403CE0' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403CE0' end='0x18403D00' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403D00' end='0x18403D20' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403D20' end='0x18403D40' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403D40' end='0x18403D50' type='altera_avalon_pio.s1' /><slave name='sensor_interface.csr' start='0x18403D50' end='0x18403D60' type='sensor_recon.csr' /><slave name='onchip_flash.csr' start='0x18403D60' end='0x18403D68' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403D68' end='0x18403D70' type='altera_avalon_sysid_qsys.control_slave' /></address-map>,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_size=0,data_master_paddr_base=0,data_master_paddr_size=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=2,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=MAX 10,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=134218016,exceptionOffset=288,exceptionSlave=ddr3_ram.avl,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_size=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=2048,icache_tagramBlockType=Automatic,impl=Fast,instAddrWidth=29,instSlaveMapParam=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_size=0,instruction_master_paddr_base=0,instruction_master_paddr_size=0,internalIrqMaskSystemInfo=61,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,mul_32_impl=3,mul_64_impl=0,mul_shift_choice=0,multiplierType=mul_fast32,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=335544320,resetOffset=0,resetSlave=ext_flash.avl_mem,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=true,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=true,setting_branchpredictiontype=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=false,setting_disable_tmr_inj=false,setting_disableocitrace=false,setting_dtcm_ecc_present=false,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportHostDebugPort=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=false,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_tmr_output_disable=false,setting_usedesignware=false,shift_rot_impl=0,shifterType=fast_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_size=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_size=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_size=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_size=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_size=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_size=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_size=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_size=0,tmr_enabled=false,tracefilename=,translate_off= "synthesis translate_off" ,translate_on= "synthesis translate_on" ,userDefinedSettings=(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=50000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=1)(altera_nios2_gen2_unit:19.1:bht_ramBlockType=Automatic,breakAbsoluteAddr=406857760,breakOffset=32,breakSlave=cpu.jtag_debug_module,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,cpu_name=cpu,customInstSlavesSystemInfo=<info/>,dataAddrWidth=29,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='calibration_ram.s1' start='0x18403400' end='0x18403680' type='altera_avalon_onchip_memory2.s1' /><slave name='frame_timer.s1' start='0x18403C00' end='0x18403C20' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403C20' end='0x18403C40' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403C40' end='0x18403C60' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403C60' end='0x18403C80' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403C80' end='0x18403CA0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x18403CA0' end='0x18403CC0' type='altera_msgdma.prefetcher_csr' /><slave name='udp_generator.csr' start='0x18403CC0' end='0x18403CE0' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403CE0' end='0x18403D00' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403D00' end='0x18403D20' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403D20' end='0x18403D40' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403D40' end='0x18403D50' type='altera_avalon_pio.s1' /><slave name='sensor_interface.csr' start='0x18403D50' end='0x18403D60' type='sensor_recon.csr' /><slave name='onchip_flash.csr' start='0x18403D60' end='0x18403D68' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403D68' end='0x18403D70' type='altera_avalon_sysid_qsys.control_slave' /></address-map>,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_top=0,data_master_paddr_base=0,data_master_paddr_top=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=2,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=MAX 10,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=134218016,exceptionOffset=288,exceptionSlave=ddr3_ram.avl,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_top=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=2048,icache_tagramBlockType=Automatic,impl=Fast,instAddrWidth=29,instSlaveMapParam=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_top=0,instruction_master_paddr_base=0,instruction_master_paddr_top=0,internalIrqMaskSystemInfo=61,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,multiplierType=mul_fast32,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=335544320,resetOffset=0,resetSlave=ext_flash.avl_mem,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=true,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=true,setting_branchPredictionType=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=false,setting_disableocitrace=false,setting_dtcm_ecc_present=false,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=false,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_usedesignware=false,shifterType=fast_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_top=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_top=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_top=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_top=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_top=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_top=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_top=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_top=0,tmr_enabled=false,tracefilename=,translate_off= "synthesis translate_off" ,translate_on= "synthesis translate_on" ,userDefinedSettings=)(clock:19.1:)(clock:19.1:)(reset:19.1:)"
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instancePathKey="q_sys:.:cpu"
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kind="altera_nios2_gen2"
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version="19.1"
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name="q_sys_cpu">
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<parameter name="mpx_enabled" value="false" />
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<parameter name="ocimem_ramBlockType" value="Automatic" />
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<parameter name="dcache_victim_buf_impl" value="ram" />
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<parameter name="setting_exportPCB" value="false" />
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<parameter name="setting_ic_ecc_present" value="true" />
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<parameter name="dcache_size_derived" value="2048" />
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<parameter name="mmu_udtlbNumEntries" value="6" />
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<parameter
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name="deviceFeaturesSystemInfo"
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value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
|
|
<parameter name="bht_ramBlockType" value="Automatic" />
|
|
<parameter name="mmu_TLBMissExcSlave" value="" />
|
|
<parameter name="impl" value="Fast" />
|
|
<parameter name="setting_branchpredictiontype" value="Dynamic" />
|
|
<parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
|
|
<parameter name="breakOffset" value="32" />
|
|
<parameter name="setting_activateTrace" value="true" />
|
|
<parameter name="debug_offchiptrace" value="false" />
|
|
<parameter name="setting_avalonDebugPortPresent" value="false" />
|
|
<parameter name="dcache_numTCDM" value="0" />
|
|
<parameter name="setting_tmr_output_disable" value="false" />
|
|
<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
|
|
<parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
|
|
<parameter name="debug_debugReqSignals" value="false" />
|
|
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
|
|
<parameter name="instruction_master_high_performance_paddr_size" value="0" />
|
|
<parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
|
|
<parameter name="mmu_processIDNumBits" value="8" />
|
|
<parameter name="debug_onchiptrace" value="false" />
|
|
<parameter name="setting_rf_ecc_present" value="true" />
|
|
<parameter name="ocimem_ramInit" value="false" />
|
|
<parameter name="internalIrqMaskSystemInfo" value="61" />
|
|
<parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
|
|
<parameter name="exceptionAbsoluteAddr" value="134218016" />
|
|
<parameter name="icache_size" value="2048" />
|
|
<parameter
|
|
name="dataSlaveMapParam"
|
|
value="<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='calibration_ram.s1' start='0x18403400' end='0x18403680' type='altera_avalon_onchip_memory2.s1' /><slave name='frame_timer.s1' start='0x18403C00' end='0x18403C20' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403C20' end='0x18403C40' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403C40' end='0x18403C60' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403C60' end='0x18403C80' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403C80' end='0x18403CA0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x18403CA0' end='0x18403CC0' type='altera_msgdma.prefetcher_csr' /><slave name='udp_generator.csr' start='0x18403CC0' end='0x18403CE0' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403CE0' end='0x18403D00' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403D00' end='0x18403D20' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403D20' end='0x18403D40' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403D40' end='0x18403D50' type='altera_avalon_pio.s1' /><slave name='sensor_interface.csr' start='0x18403D50' end='0x18403D60' type='sensor_recon.csr' /><slave name='onchip_flash.csr' start='0x18403D60' end='0x18403D68' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403D68' end='0x18403D70' type='altera_avalon_sysid_qsys.control_slave' /></address-map>" />
|
|
<parameter name="mpu_enabled" value="false" />
|
|
<parameter name="flash_instruction_master_paddr_size" value="0" />
|
|
<parameter name="setting_ecc_present" value="false" />
|
|
<parameter name="stratix_dspblock_shift_mul" value="false" />
|
|
<parameter name="shift_rot_impl" value="0" />
|
|
<parameter name="setting_ioregionBypassDCache" value="false" />
|
|
<parameter name="register_file_por" value="false" />
|
|
<parameter name="faAddrWidth" value="1" />
|
|
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
|
|
<parameter name="resetrequest_enabled" value="true" />
|
|
<parameter name="exceptionSlave" value="ddr3_ram.avl" />
|
|
<parameter name="debug_triggerArming" value="true" />
|
|
<parameter name="debug_OCIOnchipTrace" value="_128" />
|
|
<parameter name="dataAddrWidth" value="29" />
|
|
<parameter name="setting_bit31BypassDCache" value="true" />
|
|
<parameter name="instAddrWidth" value="29" />
|
|
<parameter name="io_regionbase" value="0" />
|
|
<parameter name="mul_32_impl" value="3" />
|
|
<parameter name="translate_on" value=" "synthesis translate_on" " />
|
|
<parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
|
|
<parameter name="mmu_autoAssignTlbPtrSz" value="true" />
|
|
<parameter name="instruction_master_paddr_base" value="0" />
|
|
<parameter name="userDefinedSettings" value="" />
|
|
<parameter name="mul_64_impl" value="0" />
|
|
<parameter name="clockFrequency" value="50000000" />
|
|
<parameter name="resetOffset" value="0" />
|
|
<parameter name="dcache_ramBlockType" value="Automatic" />
|
|
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
|
|
<parameter name="mul_shift_choice" value="0" />
|
|
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
|
|
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
|
|
<parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
|
|
<parameter name="setting_asic_third_party_synthesis" value="false" />
|
|
<parameter name="mpu_minInstRegionSize" value="12" />
|
|
<parameter name="setting_exportdebuginfo" value="false" />
|
|
<parameter name="mmu_tlbPtrSz" value="7" />
|
|
<parameter name="resetSlave" value="ext_flash.avl_mem" />
|
|
<parameter name="dcache_bursts_derived" value="false" />
|
|
<parameter name="multiplierType" value="mul_fast32" />
|
|
<parameter name="debug_traceStorage" value="onchip_trace" />
|
|
<parameter name="setting_preciseIllegalMemAccessException" value="false" />
|
|
<parameter name="fa_cache_linesize" value="0" />
|
|
<parameter name="data_master_paddr_size" value="0" />
|
|
<parameter name="setting_HBreakTest" value="false" />
|
|
<parameter name="setting_disableocitrace" value="false" />
|
|
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
|
|
<parameter name="setting_showInternalSettings" value="false" />
|
|
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
|
|
<parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
|
|
<parameter name="debug_datatrigger" value="0" />
|
|
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
|
|
<parameter name="debug_enabled" value="true" />
|
|
<parameter name="setting_export_large_RAMs" value="false" />
|
|
<parameter name="setting_dc_ecc_present" value="false" />
|
|
<parameter name="dividerType" value="no_div" />
|
|
<parameter name="setting_exportvectors" value="false" />
|
|
<parameter name="breakSlave_derived" value="cpu.debug_mem_slave" />
|
|
<parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
|
|
<parameter name="mmu_ramBlockType" value="Automatic" />
|
|
<parameter name="cdx_enabled" value="false" />
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
|
|
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
|
|
<parameter name="tracefilename" value="" />
|
|
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
|
|
<parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
|
|
<parameter name="setting_oci_version" value="1" />
|
|
<parameter name="icache_burstType" value="None" />
|
|
<parameter name="data_master_high_performance_paddr_size" value="0" />
|
|
<parameter name="setting_disable_tmr_inj" value="false" />
|
|
<parameter name="instruction_master_high_performance_paddr_base" value="0" />
|
|
<parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
|
|
<parameter name="regfile_ramBlockType" value="Automatic" />
|
|
<parameter name="dcache_size" value="2048" />
|
|
<parameter name="breakSlave" value="cpu.jtag_debug_module" />
|
|
<parameter name="exceptionOffset" value="288" />
|
|
<parameter name="tightlyCoupledDataMaster0MapParam" value="" />
|
|
<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
|
|
<parameter name="breakAbsoluteAddr" value="406857760" />
|
|
<parameter name="setting_ecc_sim_test_ports" value="false" />
|
|
<parameter name="setting_showUnpublishedSettings" value="false" />
|
|
<parameter name="master_addr_map" value="false" />
|
|
<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
|
|
<parameter name="resetAbsoluteAddr" value="335544320" />
|
|
<parameter name="cpuArchRev" value="1" />
|
|
<parameter name="setting_dtcm_ecc_present" value="false" />
|
|
<parameter name="customInstSlavesSystemInfo_nios_c" value="<info/>" />
|
|
<parameter name="customInstSlavesSystemInfo_nios_b" value="<info/>" />
|
|
<parameter name="customInstSlavesSystemInfo_nios_a" value="<info/>" />
|
|
<parameter name="setting_interruptControllerType" value="Internal" />
|
|
<parameter name="dcache_tagramBlockType" value="Automatic" />
|
|
<parameter name="debug_insttrace" value="false" />
|
|
<parameter name="setting_itcm_ecc_present" value="false" />
|
|
<parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
|
|
<parameter name="mmu_TLBMissExcAbsAddr" value="0" />
|
|
<parameter name="mpu_useLimit" value="false" />
|
|
<parameter name="icache_numTCIM" value="0" />
|
|
<parameter name="setting_usedesignware" value="false" />
|
|
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
|
|
<parameter name="instruction_master_paddr_size" value="0" />
|
|
<parameter name="mmu_TLBMissExcOffset" value="0" />
|
|
<parameter name="mmu_enabled" value="false" />
|
|
<parameter name="mmu_uitlbNumEntries" value="4" />
|
|
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
|
|
<parameter name="setting_activateTestEndChecker" value="false" />
|
|
<parameter name="cpuID" value="0" />
|
|
<parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
|
|
<parameter name="setting_asic_enabled" value="false" />
|
|
<parameter name="setting_HDLSimCachesCleared" value="true" />
|
|
<parameter name="setting_asic_add_scan_mode_input" value="false" />
|
|
<parameter name="setting_shadowRegisterSets" value="0" />
|
|
<parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
|
|
<parameter name="icache_ramBlockType" value="Automatic" />
|
|
<parameter name="faSlaveMapParam" value="" />
|
|
<parameter name="setting_clearXBitsLDNonBypass" value="true" />
|
|
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
|
|
<parameter name="fa_cache_line" value="2" />
|
|
<parameter name="debug_assignJtagInstanceID" value="false" />
|
|
<parameter name="setting_activateMonitors" value="true" />
|
|
<parameter name="AUTO_CLK_RESET_DOMAIN" value="14" />
|
|
<parameter name="setting_allow_break_inst" value="false" />
|
|
<parameter name="io_regionsize" value="0" />
|
|
<parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
|
|
<parameter name="translate_off" value=" "synthesis translate_off" " />
|
|
<parameter name="mpu_numOfInstRegion" value="8" />
|
|
<parameter name="flash_instruction_master_paddr_base" value="0" />
|
|
<parameter name="cpuReset" value="false" />
|
|
<parameter name="setting_removeRAMinit" value="false" />
|
|
<parameter name="icache_tagramBlockType" value="Automatic" />
|
|
<parameter name="setting_mmu_ecc_present" value="true" />
|
|
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="14" />
|
|
<parameter name="debug_datatrace" value="false" />
|
|
<parameter name="debug_hwbreakpoint" value="2" />
|
|
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
|
|
<parameter name="dataMasterHighPerformanceMapParam" value="" />
|
|
<parameter name="setting_bigEndian" value="false" />
|
|
<parameter name="mpu_minDataRegionSize" value="12" />
|
|
<parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
|
|
<parameter name="debug_jtagInstanceID" value="0" />
|
|
<parameter name="setting_breakslaveoveride" value="false" />
|
|
<parameter name="debug_traceType" value="none" />
|
|
<parameter name="setting_alwaysEncrypt" value="true" />
|
|
<parameter name="setting_oci_export_jtag_signals" value="false" />
|
|
<parameter name="dcache_lineSize_derived" value="32" />
|
|
<parameter name="deviceFamilyName" value="MAX 10" />
|
|
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
|
|
<parameter name="setting_support31bitdcachebypass" value="true" />
|
|
<parameter
|
|
name="instSlaveMapParam"
|
|
value="<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>" />
|
|
<parameter name="setting_bhtPtrSz" value="8" />
|
|
<parameter name="setting_exportHostDebugPort" value="false" />
|
|
<parameter name="tmr_enabled" value="false" />
|
|
<parameter name="data_master_paddr_base" value="0" />
|
|
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
|
|
<parameter name="mpu_numOfDataRegion" value="8" />
|
|
<parameter name="data_master_high_performance_paddr_base" value="0" />
|
|
<parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
|
|
<parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
|
|
<parameter name="dcache_bursts" value="false" />
|
|
<parameter name="setting_asic_synopsys_translate_on_off" value="false" />
|
|
<parameter name="setting_fast_register_read" value="false" />
|
|
<parameter name="mmu_tlbNumWays" value="16" />
|
|
<parameter name="shifterType" value="fast_le_shift" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_mult_cell.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu.sdc"
|
|
type="SDC"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_bht_ram.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_test_bench.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_ic_tag_ram.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_tck.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_a.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_b.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_ociram_default_contents.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_dc_tag_ram.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.ocp"
|
|
type="OTHER"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys" as="cpu" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 29 starting:altera_nios2_gen2 "submodules/q_sys_cpu"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="cpu"><![CDATA["<b>cpu</b>" reuses <b>altera_nios2_gen2_unit</b> "<b>submodules/q_sys_cpu_cpu</b>"]]></message>
|
|
<message level="Info" culprit="cpu"><![CDATA["<b>q_sys</b>" instantiated <b>altera_nios2_gen2</b> "<b>cpu</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 233 starting:altera_nios2_gen2_unit "submodules/q_sys_cpu_cpu"</message>
|
|
<message level="Info" culprit="cpu">Starting RTL generation for module 'q_sys_cpu_cpu'</message>
|
|
<message level="Info" culprit="cpu"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=q_sys_cpu_cpu --dir=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen/ --quartus_bindir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/ --verilog --config=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen//q_sys_cpu_cpu_processor_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Starting Nios II generation</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Elaborating CPU configuration settings</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Creating all objects for CPU</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Testbench</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Instruction decoding</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Instruction fields</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Instruction decodes</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Signals for RTL simulation waveforms</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Instruction controls</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Pipeline frontend</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Pipeline backend</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Generating RTL from CPU objects</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Creating plain-text RTL</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Done Nios II generation</message>
|
|
<message level="Info" culprit="cpu">Done RTL generation for module 'q_sys_cpu_cpu'</message>
|
|
<message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_mem_if_ddr3_emif:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=true,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=true,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=100.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=NIOS,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,SPEED_GRADE_CACHE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=true,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=150000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=300000000,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_mem_if_ddr3_pll:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PERIOD_PS=10000,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_ddr3_phy_core:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_ddr3_afi_mux:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,CFG_TCCD=1,CFG_TCCD_NS=2.5,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEXTGEN=true,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,PRE_V_SERIES_FAMILY=false,RATE=Half,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false)(altera_mem_if_ddr3_afi_splitter:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,CFG_TCCD=1,CFG_TCCD_NS=2.5,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEXTGEN=true,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,PRE_V_SERIES_FAMILY=false,RATE=Half,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false)(altera_mem_if_ddr3_qseq:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_MAX_READ_LATENCY_COUNT_WIDTH=6,AFI_MAX_WRITE_LATENCY_COUNT_WIDTH=6,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AVL_ADDR_WIDTH=13,AVL_DATA_WIDTH=32,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true)(altera_mem_if_nextgen_ddr3_controller:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6(altera_mem_if_nextgen_ddr3_controller_core:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(alt_mem_ddrx_mm_st_converter:19.1:AVL_ADDR_WIDTH=25,AVL_BYTE_ENABLE=true,AVL_DATA_WIDTH=32,AVL_NUM_SYMBOLS=4,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,CFG_DWIDTH_RATIO=4,CTL_AUTOPCH_EN=false,CTL_ECC_ENABLED=false,ENABLE_CTRL_AVALON_INTERFACE=true,LOCAL_ID_WIDTH=8,MAX_PENDING_READ_TRANSACTION=32,MULTICAST_EN=false)(clock:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:))(altera_mem_if_pll_bridge:19.1:CORE_PERIPHERY_DUAL_CLOCK=false,CUT_NEW_FAMILY_TIMING=true,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DISABLE_CHILD_MESSAGING=true,DUPLICATE_PLL_FOR_PHY_CLK=false,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,NUM_PLL_SHARING_INTERFACES=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PRE_V_SERIES_FAMILY=false,RATE=Half,SEQUENCER_TYPE=NIOS,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,USE_DR_CLK=false)(clock:19.1:)(reset:19.1:)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:)(clock:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)"
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instancePathKey="q_sys:.:ddr3_ram"
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kind="altera_mem_if_ddr3_emif"
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version="19.1"
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name="q_sys_ddr3_ram">
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<parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
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<parameter name="VECT_ATTR_COUNTER_ZERO_MATCH" value="0" />
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<parameter name="ENUM_GANGED_ARF" value="DISABLED" />
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<parameter name="LRDIMM_INT" value="0" />
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<parameter name="ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
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<parameter name="MAX_LATENCY_COUNT_WIDTH" value="5" />
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<parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
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<parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
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<parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
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<parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
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<parameter name="MEM_LEVELING" value="true" />
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<parameter name="CV_ENUM_PRIORITY_1_0" value="WEIGHT_0" />
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<parameter name="ENUM_MEM_IF_TRRD" value="TRRD_4" />
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<parameter name="CV_ENUM_PRIORITY_1_2" value="WEIGHT_0" />
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<parameter name="ENUM_ATTR_COUNTER_ZERO_RESET" value="DISABLED" />
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<parameter name="CV_ENUM_PRIORITY_1_1" value="WEIGHT_0" />
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<parameter name="PLL_AFI_HALF_CLK_DIV" value="1" />
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<parameter name="MEM_ADD_LAT" value="0" />
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<parameter name="CV_ENUM_PRIORITY_1_4" value="WEIGHT_0" />
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<parameter name="CV_ENUM_PRIORITY_1_3" value="WEIGHT_0" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR" value="0" />
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<parameter name="CV_ENUM_PRIORITY_1_5" value="WEIGHT_0" />
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<parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT" value="0" />
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<parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
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<parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
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<parameter name="ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
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<parameter name="INTG_MEM_IF_TRFC" value="34" />
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<parameter name="MEM_REGDIMM_ENABLED" value="false" />
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<parameter name="PLL_HR_CLK_FREQ" value="0.0" />
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<parameter name="AFI_DQ_WIDTH" value="32" />
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<parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
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<parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
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<parameter name="AP_MODE_EN" value="0" />
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<parameter name="ENUM_CPORT5_RDY_ALMOST_FULL" value="NOT_FULL" />
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<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
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<parameter name="CALIB_LFIFO_OFFSET" value="4" />
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<parameter name="INTG_SUM_WT_PRIORITY_4" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_5" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_6" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_7" value="0" />
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<parameter name="ENUM_CPORT2_RDY_ALMOST_FULL" value="NOT_FULL" />
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<parameter name="VECT_ATTR_COUNTER_ZERO_MASK" value="0" />
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<parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
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<parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
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<parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="0 ps" />
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<parameter name="ALLOCATED_WFIFO_PORT" value="0,None,None,None,None,None" />
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<parameter name="MEM_TRAS_NS" value="35.0" />
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<parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
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<parameter name="ENABLE_EXTRA_REPORTING" value="false" />
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<parameter name="IO_DQ_OUT_RESERVE" value="0" />
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<parameter name="IO_DM_OUT_RESERVE" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_0" value="0" />
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<parameter name="CV_ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
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<parameter name="INTG_SUM_WT_PRIORITY_1" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_2" value="0" />
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<parameter name="DELAY_PER_OPA_TAP" value="416" />
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<parameter name="INTG_SUM_WT_PRIORITY_3" value="0" />
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<parameter name="ENABLE_BONDING" value="false" />
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<parameter name="HHP_HPS_VERIFICATION" value="false" />
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<parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC" value="0" />
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<parameter name="CV_ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
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<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="2500" />
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<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP" value="0" />
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<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
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<parameter name="ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
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<parameter name="RDIMM_CONFIG" value="0000000000000000" />
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<parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="CV_ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
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<parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
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<parameter name="ENUM_ENABLE_INTR" value="DISABLED" />
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<parameter name="INTG_MEM_AUTO_PD_CYCLES" value="0" />
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<parameter name="AVL_DATA_WIDTH" value="32" />
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<parameter name="PLL_AFI_CLK_MULT_CACHE" value="3" />
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<parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
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<parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
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<parameter name="MR1_RDQS" value="0" />
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<parameter name="ENUM_MEM_IF_ROWADDR_WIDTH" value="ADDR_WIDTH_16" />
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<parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
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<parameter name="MR0_PD" value="0" />
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<parameter name="MEM_VENDOR" value="JEDEC" />
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<parameter name="MEM_IF_CS_PER_RANK" value="1" />
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<parameter name="CV_PORT_1_CONNECT_TO_AV_PORT" value="1" />
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<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
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<parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
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<parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
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<parameter name="CV_ENUM_CPORT1_TYPE" value="DISABLE" />
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<parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="0 ps" />
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<parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
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<parameter name="USE_MEM_CLK_FREQ" value="false" />
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<parameter name="CV_MSB_WFIFO_PORT_5" value="5" />
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<parameter name="MEM_DEVICE" value="MISSING_MODEL" />
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<parameter name="CFG_READ_ODT_CHIP" value="0" />
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<parameter name="CV_MSB_WFIFO_PORT_4" value="5" />
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<parameter name="CV_MSB_WFIFO_PORT_3" value="5" />
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<parameter name="IO_DQS_EN_PHASE_MAX" value="7" />
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<parameter name="RDIMM" value="false" />
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<parameter name="ENUM_MEM_IF_COLADDR_WIDTH" value="ADDR_WIDTH_12" />
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<parameter name="PLL_CONFIG_CLK_FREQ" value="0.0" />
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<parameter name="ENABLE_USER_ECC" value="false" />
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<parameter name="PLL_PHASE_COUNTER_WIDTH" value="4" />
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<parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD" value="0" />
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<parameter name="MEM_TRC" value="15" />
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<parameter name="AVL_ADDR_WIDTH_PORT_2" value="0" />
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<parameter name="ENUM_PRIORITY_6_4" value="WEIGHT_0" />
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<parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID" value="0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_3" value="USE_NO" />
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<parameter name="AVL_ADDR_WIDTH_PORT_1" value="0" />
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<parameter name="ENUM_PRIORITY_6_5" value="WEIGHT_0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_2" value="USE_NO" />
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<parameter name="AVL_ADDR_WIDTH_PORT_0" value="0" />
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<parameter name="ENUM_PRIORITY_6_2" value="WEIGHT_0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_5" value="USE_NO" />
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<parameter name="ENUM_PRIORITY_6_3" value="WEIGHT_0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_4" value="USE_NO" />
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<parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
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<parameter name="AFI_CS_WIDTH" value="2" />
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<parameter name="ENUM_PRIORITY_6_0" value="WEIGHT_0" />
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<parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
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<parameter name="AVL_ADDR_WIDTH_PORT_5" value="0" />
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<parameter name="ENUM_PRIORITY_6_1" value="WEIGHT_0" />
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<parameter name="AVL_ADDR_WIDTH_PORT_4" value="0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_1" value="USE_NO" />
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<parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
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<parameter name="AVL_ADDR_WIDTH_PORT_3" value="0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_0" value="USE_NO" />
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<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
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<parameter name="CV_MSB_WFIFO_PORT_2" value="5" />
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<parameter name="CV_MSB_WFIFO_PORT_1" value="5" />
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<parameter name="PLL_NIOS_CLK_MULT" value="0" />
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<parameter name="ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
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<parameter name="CV_MSB_WFIFO_PORT_0" value="5" />
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<parameter name="TG_TEMP_PORT_5" value="0" />
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<parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
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<parameter name="TG_TEMP_PORT_3" value="0" />
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<parameter name="TG_TEMP_PORT_4" value="0" />
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<parameter name="TG_TEMP_PORT_1" value="0" />
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<parameter name="TG_TEMP_PORT_2" value="0" />
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<parameter name="MEM_CLK_NS" value="3.333" />
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<parameter name="TG_TEMP_PORT_0" value="0" />
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<parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
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<parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
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<parameter name="ENUM_MEM_IF_BURSTLENGTH" value="MEM_IF_BURSTLENGTH_8" />
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<parameter name="PLL_AFI_CLK_MULT" value="3" />
|
|
<parameter name="SKIP_MEM_INIT" value="true" />
|
|
<parameter name="CFG_ENABLE_NO_DM" value="0" />
|
|
<parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="MR1_TDQS" value="0" />
|
|
<parameter name="INTG_MEM_CLK_ENTRY_CYCLES" value="10" />
|
|
<parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
|
|
<parameter name="CTL_ECC_MULTIPLES_16_24_40_72" value="1" />
|
|
<parameter name="CV_ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="1" />
|
|
<parameter name="ENUM_MEM_IF_TCWL" value="TCWL_5" />
|
|
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
|
|
<parameter name="REFRESH_BURST_VALIDATION" value="false" />
|
|
<parameter name="DEVICE_FAMILY_PARAM" value="" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID" value="0" />
|
|
<parameter name="ENUM_MEM_IF_TRTP" value="TRTP_4" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="270.0" />
|
|
<parameter name="INTG_POWER_SAVING_EXIT_CYCLES" value="5" />
|
|
<parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="50" />
|
|
<parameter name="MEM_IF_ADDR_WIDTH" value="14" />
|
|
<parameter name="PLL_DR_CLK_DIV" value="0" />
|
|
<parameter name="USE_SEQUENCER_BFM" value="false" />
|
|
<parameter name="DELAY_PER_DCHAIN_TAP" value="50" />
|
|
<parameter name="CSR_ADDR_WIDTH" value="8" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID" value="0" />
|
|
<parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="6668 ps" />
|
|
<parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
|
|
<parameter name="CV_ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
|
|
<parameter name="CV_ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
|
|
<parameter name="RDIMM_INT" value="0" />
|
|
<parameter name="CV_ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
|
|
<parameter name="CTL_CSR_READ_ONLY" value="1" />
|
|
<parameter name="ENUM_MASK_DBE_INTR" value="DISABLED" />
|
|
<parameter name="CV_ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
|
|
<parameter name="CV_ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="CV_ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
|
|
<parameter name="READ_VALID_FIFO_SIZE" value="16" />
|
|
<parameter name="DLL_MASTER" value="true" />
|
|
<parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
|
|
<parameter name="MEM_TWTR" value="6" />
|
|
<parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
|
|
<parameter name="ENUM_ENABLE_BURST_INTERRUPT" value="DISABLED" />
|
|
<parameter name="CV_ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="WEIGHT_PORT_2" value="0" />
|
|
<parameter name="WEIGHT_PORT_1" value="0" />
|
|
<parameter name="WEIGHT_PORT_0" value="0" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="MAX10" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="WEIGHT_PORT_5" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="WEIGHT_PORT_4" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
|
|
<parameter name="WEIGHT_PORT_3" value="0" />
|
|
<parameter name="ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="CV_ENUM_ENABLE_BONDING_2" value="DISABLED" />
|
|
<parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
|
|
<parameter name="CV_ENUM_ENABLE_BONDING_3" value="DISABLED" />
|
|
<parameter name="MEM_TRFC_NS" value="110.0" />
|
|
<parameter name="CV_ENUM_ENABLE_BONDING_4" value="DISABLED" />
|
|
<parameter name="CV_ENUM_ENABLE_BONDING_5" value="DISABLED" />
|
|
<parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
|
|
<parameter name="ENABLE_ISS_PROBES" value="false" />
|
|
<parameter name="MR2_RTT_WR" value="0" />
|
|
<parameter name="ENUM_MEM_IF_TFAW" value="TFAW_16" />
|
|
<parameter name="TIMING_BOARD_TDS_APPLIED" value="0.16" />
|
|
<parameter name="AFI_ODT_WIDTH" value="2" />
|
|
<parameter name="PLL_MASTER" value="true" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
|
|
<parameter name="CV_ENUM_ENABLE_BONDING_0" value="DISABLED" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
|
|
<parameter name="CV_ENUM_ENABLE_BONDING_1" value="DISABLED" />
|
|
<parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="DISCRETE_FLY_BY" value="true" />
|
|
<parameter name="QVLD_WR_ADDRESS_OFFSET" value="4" />
|
|
<parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="1" />
|
|
<parameter name="AVL_SYMBOL_WIDTH" value="8" />
|
|
<parameter name="TB_PLL_DLL_MASTER" value="true" />
|
|
<parameter name="MEM_IF_DM_WIDTH" value="1" />
|
|
<parameter name="LOCAL_CS_WIDTH" value="0" />
|
|
<parameter name="CTL_ECC_ENABLED" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="2500" />
|
|
<parameter name="AUTO_POWERDN_EN" value="false" />
|
|
<parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PHY_CLKBUF" value="false" />
|
|
<parameter name="ENABLE_ABS_RAM_INTERNAL" value="false" />
|
|
<parameter name="MAX_PENDING_WR_CMD" value="16" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="ENUM_ATTR_COUNTER_ONE_RESET" value="DISABLED" />
|
|
<parameter name="ENUM_WRITE_ODT_CHIP" value="ODT_DISABLED" />
|
|
<parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
|
|
<parameter name="MEM_IF_CHIP_BITS" value="1" />
|
|
<parameter name="ENUM_MEM_IF_CS_PER_RANK" value="MEM_IF_CS_PER_RANK_1" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
|
|
<parameter name="MEM_IF_CK_WIDTH" value="1" />
|
|
<parameter name="MEM_TCL" value="5" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="ENUM_LOCAL_IF_CS_WIDTH" value="ADDR_WIDTH_2" />
|
|
<parameter name="TIMING_TDQSCK" value="225" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="CTL_USR_REFRESH_EN" value="false" />
|
|
<parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
|
|
<parameter name="ENUM_WR_FIFO_IN_USE_3" value="FALSE" />
|
|
<parameter name="ENUM_WR_FIFO_IN_USE_2" value="FALSE" />
|
|
<parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP" value="1" />
|
|
<parameter name="ENUM_WR_FIFO_IN_USE_1" value="FALSE" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="ENUM_WR_FIFO_IN_USE_0" value="FALSE" />
|
|
<parameter name="ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="AFI_RATE_RATIO" value="2" />
|
|
<parameter name="ENUM_THLD_JAR2_3" value="THRESHOLD_16" />
|
|
<parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
|
|
<parameter name="ENUM_THLD_JAR2_4" value="THRESHOLD_16" />
|
|
<parameter name="ENUM_THLD_JAR2_5" value="THRESHOLD_16" />
|
|
<parameter name="AV_PORT_0_CONNECT_TO_CV_PORT" value="0" />
|
|
<parameter name="PLL_MEM_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="ENUM_CTL_ECC_RMW_ENABLED" value="CTL_ECC_RMW_DISABLED" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="CFG_TCCD_NS" value="2.5" />
|
|
<parameter name="IO_DQS_IN_RESERVE" value="3" />
|
|
<parameter name="AVL_NUM_SYMBOLS" value="4" />
|
|
<parameter name="ENABLE_NIOS_OCI" value="false" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="FIX_READ_LATENCY" value="8" />
|
|
<parameter name="CTL_OUTPUT_REGD" value="false" />
|
|
<parameter name="CV_PORT_0_CONNECT_TO_AV_PORT" value="0" />
|
|
<parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
|
|
<parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="CTL_CSR_ENABLED" value="false" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="PHY_CSR_ENABLED" value="false" />
|
|
<parameter name="DQ_DDR" value="1" />
|
|
<parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_DEG" value="270.0" />
|
|
<parameter name="MEM_INIT_FILE" value="" />
|
|
<parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
|
|
<parameter name="AVL_PORT" value="" />
|
|
<parameter name="TB_RATE" value="HALF" />
|
|
<parameter name="REF_CLK_FREQ_CACHE_VALID" value="true" />
|
|
<parameter name="ALLOCATED_RFIFO_PORT" value="0,None,None,None,None,None" />
|
|
<parameter name="MEM_CK_WIDTH" value="1" />
|
|
<parameter name="MEM_ATCL" value="Disabled" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="DISABLE_CHILD_MESSAGING" value="false" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
|
|
<parameter name="MEM_TDQSCK" value="1" />
|
|
<parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD" value="0" />
|
|
<parameter name="MEM_WTCL" value="5" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP" value="0" />
|
|
<parameter name="CV_ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="PLL_MEM_CLK_MULT" value="3" />
|
|
<parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="MEM_IF_CS_PER_DIMM" value="1" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
|
|
<parameter name="CTL_ECC_CSR_ENABLED" value="false" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP" value="0" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
|
|
<parameter name="MEM_AUTO_PD_CYCLES" value="0" />
|
|
<parameter name="CV_ENUM_CPORT3_TYPE" value="DISABLE" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
|
|
<parameter name="PLL_WRITE_CLK_DIV" value="1" />
|
|
<parameter name="CALIB_VFIFO_OFFSET" value="12" />
|
|
<parameter name="CTL_ECC_MULTIPLES_40_72" value="1" />
|
|
<parameter name="MSB_RFIFO_PORT_2" value="5" />
|
|
<parameter name="MSB_RFIFO_PORT_3" value="5" />
|
|
<parameter name="MSB_RFIFO_PORT_4" value="5" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="MSB_RFIFO_PORT_5" value="5" />
|
|
<parameter name="CV_ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
|
|
<parameter name="MEM_DRV_STR" value="RZQ/6" />
|
|
<parameter name="MEM_TREFI" value="2341" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="NUM_SUBGROUP_PER_READ_DQS" value="1" />
|
|
<parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
|
|
<parameter name="MSB_RFIFO_PORT_0" value="5" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="MEM_TRP_NS" value="13.75" />
|
|
<parameter name="MSB_RFIFO_PORT_1" value="5" />
|
|
<parameter name="QVLD_EXTRA_FLOP_STAGES" value="0" />
|
|
<parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="CTL_HRB_ENABLED" value="false" />
|
|
<parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ" value="300.0" />
|
|
<parameter name="EXTRA_SETTINGS" value="" />
|
|
<parameter name="ENUM_MMR_CFG_MEM_BL" value="MP_BL_8" />
|
|
<parameter name="PLL_DR_CLK_FREQ_STR" value="" />
|
|
<parameter name="MEM_IF_CS_WIDTH" value="1" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_1" value="USE_NO" />
|
|
<parameter name="STARVE_LIMIT" value="10" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_2" value="USE_NO" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_3" value="USE_NO" />
|
|
<parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP" value="1" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_4" value="USE_NO" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_0" value="USE_NO" />
|
|
<parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="false" />
|
|
<parameter name="SEQUENCER_TYPE_CACHE" value="NIOS" />
|
|
<parameter name="CTL_USR_REFRESH" value="0" />
|
|
<parameter name="AV_PORT_2_CONNECT_TO_CV_PORT" value="2" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_5" value="USE_NO" />
|
|
<parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
|
|
<parameter name="MR0_BT" value="0" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL" value="0" />
|
|
<parameter name="MR1_AL" value="0" />
|
|
<parameter name="DQS_PHASE_SHIFT" value="9000" />
|
|
<parameter name="MR0_BL" value="1" />
|
|
<parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
|
|
<parameter name="MEM_TRCD" value="5" />
|
|
<parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
|
|
<parameter name="MAX_PENDING_RD_CMD" value="32" />
|
|
<parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="REGISTER_C2P" value="false" />
|
|
<parameter name="MEM_WTCL_INT" value="5" />
|
|
<parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
|
|
<parameter name="DQS_EN_DELAY_MAX" value="7" />
|
|
<parameter name="ENUM_CPORT1_TYPE" value="DISABLE" />
|
|
<parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
|
|
<parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
|
|
<parameter name="REF_CLK_FREQ" value="100.0" />
|
|
<parameter name="AV_PORT_5_CONNECT_TO_CV_PORT" value="5" />
|
|
<parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV" value="0" />
|
|
<parameter name="MR0_DLL" value="1" />
|
|
<parameter name="FORCE_SHADOW_REGS" value="AUTO" />
|
|
<parameter name="PINGPONGPHY_EN" value="false" />
|
|
<parameter name="CFG_WRITE_ODT_CHIP" value="1" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_5" value="2" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="6668 ps" />
|
|
<parameter name="MR2_ASR" value="0" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_3" value="2" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_4" value="2" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_1" value="2" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_2" value="2" />
|
|
<parameter name="MR2_CWL" value="0" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_0" value="2" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV" value="1" />
|
|
<parameter name="HPS_PROTOCOL" value="DEFAULT" />
|
|
<parameter name="MEM_IF_LRDIMM_RM" value="0" />
|
|
<parameter name="VECT_ATTR_COUNTER_ONE_MATCH" value="0" />
|
|
<parameter name="ENUM_PRIORITY_1_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_1" value="WEIGHT_0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="ENUM_PRIORITY_1_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="DUPLICATE_AC" value="false" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_5" value="2" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_1" value="2" />
|
|
<parameter name="DUAL_WRITE_CLOCK" value="false" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_2" value="2" />
|
|
<parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_3" value="2" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_4" value="2" />
|
|
<parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
|
|
<parameter name="CFG_POWER_SAVING_EXIT_CYCLES" value="5" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_0" value="2" />
|
|
<parameter name="CV_PORT_2_CONNECT_TO_AV_PORT" value="2" />
|
|
<parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
|
|
<parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
|
|
<parameter name="AUTO_PD_CYCLES" value="0" />
|
|
<parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
|
|
<parameter name="ENUM_CPORT5_TYPE" value="DISABLE" />
|
|
<parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD" value="0" />
|
|
<parameter name="AFI_BANKADDR_WIDTH" value="6" />
|
|
<parameter name="CV_ENUM_CPORT0_TYPE" value="DISABLE" />
|
|
<parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="ENUM_THLD_JAR2_0" value="THRESHOLD_16" />
|
|
<parameter name="CTL_DEEP_POWERDN_EN" value="false" />
|
|
<parameter name="CTL_TBP_NUM" value="4" />
|
|
<parameter name="ENUM_THLD_JAR2_1" value="THRESHOLD_16" />
|
|
<parameter name="MEM_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="ENUM_THLD_JAR2_2" value="THRESHOLD_16" />
|
|
<parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
|
|
<parameter name="CTL_ENABLE_BURST_TERMINATE_INT" value="false" />
|
|
<parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="CFG_ECC_DECODER_REG" value="0" />
|
|
<parameter name="CTL_ENABLE_BURST_INTERRUPT_INT" value="false" />
|
|
<parameter name="REF_CLK_FREQ_CACHE" value="100.0" />
|
|
<parameter name="TRACKING_ERROR_TEST" value="false" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="REF_CLK_FREQ_STR" value="100.0 MHz" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
|
|
<parameter name="PLL_MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
|
|
<parameter name="MR1_RTT" value="0" />
|
|
<parameter name="READ_FIFO_HALF_RATE" value="true" />
|
|
<parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
|
|
<parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
|
|
<parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
|
|
<parameter name="CSR_DATA_WIDTH" value="32" />
|
|
<parameter name="MEM_DLL_EN" value="true" />
|
|
<parameter name="IS_ES_DEVICE" value="false" />
|
|
<parameter name="PRE_V_SERIES_FAMILY" value="true" />
|
|
<parameter name="USE_MM_ADAPTOR" value="true" />
|
|
<parameter name="HHP_HPS_SIMULATION" value="false" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_1" value="WEIGHT_0" />
|
|
<parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_0" value="WEIGHT_0" />
|
|
<parameter name="IO_OUT2_DELAY_MAX" value="7" />
|
|
<parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
|
|
<parameter name="PLL_MEM_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
|
|
<parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
|
|
<parameter name="HCX_COMPAT_MODE" value="false" />
|
|
<parameter name="MEM_IF_DQSN_EN" value="true" />
|
|
<parameter name="ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="AC_ROM_MR0" value="0001000010001" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_TRAS" value="11" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="ENUM_ECC_DQ_WIDTH" value="ECC_DQ_WIDTH_0" />
|
|
<parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP" value="0" />
|
|
<parameter name="MEM_TINIT_US" value="500" />
|
|
<parameter name="CTL_SELF_REFRESH" value="0" />
|
|
<parameter name="ENUM_MEM_IF_TWTR" value="TWTR_4" />
|
|
<parameter name="CALIBRATION_MODE" value="Skip" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
|
|
<parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
|
|
<parameter name="ENUM_USER_ECC_EN" value="DISABLE" />
|
|
<parameter name="PLL_MEM_CLK_DIV" value="1" />
|
|
<parameter name="OCT_SHARING_MODE" value="None" />
|
|
<parameter name="AC_ROM_MR2" value="0000000000000" />
|
|
<parameter name="AC_ROM_MR1" value="0000000000000" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV" value="0" />
|
|
<parameter name="AC_ROM_MR3" value="0000000000000" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH" value="0" />
|
|
<parameter name="USE_HARD_READ_FIFO" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID" value="0" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
|
|
<parameter name="ENUM_CFG_BURST_LENGTH" value="BL_8" />
|
|
<parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_3" value="WEIGHT_0" />
|
|
<parameter name="PHY_VERSION_NUMBER" value="191" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_2" value="WEIGHT_0" />
|
|
<parameter name="MEM_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_5" value="WEIGHT_0" />
|
|
<parameter name="TIMING_BOARD_TIH_APPLIED" value="0.22" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_4" value="WEIGHT_0" />
|
|
<parameter name="MEM_SRT" value="Normal" />
|
|
<parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
|
|
<parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
|
|
<parameter name="PLL_WRITE_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
|
|
<parameter name="EXTRA_VFIFO_SHIFT" value="0" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
|
|
<parameter name="CFG_TYPE" value="2" />
|
|
<parameter name="ENUM_CLR_INTR" value="NO_CLR_INTR" />
|
|
<parameter name="ENUM_CPORT3_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_CLK_PARAM_VALID" value="false" />
|
|
<parameter name="DELAY_CHAIN_LENGTH" value="8" />
|
|
<parameter name="PLL_WRITE_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_1" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_2" value="WEIGHT_0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID" value="0" />
|
|
<parameter name="ENUM_PRIORITY_5_5" value="WEIGHT_0" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="ENUM_PRIORITY_5_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_2" value="WEIGHT_0" />
|
|
<parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="ENUM_PRIORITY_5_0" value="WEIGHT_0" />
|
|
<parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="AV_PORT_1_CONNECT_TO_CV_PORT" value="1" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="CV_PORT_5_CONNECT_TO_AV_PORT" value="5" />
|
|
<parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="MEM_TMRD_CK" value="4" />
|
|
<parameter name="CFG_INTERFACE_WIDTH" value="8" />
|
|
<parameter name="IO_OUT1_DELAY_MAX" value="15" />
|
|
<parameter name="DEVICE_DEPTH" value="1" />
|
|
<parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
|
|
<parameter name="CV_ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_MULT" value="3" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="ENUM_MASK_CORR_DROPPED_INTR" value="DISABLED" />
|
|
<parameter name="AC_PACKAGE_DESKEW" value="false" />
|
|
<parameter name="ENUM_ATTR_STATIC_CONFIG_VALID" value="DISABLED" />
|
|
<parameter name="CTL_ENABLE_WDATA_PATH_LATENCY" value="false" />
|
|
<parameter name="ENUM_CLOCK_OFF_2" value="DISABLED" />
|
|
<parameter name="ENUM_CLOCK_OFF_1" value="DISABLED" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
|
|
<parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="ENUM_CLOCK_OFF_0" value="DISABLED" />
|
|
<parameter name="SEQ_BURST_COUNT_WIDTH" value="1" />
|
|
<parameter name="CFG_BURST_LENGTH" value="8" />
|
|
<parameter name="ENUM_CLOCK_OFF_5" value="DISABLED" />
|
|
<parameter name="ENUM_CLOCK_OFF_4" value="DISABLED" />
|
|
<parameter name="ENUM_CLOCK_OFF_3" value="DISABLED" />
|
|
<parameter name="PHY_ONLY" value="false" />
|
|
<parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
|
|
<parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="false" />
|
|
<parameter name="TRFC" value="350" />
|
|
<parameter name="IO_STANDARD" value="SSTL-15" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_5" value="WEIGHT_0" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="SPEED_GRADE_CACHE" value="6" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_4" value="WEIGHT_0" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_CACHE" value="150.0" />
|
|
<parameter name="READ_FIFO_SIZE" value="8" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="TB_MEM_IF_DQ_WIDTH" value="8" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
|
|
<parameter name="NEGATIVE_WRITE_CK_PHASE" value="true" />
|
|
<parameter name="CFG_MEM_CLK_ENTRY_CYCLES" value="20" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
|
|
<parameter name="CV_ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
|
|
<parameter name="ENUM_CFG_INTERFACE_WIDTH" value="DWIDTH_32" />
|
|
<parameter name="ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="MEM_ATCL_INT" value="0" />
|
|
<parameter name="ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
|
|
<parameter name="CV_ENUM_CPORT4_TYPE" value="DISABLE" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="TIMING_TDSS" value="0.18" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_1" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_0" value="WEIGHT_0" />
|
|
<parameter name="CSR_BE_WIDTH" value="4" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_2" value="WEIGHT_0" />
|
|
<parameter name="PLL_LOCATION" value="Top_Bottom" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_4" value="WEIGHT_0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="2500 ps" />
|
|
<parameter name="MEM_TRTP_NS" value="7.5" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_2" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_3" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_0" value="0" />
|
|
<parameter name="PLL_SHARING_MODE" value="None" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_1" value="0" />
|
|
<parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_4" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_5" value="0" />
|
|
<parameter name="ENUM_PRIORITY_3_5" value="WEIGHT_0" />
|
|
<parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="AP_MODE" value="false" />
|
|
<parameter name="ENUM_PRIORITY_3_3" value="WEIGHT_0" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="ENUM_PRIORITY_3_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_3_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_3_2" value="WEIGHT_0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="ENUM_PRIORITY_3_0" value="WEIGHT_0" />
|
|
<parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="false" />
|
|
<parameter name="ENUM_MEM_IF_MEMTYPE" value="DDR3_SDRAM" />
|
|
<parameter name="MEM_PD" value="DLL off" />
|
|
<parameter name="MAX10_RTL_SEQ" value="true" />
|
|
<parameter name="TIMING_TDSH" value="0.18" />
|
|
<parameter name="CTL_AUTOPCH_EN" value="false" />
|
|
<parameter name="ENUM_PDN_EXIT_CYCLES" value="SLOW_EXIT" />
|
|
<parameter name="REF_CLK_FREQ_MAX_CACHE" value="500.0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID" value="0" />
|
|
<parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
|
|
<parameter name="MEM_DQ_WIDTH" value="8" />
|
|
<parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
|
|
<parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
|
|
<parameter name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES" value="" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="FLY_BY" value="false" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="TIMING_TQSH" value="0.4" />
|
|
<parameter name="CV_ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="LSB_RFIFO_PORT_0" value="5" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ" value="0.0" />
|
|
<parameter name="AFI_CLK_PAIR_COUNT" value="1" />
|
|
<parameter name="HARD_EMIF" value="false" />
|
|
<parameter name="LSB_RFIFO_PORT_5" value="5" />
|
|
<parameter name="LSB_RFIFO_PORT_3" value="5" />
|
|
<parameter name="LSB_RFIFO_PORT_4" value="5" />
|
|
<parameter name="LSB_RFIFO_PORT_1" value="5" />
|
|
<parameter name="CV_ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="LSB_RFIFO_PORT_2" value="5" />
|
|
<parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
|
|
<parameter name="MEM_CLK_MAX_NS" value="1.25" />
|
|
<parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
|
|
<parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="CALIB_REG_WIDTH" value="8" />
|
|
<parameter name="DWIDTH_RATIO" value="4" />
|
|
<parameter name="INTG_MEM_IF_TREFI" value="3120" />
|
|
<parameter name="CFG_CLR_INTR" value="0" />
|
|
<parameter name="ENABLE_ABSTRACT_RAM" value="false" />
|
|
<parameter name="ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_ENABLE_NO_DM" value="DISABLED" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="MEM_TINIT_CK" value="150000" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
|
|
<parameter name="IO_DQS_OUT_RESERVE" value="3" />
|
|
<parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
|
|
<parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
|
|
<parameter name="MEM_BL" value="OTF" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
|
|
<parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
|
|
<parameter name="MEM_BT" value="Sequential" />
|
|
<parameter name="ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
|
|
<parameter name="CONTROLLER_LATENCY" value="5" />
|
|
<parameter name="MEM_TRTP" value="3" />
|
|
<parameter name="ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
|
|
<parameter name="TREFI" value="35100" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
|
|
<parameter name="ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
|
|
<parameter name="PLL_AFI_CLK_DIV_CACHE" value="2" />
|
|
<parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="MEM_DQ_PER_DQS" value="8" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CTL_REGDIMM_ENABLED" value="REGDIMM_DISABLED" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_2" value="WEIGHT_0" />
|
|
<parameter name="ENABLE_BURST_MERGE" value="false" />
|
|
<parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="2" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_4" value="WEIGHT_0" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
|
|
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
|
|
<parameter name="CV_ENUM_CPORT5_TYPE" value="DISABLE" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="ENUM_ENABLE_BURST_TERMINATE" value="DISABLED" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
|
|
<parameter name="VECT_ATTR_DEBUG_SELECT_BYTE" value="0" />
|
|
<parameter name="CV_PORT_4_CONNECT_TO_AV_PORT" value="4" />
|
|
<parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
|
|
<parameter name="DEVICE_WIDTH" value="1" />
|
|
<parameter name="SOPC_COMPAT_RESET" value="false" />
|
|
<parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
|
|
<parameter name="PLL_HR_CLK_FREQ_STR" value="" />
|
|
<parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
|
|
<parameter name="AFI_CONTROL_WIDTH" value="2" />
|
|
<parameter name="ENUM_ENABLE_PIPELINEGLOBAL" value="DISABLED" />
|
|
<parameter name="COMMAND_PHASE_CACHE" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_DIV" value="0" />
|
|
<parameter name="REF_CLK_FREQ_MIN_CACHE" value="10.0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_6" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_7" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_4" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_5" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_2" value="0" />
|
|
<parameter name="MEM_IF_DM_PINS_EN" value="true" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_3" value="0" />
|
|
<parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_0" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_1" value="0" />
|
|
<parameter name="ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
|
|
<parameter name="USER_DEBUG_LEVEL" value="1" />
|
|
<parameter name="ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
|
|
<parameter name="ENUM_SINGLE_READY_3" value="CONCATENATE_RDY" />
|
|
<parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
|
|
<parameter name="ENUM_SINGLE_READY_1" value="CONCATENATE_RDY" />
|
|
<parameter name="ENUM_SINGLE_READY_2" value="CONCATENATE_RDY" />
|
|
<parameter name="ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_GEN_DBE" value="GEN_DBE_DISABLED" />
|
|
<parameter name="ENUM_SINGLE_READY_0" value="CONCATENATE_RDY" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="DATA_RATE_RATIO" value="2" />
|
|
<parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
|
|
<parameter name="ENUM_ENABLE_DQS_TRACKING" value="DISABLED" />
|
|
<parameter name="ENUM_ENABLE_BONDING_3" value="DISABLED" />
|
|
<parameter name="ENUM_ENABLE_BONDING_2" value="DISABLED" />
|
|
<parameter name="ENUM_ENABLE_BONDING_5" value="DISABLED" />
|
|
<parameter name="ENUM_MEM_IF_TCL" value="TCL_6" />
|
|
<parameter name="ENUM_ENABLE_BONDING_4" value="DISABLED" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
|
|
<parameter name="LOW_LATENCY" value="false" />
|
|
<parameter name="ENUM_ENABLE_BONDING_1" value="DISABLED" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
|
|
<parameter name="ENUM_ENABLE_BONDING_0" value="DISABLED" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="270.0" />
|
|
<parameter name="ENUM_MEM_IF_DQ_PER_CHIP" value="MEM_IF_DQ_PER_CHIP_8" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="RATE" value="Half" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="MR1_WL" value="0" />
|
|
<parameter name="POWER_OF_TWO_BUS" value="false" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="MR3_MPR_RF" value="0" />
|
|
<parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
|
|
<parameter name="DEBUG_MODE" value="false" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
|
|
<parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="1" />
|
|
<parameter name="CFG_STARVE_LIMIT" value="10" />
|
|
<parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT" value="0" />
|
|
<parameter name="ENUM_PRIORITY_7_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_7_4" value="WEIGHT_0" />
|
|
<parameter name="MEM_CLK_MAX_PS" value="1250.0" />
|
|
<parameter name="ENUM_PRIORITY_7_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_7_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_7_0" value="WEIGHT_0" />
|
|
<parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
|
|
<parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
|
|
<parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
|
|
<parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="EXPORT_AFI_HALF_CLK" value="false" />
|
|
<parameter name="ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
|
|
<parameter name="MEM_BURST_LENGTH" value="8" />
|
|
<parameter name="ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
|
|
<parameter name="ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_STR" value="150.0 MHz" />
|
|
<parameter name="IO_DQDQS_OUT_PHASE_MAX" value="14" />
|
|
<parameter name="MEM_TRRD" value="2" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
|
|
<parameter name="ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
|
|
<parameter name="REFRESH_INTERVAL" value="15000" />
|
|
<parameter name="ENUM_PRIORITY_7_5" value="WEIGHT_0" />
|
|
<parameter name="MEM_INIT_EN" value="false" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH" value="0" />
|
|
<parameter name="ADDR_RATE_RATIO" value="1" />
|
|
<parameter name="TIMING_BOARD_TDH_APPLIED" value="0.145" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="CFG_SELF_RFSH_EXIT_CYCLES" value="512" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
|
|
<parameter name="CTL_REGDIMM_ENABLED" value="false" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_1" value="5" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_0" value="5" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_0" value="0" />
|
|
<parameter name="CV_ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_GEN_SBE" value="GEN_SBE_DISABLED" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
|
|
<parameter name="ENUM_ENABLE_BONDING_WRAPBACK" value="DISABLED" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_2" value="0" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_1" value="0" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
|
|
<parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
|
|
<parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
|
|
<parameter name="ENUM_THLD_JAR1_4" value="THRESHOLD_32" />
|
|
<parameter name="MEM_RTT_NOM" value="ODT Disabled" />
|
|
<parameter name="ENUM_THLD_JAR1_5" value="THRESHOLD_32" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_4" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_3" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_5" value="0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS" value="2500" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
|
|
<parameter name="AFI_WRANK_WIDTH" value="2" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="LRDIMM" value="false" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="2500" />
|
|
<parameter name="MR1_DLL" value="0" />
|
|
<parameter name="CFG_ADDR_ORDER" value="0" />
|
|
<parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
|
|
<parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
|
|
<parameter name="ENUM_WR_PORT_INFO_0" value="USE_NO" />
|
|
<parameter name="CTL_ODT_ENABLED" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="SEQUENCER_TYPE" value="NIOS" />
|
|
<parameter name="ENUM_WR_PORT_INFO_5" value="USE_NO" />
|
|
<parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ENUM_WR_PORT_INFO_1" value="USE_NO" />
|
|
<parameter name="ENUM_WR_PORT_INFO_2" value="USE_NO" />
|
|
<parameter name="ENUM_WR_PORT_INFO_3" value="USE_NO" />
|
|
<parameter name="VFIFO_AS_SHIFT_REG" value="true" />
|
|
<parameter name="ENUM_WR_PORT_INFO_4" value="USE_NO" />
|
|
<parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
|
|
<parameter name="ENUM_THLD_JAR1_0" value="THRESHOLD_32" />
|
|
<parameter name="ENUM_THLD_JAR1_1" value="THRESHOLD_32" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
|
|
<parameter name="ENUM_THLD_JAR1_2" value="THRESHOLD_32" />
|
|
<parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
|
|
<parameter name="ENUM_THLD_JAR1_3" value="THRESHOLD_32" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
|
|
<parameter name="DLL_SHARING_MODE" value="None" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="ENUM_CPORT2_TYPE" value="DISABLE" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="2500" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="ENUM_ENABLE_ATPG" value="DISABLED" />
|
|
<parameter name="PLL_DR_CLK_MULT" value="0" />
|
|
<parameter name="USE_USER_RDIMM_VALUE" value="false" />
|
|
<parameter name="MEM_FORMAT" value="DISCRETE" />
|
|
<parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
|
|
<parameter name="CONTROLLER_TYPE" value="nextgen_v110" />
|
|
<parameter name="AFI_WLAT_WIDTH" value="6" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
|
|
<parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
|
|
<parameter name="RATE_CACHE" value="Half" />
|
|
<parameter name="COMMAND_PHASE" value="0.0" />
|
|
<parameter name="CTL_CS_WIDTH" value="1" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT" value="3" />
|
|
<parameter name="ENUM_OUTPUT_REGD" value="DISABLED" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
|
|
<parameter name="MR1_ODS" value="0" />
|
|
<parameter name="MEM_TRFC" value="34" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="AV_PORT_4_CONNECT_TO_CV_PORT" value="4" />
|
|
<parameter name="ENUM_SYNC_MODE_1" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_SYNC_MODE_0" value="ASYNCHRONOUS" />
|
|
<parameter name="ENUM_SYNC_MODE_3" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_SYNC_MODE_2" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CPORT1_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="ENUM_SYNC_MODE_5" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CPORT4_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="ENUM_SYNC_MODE_4" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="MEM_CK_PHASE" value="0.0" />
|
|
<parameter name="FORCE_DQS_TRACKING" value="AUTO" />
|
|
<parameter name="ENUM_CFG_TYPE" value="DDR3" />
|
|
<parameter name="CV_ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="0.02286" />
|
|
<parameter name="ADDR_ORDER" value="0" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_VERBOSE" value="true" />
|
|
<parameter name="HARD_PHY" value="false" />
|
|
<parameter name="MR2_SRF" value="0" />
|
|
<parameter name="ENUM_CPORT4_TYPE" value="DISABLE" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="false" />
|
|
<parameter name="ENUM_MEM_IF_BANKADDR_WIDTH" value="ADDR_WIDTH_3" />
|
|
<parameter name="ENUM_MASK_SBE_INTR" value="DISABLED" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK" value="0" />
|
|
<parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
|
|
<parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
|
|
<parameter name="ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_READ_ODT_CHIP" value="ODT_DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
|
|
<parameter name="VECT_ATTR_COUNTER_ONE_MASK" value="0" />
|
|
<parameter name="MULTICAST_EN" value="false" />
|
|
<parameter name="VCALIB_COUNT_WIDTH" value="2" />
|
|
<parameter name="CV_ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
|
|
<parameter name="OCT_TERM_CONTROL_WIDTH" value="14" />
|
|
<parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="DLL_USE_DR_CLK" value="false" />
|
|
<parameter name="ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="AC_PARITY" value="false" />
|
|
<parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
|
|
<parameter name="MR1_DQS" value="0" />
|
|
<parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES" value="DISABLED" />
|
|
<parameter name="MR2_SRT" value="0" />
|
|
<parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
|
|
<parameter name="ENUM_MEM_IF_TMRD" value="" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_3" value="5" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_2" value="5" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_5" value="5" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_4" value="5" />
|
|
<parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
|
|
<parameter name="MR1_QOFF" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="TB_MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="DLL_DELAY_CTRL_WIDTH" value="6" />
|
|
<parameter name="MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="MEM_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="CV_ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="USE_FAKE_PHY" value="false" />
|
|
<parameter name="ENUM_MEM_IF_TWR" value="TWR_6" />
|
|
<parameter name="SEQ_MODE" value="0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
|
|
<parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
|
|
<parameter name="ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="MEM_TYPE" value="DDR3" />
|
|
<parameter name="REF_CLK_PS" value="10000.0" />
|
|
<parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="ENUM_MEM_IF_TRAS" value="TRAS_16" />
|
|
<parameter name="ENUM_INC_SYNC" value="FIFO_SET_2" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
|
|
<parameter name="ENUM_MEM_IF_TRCD" value="TRCD_6" />
|
|
<parameter name="MARGIN_VARIATION_TEST" value="false" />
|
|
<parameter name="TIMING_TIS" value="170" />
|
|
<parameter name="ENUM_PRIORITY_0_4" value="WEIGHT_0" />
|
|
<parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
|
|
<parameter name="ENUM_PRIORITY_0_5" value="WEIGHT_0" />
|
|
<parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
|
|
<parameter name="ENUM_PRIORITY_0_2" value="WEIGHT_0" />
|
|
<parameter name="IO_IN_DELAY_MAX" value="15" />
|
|
<parameter name="ENUM_PRIORITY_0_3" value="WEIGHT_0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID" value="0" />
|
|
<parameter name="ENUM_PRIORITY_0_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_0_1" value="WEIGHT_0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR" value="0" />
|
|
<parameter name="FAST_SIM_CALIBRATION" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
|
|
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="0 ps" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="AVL_ADDR_WIDTH" value="25" />
|
|
<parameter name="CV_ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="MAX10_CFG" value="true" />
|
|
<parameter name="CFG_REORDER_DATA" value="true" />
|
|
<parameter name="ENUM_ENABLE_FAST_EXIT_PPD" value="DISABLED" />
|
|
<parameter name="DELAY_BUFFER_MODE" value="HIGH" />
|
|
<parameter name="ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
|
|
<parameter name="CONTINUE_AFTER_CAL_FAIL" value="false" />
|
|
<parameter name="AFI_RRANK_WIDTH" value="2" />
|
|
<parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="MR3_MPR" value="0" />
|
|
<parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
|
|
<parameter name="ENUM_CFG_STARVE_LIMIT" value="STARVE_LIMIT_32" />
|
|
<parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
|
|
<parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="MEM_IF_ODT_WIDTH" value="1" />
|
|
<parameter name="TIMING_TDQSCKDL" value="1200" />
|
|
<parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
|
|
<parameter name="TIMING_TDQSCKDS" value="450" />
|
|
<parameter name="TIMING_TDQSCKDM" value="900" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="TIMING_BOARD_TIS" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="ENUM_MEM_IF_TCCD" value="TCCD_4" />
|
|
<parameter name="CV_ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="NIOS_HEX_FILE_LOCATION" value="../" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="0 ps" />
|
|
<parameter name="AVL_BE_WIDTH" value="4" />
|
|
<parameter name="AVL_MAX_SIZE" value="4" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="TIMING_BOARD_TIH" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_MULT" value="3" />
|
|
<parameter name="ENUM_CTL_USR_REFRESH" value="CTL_USR_REFRESH_DISABLED" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="TIMING_BOARD_TDS" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="CV_ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
|
|
<parameter name="CFG_ERRCMD_FIFO_REG" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="TIMING_BOARD_TDH" value="0.0" />
|
|
<parameter name="PACKAGE_DESKEW" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="TRACKING_WATCH_TEST" value="false" />
|
|
<parameter name="ENUM_DISABLE_MERGING" value="MERGING_ENABLED" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CTL_ADDR_ORDER" value="CHIP_BANK_ROW_COL" />
|
|
<parameter name="AFI_DM_WIDTH" value="4" />
|
|
<parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV" value="0" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
|
|
<parameter name="ENUM_CTL_ECC_ENABLED" value="CTL_ECC_DISABLED" />
|
|
<parameter name="USE_SHADOW_REGS" value="false" />
|
|
<parameter name="BYTE_ENABLE" value="true" />
|
|
<parameter name="ENUM_MEM_IF_CS_WIDTH" value="MEM_IF_CS_WIDTH_1" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="CV_ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="ENUM_CAL_REQ" value="DISABLED" />
|
|
<parameter name="ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="MEM_IF_DQ_WIDTH" value="8" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
|
|
<parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
|
|
<parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="ADDR_CMD_DDR" value="0" />
|
|
<parameter name="GENERIC_PLL" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="ENABLE_NON_DES_CAL" value="false" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="MR3_MPR_AA" value="0" />
|
|
<parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_1" value="0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_0" value="0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_3" value="0" />
|
|
<parameter name="MEM_TFAW_NS" value="30.0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_2" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ" value="300.0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_5" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_4" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_3" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_2" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_1" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_0" value="0" />
|
|
<parameter name="REF_CLK_NS" value="10.0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_5" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_4" value="0" />
|
|
<parameter name="AFI_CLK_EN_WIDTH" value="2" />
|
|
<parameter name="TIMING_TQH" value="0.38" />
|
|
<parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_CLK_CACHE_VALID" value="true" />
|
|
<parameter name="ENUM_MEM_IF_DWIDTH" value="MEM_IF_DWIDTH_32" />
|
|
<parameter name="ENUM_RD_PORT_INFO_2" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_PORT_INFO_3" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="ENUM_RD_PORT_INFO_4" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
|
|
<parameter name="ENUM_MEM_IF_SPEEDBIN" value="DDR3_1066_6_6_6" />
|
|
<parameter name="ENUM_RD_PORT_INFO_5" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
|
|
<parameter name="ENUM_CPORT0_TYPE" value="DISABLE" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_2" value="WEIGHT_0" />
|
|
<parameter name="PLL_HR_CLK_MULT" value="0" />
|
|
<parameter name="ENUM_MEM_IF_TRP" value="TRP_6" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_1" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="HHP_HPS" value="false" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_5" value="WEIGHT_0" />
|
|
<parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="CV_ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
|
|
<parameter name="ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="AVL_SIZE_WIDTH" value="3" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING" value="0" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
|
|
<parameter name="RDBUFFER_ADDR_WIDTH" value="7" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
|
|
<parameter name="ENUM_MEM_IF_TRC" value="TRC_22" />
|
|
<parameter name="ENUM_RD_PORT_INFO_0" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_PORT_INFO_1" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
|
|
<parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
|
|
<parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="DAT_DATA_WIDTH" value="32" />
|
|
<parameter
|
|
name="CPORT_TYPE_PORT"
|
|
value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
|
|
<parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
|
|
<parameter name="AC_ROM_MR1_CALIB" value="" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_5" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_4" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_3" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_2" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_1" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_0" value="1" />
|
|
<parameter name="SPEED_GRADE" value="6" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_2" value="WEIGHT_0" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ" value="0.0" />
|
|
<parameter name="ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_1" value="WEIGHT_0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="0" />
|
|
<parameter name="MEM_TRCD_NS" value="13.75" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="ENUM_PRIORITY_4_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_3" value="WEIGHT_0" />
|
|
<parameter name="AFI_ADDR_WIDTH" value="28" />
|
|
<parameter name="ENUM_PRIORITY_4_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_1" value="WEIGHT_0" />
|
|
<parameter name="USE_HPS_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="EXPORT_CSR_PORT" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="2500 ps" />
|
|
<parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
|
|
<parameter name="CTL_SELF_REFRESH_EN" value="false" />
|
|
<parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
|
|
<parameter name="MSB_WFIFO_PORT_0" value="5" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_5" value="5" />
|
|
<parameter name="MSB_WFIFO_PORT_1" value="5" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="TIMING_TDS" value="10" />
|
|
<parameter name="MSB_WFIFO_PORT_2" value="5" />
|
|
<parameter name="MSB_WFIFO_PORT_3" value="5" />
|
|
<parameter name="MEM_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="MSB_WFIFO_PORT_4" value="5" />
|
|
<parameter name="MSB_WFIFO_PORT_5" value="5" />
|
|
<parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="CFG_TCCD" value="1" />
|
|
<parameter name="ENUM_MEM_IF_AL" value="AL_0" />
|
|
<parameter name="ENUM_TEST_MODE" value="NORMAL_MODE" />
|
|
<parameter name="MEM_CS_WIDTH" value="1" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_0" value="5" />
|
|
<parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
|
|
<parameter name="ENUM_CPORT0_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_2" value="5" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_1" value="5" />
|
|
<parameter name="TIMING_TDH" value="45" />
|
|
<parameter name="AV_PORT_3_CONNECT_TO_CV_PORT" value="3" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_4" value="5" />
|
|
<parameter name="SCC_DATA_WIDTH" value="1" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_3" value="5" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC" value="0" />
|
|
<parameter name="CV_ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ" value="300.0" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="MEM_TREFI_US" value="7.8" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="USE_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_LRDIMM_ENABLED" value="false" />
|
|
<parameter name="TIMING_BOARD_TIS_APPLIED" value="0.32" />
|
|
<parameter name="ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.04429" />
|
|
<parameter name="ENUM_MEM_IF_DQS_WIDTH" value="DQS_WIDTH_4" />
|
|
<parameter name="CTL_ZQCAL_EN" value="false" />
|
|
<parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
|
|
<parameter name="ENUM_DFX_BYPASS_ENABLE" value="DFX_BYPASS_DISABLED" />
|
|
<parameter name="AC_ROM_MR0_CALIB" value="" />
|
|
<parameter name="MEM_TWR_NS" value="15.0" />
|
|
<parameter name="ENUM_CTRL_WIDTH" value="DATA_WIDTH_64_BIT" />
|
|
<parameter name="MEM_T_WL" value="5" />
|
|
<parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_5" value="WEIGHT_0" />
|
|
<parameter name="AFI_RLAT_WIDTH" value="6" />
|
|
<parameter name="CV_ENUM_CPORT2_TYPE" value="DISABLE" />
|
|
<parameter name="ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="MEM_TRP" value="5" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR" value="0" />
|
|
<parameter name="MEM_CLK_PS" value="3333.0" />
|
|
<parameter name="IS_ES_DEVICE_CACHE" value="false" />
|
|
<parameter name="PLL_AFI_CLK_FREQ" value="150.0" />
|
|
<parameter name="ENUM_USE_ALMOST_EMPTY_1" value="EMPTY" />
|
|
<parameter name="ENUM_USE_ALMOST_EMPTY_2" value="EMPTY" />
|
|
<parameter name="ENUM_USE_ALMOST_EMPTY_3" value="EMPTY" />
|
|
<parameter name="MEM_TRRD_NS" value="6.0" />
|
|
<parameter name="CV_PORT_3_CONNECT_TO_AV_PORT" value="3" />
|
|
<parameter name="ENUM_DELAY_BONDING" value="BONDING_LATENCY_0" />
|
|
<parameter name="ENUM_USE_ALMOST_EMPTY_0" value="EMPTY" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="270.0" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="DQS_IN_DELAY_MAX" value="15" />
|
|
<parameter name="LSB_WFIFO_PORT_4" value="5" />
|
|
<parameter name="LSB_WFIFO_PORT_5" value="5" />
|
|
<parameter name="LSB_WFIFO_PORT_2" value="5" />
|
|
<parameter name="LSB_WFIFO_PORT_3" value="5" />
|
|
<parameter name="MR0_CAS_LATENCY" value="1" />
|
|
<parameter name="LSB_WFIFO_PORT_0" value="5" />
|
|
<parameter name="LSB_WFIFO_PORT_1" value="5" />
|
|
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.0" />
|
|
<parameter name="CFG_PDN_EXIT_CYCLES" value="10" />
|
|
<parameter name="MR0_WR" value="1" />
|
|
<parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_0" value="WEIGHT_0" />
|
|
<parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_2" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_1" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_3" value="WEIGHT_0" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="LOCAL_ID_WIDTH" value="8" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="TIMING_TDQSS" value="0.27" />
|
|
<parameter name="TIMING_TDQSQ" value="100" />
|
|
<parameter name="ENUM_PRIORITY_2_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_2_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_PRIORITY_2_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_2_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_2_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="ENUM_PRIORITY_2_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="USE_2X_FF" value="false" />
|
|
<parameter name="MEM_ASR" value="Manual" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_2" value="FALSE" />
|
|
<parameter name="PLL_DR_CLK_FREQ" value="0.0" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_3" value="FALSE" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_0" value="FALSE" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_1" value="FALSE" />
|
|
<parameter name="ADVANCED_CK_PHASES" value="false" />
|
|
<parameter name="ENUM_REORDER_DATA" value="DATA_REORDERING" />
|
|
<parameter name="NEXTGEN" value="true" />
|
|
<parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
|
|
<parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
|
|
<parameter name="PRIORITY_PORT_0" value="0" />
|
|
<parameter name="MEM_T_RL" value="5" />
|
|
<parameter name="MEM_TWR" value="5" />
|
|
<parameter name="PRIORITY_PORT_2" value="0" />
|
|
<parameter name="PRIORITY_PORT_1" value="0" />
|
|
<parameter name="USE_DR_CLK" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="2500" />
|
|
<parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
|
|
<parameter name="ENABLE_EMIT_JTAG_MASTER" value="false" />
|
|
<parameter name="CPORT_TYPE_PORT_3" value="0" />
|
|
<parameter name="MEM_IF_DQS_WIDTH" value="1" />
|
|
<parameter name="CPORT_TYPE_PORT_2" value="0" />
|
|
<parameter name="CPORT_TYPE_PORT_1" value="0" />
|
|
<parameter name="TIMING_TIH" value="120" />
|
|
<parameter name="CPORT_TYPE_PORT_0" value="0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="USE_AXI_ADAPTOR" value="false" />
|
|
<parameter name="PRIORITY_PORT_4" value="0" />
|
|
<parameter name="PRIORITY_PORT_3" value="0" />
|
|
<parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
|
|
<parameter name="PRIORITY_PORT_5" value="0" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
|
|
<parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
|
|
<parameter name="ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
|
|
<parameter name="NUM_OF_PORTS" value="1" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_5" value="WEIGHT_0" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
|
|
<parameter name="ENUM_CPORT3_TYPE" value="DISABLE" />
|
|
<parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="CPORT_TYPE_PORT_5" value="0" />
|
|
<parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
|
|
<parameter name="CPORT_TYPE_PORT_4" value="0" />
|
|
<parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
|
|
<parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_1" value="5" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_0" value="5" />
|
|
<parameter name="PLL_AFI_CLK_DIV" value="2" />
|
|
<parameter name="ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_5" value="5" />
|
|
<parameter name="MEM_TFAW" value="10" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_4" value="5" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_3" value="5" />
|
|
<parameter name="CV_ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_2" value="5" />
|
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram.v"
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type="VERILOG" />
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type="SYSTEM_VERILOG"
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attributes="" />
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<file
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attributes="" />
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attributes="" />
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<file
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attributes="" />
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<file
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attributes="" />
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attributes="" />
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<file
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attributes="" />
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attributes="" />
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attributes="" />
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<file
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attributes="" />
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<file
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sdc"
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attributes="" />
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr_controller_110/rtl/alt_mem_ddrx_mm_st_converter/alt_mem_ddrx_mm_st_converter_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys" as="ddr3_ram" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 29 starting:altera_mem_if_ddr3_emif "submodules/q_sys_ddr3_ram"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>14</b> modules, <b>31</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_pll</b> "<b>submodules/q_sys_ddr3_ram_pll0</b>"]]></message>
|
|
<message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_phy_core</b> "<b>submodules/q_sys_ddr3_ram_p0</b>"]]></message>
|
|
<message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_afi_mux</b> "<b>submodules/afi_mux_ddr3_ddrx</b>"]]></message>
|
|
<message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_ddr3_qseq</b> "<b>submodules/q_sys_ddr3_ram_s0</b>"]]></message>
|
|
<message level="Debug" culprit="ddr3_ram"><![CDATA["<b>ddr3_ram</b>" reuses <b>altera_mem_if_nextgen_ddr3_controller</b> "<b>submodules/q_sys_ddr3_ram_c0</b>"]]></message>
|
|
<message level="Info" culprit="ddr3_ram"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>ddr3_ram</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 232 starting:altera_mem_if_ddr3_pll "submodules/q_sys_ddr3_ram_pll0"</message>
|
|
<message level="Info" culprit="pll0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 231 starting:altera_mem_if_ddr3_phy_core "submodules/q_sys_ddr3_ram_p0"</message>
|
|
<message level="Info" culprit="p0">Generating clock pair generator</message>
|
|
<message level="Info" culprit="p0">Generating altgpio</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0">*****************************</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0">Remember to run the q_sys_ddr3_ram_p0_pin_assignments.tcl</message>
|
|
<message level="Info" culprit="p0">script after running Synthesis and before Fitting.</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0">*****************************</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 230 starting:altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx"</message>
|
|
<message level="Info" culprit="m0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 229 starting:altera_mem_if_ddr3_qseq "submodules/q_sys_ddr3_ram_s0"</message>
|
|
<message level="Info" culprit="s0">Generating Qsys sequencer system</message>
|
|
<message level="Info" culprit="s0">QSYS sequencer system generated successfully</message>
|
|
<message level="Info" culprit="s0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 228 starting:altera_mem_if_nextgen_ddr3_controller "submodules/q_sys_ddr3_ram_c0"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>8</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>submodules/alt_mem_if_nextgen_ddr3_controller_core</b>"]]></message>
|
|
<message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>alt_mem_ddrx_mm_st_converter</b> "<b>submodules/alt_mem_ddrx_mm_st_converter</b>"]]></message>
|
|
<message level="Info" culprit="c0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller</b> "<b>c0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 6 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core"</message>
|
|
<message level="Info" culprit="ng0"><![CDATA["<b>c0</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>ng0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 5 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter"</message>
|
|
<message level="Info" culprit="a0"><![CDATA["<b>c0</b>" instantiated <b>alt_mem_ddrx_mm_st_converter</b> "<b>a0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_uart:19.1:baud=115200,baudError=0.01,clockRate=50000000,dataBits=8,fixedBaud=true,parity=NONE,parityFisrtChar=N,simCharStream=,simInteractiveInputEnable=false,simInteractiveOutputEnable=false,simTrueBaud=false,stopBits=1,syncRegDepth=2,useCtsRts=false,useEopRegister=false,useRelativePathForSimFile=false"
|
|
instancePathKey="q_sys:.:debug_uart"
|
|
kind="altera_avalon_uart"
|
|
version="19.1"
|
|
name="q_sys_debug_uart">
|
|
<parameter name="baud" value="115200" />
|
|
<parameter name="simInteractiveInputEnable" value="false" />
|
|
<parameter name="useRelativePathForSimFile" value="false" />
|
|
<parameter name="stopBits" value="1" />
|
|
<parameter name="parityFisrtChar" value="N" />
|
|
<parameter name="parity" value="NONE" />
|
|
<parameter name="useCtsRts" value="false" />
|
|
<parameter name="fixedBaud" value="true" />
|
|
<parameter name="dataBits" value="8" />
|
|
<parameter name="clockRate" value="50000000" />
|
|
<parameter name="simTrueBaud" value="false" />
|
|
<parameter name="useEopRegister" value="false" />
|
|
<parameter name="simInteractiveOutputEnable" value="false" />
|
|
<parameter name="syncRegDepth" value="2" />
|
|
<parameter name="simCharStream" value="" />
|
|
<parameter name="baudError" value="0.01" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_debug_uart.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_uart/altera_avalon_uart_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="debug_uart" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 33 starting:altera_avalon_uart "submodules/q_sys_debug_uart"</message>
|
|
<message level="Info" culprit="debug_uart">Starting RTL generation for module 'q_sys_debug_uart'</message>
|
|
<message level="Info" culprit="debug_uart"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=q_sys_debug_uart --dir=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen//q_sys_debug_uart_component_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="debug_uart">Done RTL generation for module 'q_sys_debug_uart'</message>
|
|
<message level="Info" culprit="debug_uart"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_uart</b> "<b>debug_uart</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_onchip_memory2:19.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=q_sys_descriptor_memory,blockType=AUTO,copyInitFile=false,dataWidth=32,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=Automatic,derived_init_file_name=q_sys_descriptor_memory.hex,derived_is_hardcopy=false,derived_set_addr_width=11,derived_set_addr_width2=11,derived_set_data_width=32,derived_set_data_width2=32,derived_singleClockOperation=false,deviceFamily=MAX 10,deviceFeatures=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dualPort=false,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=false,initializationFileName=/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex,instanceID=NONE,memorySize=8192,readDuringWriteMode=DONT_CARE,resetrequest_enabled=true,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true"
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instancePathKey="q_sys:.:descriptor_memory"
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kind="altera_avalon_onchip_memory2"
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version="19.1"
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name="q_sys_descriptor_memory">
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<parameter name="derived_singleClockOperation" value="false" />
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<parameter name="derived_is_hardcopy" value="false" />
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<parameter
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name="deviceFeatures"
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value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
|
|
<parameter name="autoInitializationFileName" value="q_sys_descriptor_memory" />
|
|
<parameter name="derived_gui_ram_block_type" value="Automatic" />
|
|
<parameter name="enPRInitMode" value="false" />
|
|
<parameter name="useShallowMemBlocks" value="false" />
|
|
<parameter name="writable" value="true" />
|
|
<parameter name="dualPort" value="false" />
|
|
<parameter name="derived_set_addr_width2" value="11" />
|
|
<parameter name="dataWidth" value="32" />
|
|
<parameter name="allowInSystemMemoryContentEditor" value="false" />
|
|
<parameter name="derived_set_addr_width" value="11" />
|
|
<parameter name="derived_init_file_name" value="q_sys_descriptor_memory.hex" />
|
|
<parameter
|
|
name="initializationFileName"
|
|
value="/data/acastill/simple_socket_10M50/software/niosII_simple_socket_server/mem_init/q_sys_descriptor_memory.hex" />
|
|
<parameter name="singleClockOperation" value="false" />
|
|
<parameter name="derived_set_data_width2" value="32" />
|
|
<parameter name="readDuringWriteMode" value="DONT_CARE" />
|
|
<parameter name="blockType" value="AUTO" />
|
|
<parameter name="derived_enableDiffWidth" value="false" />
|
|
<parameter name="useNonDefaultInitFile" value="false" />
|
|
<parameter name="resetrequest_enabled" value="true" />
|
|
<parameter name="simMemInitOnlyFilename" value="0" />
|
|
<parameter name="copyInitFile" value="false" />
|
|
<parameter name="deviceFamily" value="MAX 10" />
|
|
<parameter name="simAllowMRAMContentsFile" value="false" />
|
|
<parameter name="ecc_enabled" value="false" />
|
|
<parameter name="derived_set_data_width" value="32" />
|
|
<parameter name="instanceID" value="NONE" />
|
|
<parameter name="memorySize" value="8192" />
|
|
<parameter name="dataWidth2" value="32" />
|
|
<parameter name="enableDiffWidth" value="false" />
|
|
<parameter name="initMemContent" value="false" />
|
|
<parameter name="slave1Latency" value="1" />
|
|
<parameter name="slave2Latency" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_descriptor_memory.v"
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|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
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</sourceFiles>
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|
<childSourceFiles/>
|
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<instantiator instantiator="q_sys" as="descriptor_memory" />
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|
<messages>
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|
<message level="Debug" culprit="q_sys">queue size: 32 starting:altera_avalon_onchip_memory2 "submodules/q_sys_descriptor_memory"</message>
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<message level="Info" culprit="descriptor_memory">Starting RTL generation for module 'q_sys_descriptor_memory'</message>
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|
<message level="Info" culprit="descriptor_memory"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_descriptor_memory --dir=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen//q_sys_descriptor_memory_component_configuration.pl --do_build_sim=0 ]</message>
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<message level="Info" culprit="descriptor_memory">Done RTL generation for module 'q_sys_descriptor_memory'</message>
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<message level="Info" culprit="descriptor_memory"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>descriptor_memory</b>"]]></message>
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</messages>
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</entity>
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<entity
|
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path="submodules/"
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|
parameterizationKey="altpll:19.1:AUTO_DEVICE_FAMILY=MAX 10,AUTO_INCLK_INTERFACE_CLOCK_RATE=50000000,AVALON_USE_SEPARATE_SYSCLK=NO,BANDWIDTH=,BANDWIDTH_TYPE=AUTO,CLK0_DIVIDE_BY=2,CLK0_DUTY_CYCLE=50,CLK0_MULTIPLY_BY=5,CLK0_PHASE_SHIFT=0,CLK1_DIVIDE_BY=2,CLK1_DUTY_CYCLE=50,CLK1_MULTIPLY_BY=1,CLK1_PHASE_SHIFT=0,CLK2_DIVIDE_BY=20,CLK2_DUTY_CYCLE=50,CLK2_MULTIPLY_BY=1,CLK2_PHASE_SHIFT=0,CLK3_DIVIDE_BY=2,CLK3_DUTY_CYCLE=50,CLK3_MULTIPLY_BY=5,CLK3_PHASE_SHIFT=-3000,CLK4_DIVIDE_BY=2,CLK4_DUTY_CYCLE=50,CLK4_MULTIPLY_BY=1,CLK4_PHASE_SHIFT=-10000,CLK5_DIVIDE_BY=,CLK5_DUTY_CYCLE=,CLK5_MULTIPLY_BY=,CLK5_PHASE_SHIFT=,CLK6_DIVIDE_BY=,CLK6_DUTY_CYCLE=,CLK6_MULTIPLY_BY=,CLK6_PHASE_SHIFT=,CLK7_DIVIDE_BY=,CLK7_DUTY_CYCLE=,CLK7_MULTIPLY_BY=,CLK7_PHASE_SHIFT=,CLK8_DIVIDE_BY=,CLK8_DUTY_CYCLE=,CLK8_MULTIPLY_BY=,CLK8_PHASE_SHIFT=,CLK9_DIVIDE_BY=,CLK9_DUTY_CYCLE=,CLK9_MULTIPLY_BY=,CLK9_PHASE_SHIFT=,COMPENSATE_CLOCK=CLK0,DOWN_SPREAD=,DPA_DIVIDER=,DPA_DIVIDE_BY=,DPA_MULTIPLY_BY=,ENABLE_SWITCH_OVER_COUNTER=,EXTCLK0_DIVIDE_BY=,EXTCLK0_DUTY_CYCLE=,EXTCLK0_MULTIPLY_BY=,EXTCLK0_PHASE_SHIFT=,EXTCLK1_DIVIDE_BY=,EXTCLK1_DUTY_CYCLE=,EXTCLK1_MULTIPLY_BY=,EXTCLK1_PHASE_SHIFT=,EXTCLK2_DIVIDE_BY=,EXTCLK2_DUTY_CYCLE=,EXTCLK2_MULTIPLY_BY=,EXTCLK2_PHASE_SHIFT=,EXTCLK3_DIVIDE_BY=,EXTCLK3_DUTY_CYCLE=,EXTCLK3_MULTIPLY_BY=,EXTCLK3_PHASE_SHIFT=,FEEDBACK_SOURCE=,GATE_LOCK_COUNTER=,GATE_LOCK_SIGNAL=,HIDDEN_CONSTANTS=CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED,HIDDEN_CUSTOM_ELABORATION=altpll_avalon_elaboration,HIDDEN_CUSTOM_POST_EDIT=altpll_avalon_post_edit,HIDDEN_IF_PORTS=IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0},HIDDEN_IS_FIRST_EDIT=0,HIDDEN_IS_NUMERIC=IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1,HIDDEN_MF_PORTS=MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1,HIDDEN_PRIVATES=PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0,HIDDEN_USED_PORTS=UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used,INCLK0_INPUT_FREQUENCY=20000,INCLK1_INPUT_FREQUENCY=,INTENDED_DEVICE_FAMILY=MAX 10,INVALID_LOCK_MULTIPLIER=,LOCK_HIGH=,LOCK_LOW=,OPERATION_MODE=NO_COMPENSATION,PLL_TYPE=AUTO,PORT_ACTIVECLOCK=PORT_UNUSED,PORT_ARESET=PORT_UNUSED,PORT_CLKBAD0=PORT_UNUSED,PORT_CLKBAD1=PORT_UNUSED,PORT_CLKLOSS=PORT_UNUSED,PORT_CLKSWITCH=PORT_UNUSED,PORT_CONFIGUPDATE=PORT_UNUSED,PORT_ENABLE0=,PORT_ENABLE1=,PORT_FBIN=PORT_UNUSED,PORT_FBOUT=,PORT_INCLK0=PORT_USED,PORT_INCLK1=PORT_UNUSED,PORT_LOCKED=PORT_USED,PORT_PFDENA=PORT_UNUSED,PORT_PHASECOUNTERSELECT=PORT_UNUSED,PORT_PHASEDONE=PORT_UNUSED,PORT_PHASESTEP=PORT_UNUSED,PORT_PHASEUPDOWN=PORT_UNUSED,PORT_PLLENA=PORT_UNUSED,PORT_SCANACLR=PORT_UNUSED,PORT_SCANCLK=PORT_UNUSED,PORT_SCANCLKENA=PORT_UNUSED,PORT_SCANDATA=PORT_UNUSED,PORT_SCANDATAOUT=PORT_UNUSED,PORT_SCANDONE=PORT_UNUSED,PORT_SCANREAD=PORT_UNUSED,PORT_SCANWRITE=PORT_UNUSED,PORT_SCLKOUT0=,PORT_SCLKOUT1=,PORT_VCOOVERRANGE=,PORT_VCOUNDERRANGE=,PORT_clk0=PORT_USED,PORT_clk1=PORT_USED,PORT_clk2=PORT_USED,PORT_clk3=PORT_USED,PORT_clk4=PORT_USED,PORT_clk5=PORT_UNUSED,PORT_clk6=,PORT_clk7=,PORT_clk8=,PORT_clk9=,PORT_clkena0=PORT_UNUSED,PORT_clkena1=PORT_UNUSED,PORT_clkena2=PORT_UNUSED,PORT_clkena3=PORT_UNUSED,PORT_clkena4=PORT_UNUSED,PORT_clkena5=PORT_UNUSED,PORT_extclk0=PORT_UNUSED,PORT_extclk1=PORT_UNUSED,PORT_extclk2=PORT_UNUSED,PORT_extclk3=PORT_UNUSED,PORT_extclkena0=,PORT_extclkena1=,PORT_extclkena2=,PORT_extclkena3=,PRIMARY_CLOCK=,QUALIFY_CONF_DONE=,SCAN_CHAIN=,SCAN_CHAIN_MIF_FILE=,SCLKOUT0_PHASE_SHIFT=,SCLKOUT1_PHASE_SHIFT=,SELF_RESET_ON_GATED_LOSS_LOCK=,SELF_RESET_ON_LOSS_LOCK=,SKIP_VCO=,SPREAD_FREQUENCY=,SWITCH_OVER_COUNTER=,SWITCH_OVER_ON_GATED_LOCK=,SWITCH_OVER_ON_LOSSCLK=,SWITCH_OVER_TYPE=,USING_FBMIMICBIDIR_PORT=,VALID_LOCK_MULTIPLIER=,VCO_DIVIDE_BY=,VCO_FREQUENCY_CONTROL=,VCO_MULTIPLY_BY=,VCO_PHASE_SHIFT_STEP=,WIDTH_CLOCK=5,WIDTH_PHASECOUNTERSELECT="
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instancePathKey="q_sys:.:enet_pll"
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kind="altpll"
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version="19.1"
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name="q_sys_enet_pll">
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<parameter name="CLK3_PHASE_SHIFT" value="-3000" />
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<parameter name="PORT_LOCKED" value="PORT_USED" />
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<parameter name="CLK2_PHASE_SHIFT" value="0" />
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<parameter name="CLK4_PHASE_SHIFT" value="-10000" />
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<parameter name="CLK5_DUTY_CYCLE" value="" />
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<parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
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<parameter name="CLK1_PHASE_SHIFT" value="0" />
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<parameter name="CLK5_PHASE_SHIFT" value="" />
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<parameter name="HIDDEN_CUSTOM_ELABORATION" value="altpll_avalon_elaboration" />
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<parameter name="CLK8_DUTY_CYCLE" value="" />
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<parameter name="CLK0_DIVIDE_BY" value="2" />
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<parameter name="CLK7_PHASE_SHIFT" value="" />
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<parameter name="CLK0_PHASE_SHIFT" value="0" />
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<parameter name="CLK6_PHASE_SHIFT" value="" />
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<parameter name="CLK8_PHASE_SHIFT" value="" />
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<parameter name="PORT_clk8" value="" />
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<parameter name="INVALID_LOCK_MULTIPLIER" value="" />
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<parameter name="PORT_clk9" value="" />
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<parameter name="PORT_clk6" value="" />
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<parameter name="PORT_clk7" value="" />
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<parameter name="EXTCLK2_DIVIDE_BY" value="" />
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<parameter name="PORT_clk4" value="PORT_USED" />
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<parameter name="PORT_clk5" value="PORT_UNUSED" />
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<parameter name="PORT_clk2" value="PORT_USED" />
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<parameter name="EXTCLK3_DUTY_CYCLE" value="" />
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<parameter name="PORT_clk3" value="PORT_USED" />
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<parameter name="PORT_clk0" value="PORT_USED" />
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<parameter name="PORT_clk1" value="PORT_USED" />
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<parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
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<parameter name="PORT_extclkena0" value="" />
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<parameter name="SKIP_VCO" value="" />
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<parameter name="PORT_extclkena1" value="" />
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<parameter name="PORT_extclkena2" value="" />
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<parameter name="CLK2_DUTY_CYCLE" value="50" />
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<parameter name="PORT_extclkena3" value="" />
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<parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
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<parameter name="GATE_LOCK_SIGNAL" value="" />
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<parameter name="CLK7_DIVIDE_BY" value="" />
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<parameter name="CLK8_DIVIDE_BY" value="" />
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<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
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<parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
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<parameter name="PORT_ENABLE1" value="" />
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<parameter name="PORT_VCOUNDERRANGE" value="" />
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<parameter name="GATE_LOCK_COUNTER" value="" />
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<parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
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<parameter name="SWITCH_OVER_TYPE" value="" />
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<parameter name="PORT_ENABLE0" value="" />
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<parameter name="EXTCLK3_DIVIDE_BY" value="" />
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<parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
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<parameter name="CLK1_DIVIDE_BY" value="2" />
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<parameter name="CLK9_DIVIDE_BY" value="" />
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<parameter name="FEEDBACK_SOURCE" value="" />
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<parameter name="CLK1_DUTY_CYCLE" value="50" />
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<parameter name="BANDWIDTH_TYPE" value="AUTO" />
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<parameter name="SPREAD_FREQUENCY" value="" />
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<parameter name="PORT_PLLENA" value="PORT_UNUSED" />
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<parameter name="LOCK_HIGH" value="" />
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<parameter
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name="HIDDEN_USED_PORTS"
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value="UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used" />
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<parameter name="EXTCLK1_DIVIDE_BY" value="" />
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<parameter name="DOWN_SPREAD" value="" />
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<parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
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<parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
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<parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
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<parameter name="PORT_FBOUT" value="" />
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<parameter name="VCO_FREQUENCY_CONTROL" value="" />
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<parameter
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name="HIDDEN_IF_PORTS"
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value="IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}" />
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<parameter
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name="HIDDEN_MF_PORTS"
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value="MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1" />
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<parameter name="CLK9_PHASE_SHIFT" value="" />
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<parameter name="CLK6_DIVIDE_BY" value="" />
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<parameter name="CLK3_DIVIDE_BY" value="2" />
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<parameter name="EXTCLK0_MULTIPLY_BY" value="" />
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<parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
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<parameter name="BANDWIDTH" value="" />
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<parameter name="CLK0_DUTY_CYCLE" value="50" />
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<parameter name="WIDTH_CLOCK" value="5" />
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<parameter name="EXTCLK1_MULTIPLY_BY" value="" />
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<parameter name="VCO_PHASE_SHIFT_STEP" value="" />
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<parameter name="PLL_TYPE" value="AUTO" />
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<parameter name="EXTCLK2_MULTIPLY_BY" value="" />
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<parameter name="EXTCLK3_MULTIPLY_BY" value="" />
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<parameter name="CLK4_DIVIDE_BY" value="2" />
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<parameter name="PORT_FBIN" value="PORT_UNUSED" />
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<parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
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<parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
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<parameter name="PORT_VCOOVERRANGE" value="" />
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<parameter name="DPA_DIVIDE_BY" value="" />
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<parameter
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name="HIDDEN_PRIVATES"
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value="PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0" />
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<parameter name="VCO_DIVIDE_BY" value="" />
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|
<parameter name="CLK3_DUTY_CYCLE" value="50" />
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|
<parameter name="SCAN_CHAIN" value="" />
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|
<parameter name="LOCK_LOW" value="" />
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|
<parameter name="CLK0_MULTIPLY_BY" value="5" />
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|
<parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
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|
<parameter name="CLK1_MULTIPLY_BY" value="1" />
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|
<parameter name="PORT_SCLKOUT1" value="" />
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<parameter
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|
name="HIDDEN_IS_NUMERIC"
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|
value="IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1" />
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|
<parameter name="CLK3_MULTIPLY_BY" value="5" />
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|
<parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
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|
<parameter name="CLK2_MULTIPLY_BY" value="1" />
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|
<parameter name="CLK4_MULTIPLY_BY" value="1" />
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|
<parameter name="PORT_SCLKOUT0" value="" />
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|
<parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
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|
<parameter name="CLK4_DUTY_CYCLE" value="50" />
|
|
<parameter name="PORT_clkena0" value="PORT_UNUSED" />
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|
<parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
|
|
<parameter name="PORT_clkena1" value="PORT_UNUSED" />
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|
<parameter name="PORT_clkena2" value="PORT_UNUSED" />
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|
<parameter name="PORT_PFDENA" value="PORT_UNUSED" />
|
|
<parameter name="PORT_clkena3" value="PORT_UNUSED" />
|
|
<parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
|
|
<parameter name="CLK6_MULTIPLY_BY" value="" />
|
|
<parameter name="EXTCLK0_DIVIDE_BY" value="" />
|
|
<parameter name="CLK5_MULTIPLY_BY" value="" />
|
|
<parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="OPERATION_MODE" value="NO_COMPENSATION" />
|
|
<parameter name="EXTCLK2_DUTY_CYCLE" value="" />
|
|
<parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
|
|
<parameter name="SWITCH_OVER_COUNTER" value="" />
|
|
<parameter name="CLK7_MULTIPLY_BY" value="" />
|
|
<parameter name="PORT_clkena4" value="PORT_UNUSED" />
|
|
<parameter name="PORT_clkena5" value="PORT_UNUSED" />
|
|
<parameter name="SCAN_CHAIN_MIF_FILE" value="" />
|
|
<parameter name="CLK8_MULTIPLY_BY" value="" />
|
|
<parameter name="CLK9_MULTIPLY_BY" value="" />
|
|
<parameter name="EXTCLK2_PHASE_SHIFT" value="" />
|
|
<parameter name="COMPENSATE_CLOCK" value="CLK0" />
|
|
<parameter name="PORT_INCLK0" value="PORT_USED" />
|
|
<parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
|
|
<parameter name="EXTCLK3_PHASE_SHIFT" value="" />
|
|
<parameter name="PORT_INCLK1" value="PORT_UNUSED" />
|
|
<parameter name="CLK5_DIVIDE_BY" value="" />
|
|
<parameter name="CLK9_DUTY_CYCLE" value="" />
|
|
<parameter name="CLK6_DUTY_CYCLE" value="" />
|
|
<parameter name="DPA_DIVIDER" value="" />
|
|
<parameter name="VCO_MULTIPLY_BY" value="" />
|
|
<parameter name="EXTCLK1_PHASE_SHIFT" value="" />
|
|
<parameter
|
|
name="HIDDEN_CONSTANTS"
|
|
value="CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED" />
|
|
<parameter name="EXTCLK0_PHASE_SHIFT" value="" />
|
|
<parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
|
|
<parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
|
|
<parameter name="CLK2_DIVIDE_BY" value="20" />
|
|
<parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
|
|
<parameter name="USING_FBMIMICBIDIR_PORT" value="" />
|
|
<parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
|
|
<parameter name="QUALIFY_CONF_DONE" value="" />
|
|
<parameter name="PORT_ARESET" value="PORT_UNUSED" />
|
|
<parameter name="DPA_MULTIPLY_BY" value="" />
|
|
<parameter name="INCLK1_INPUT_FREQUENCY" value="" />
|
|
<parameter name="CLK7_DUTY_CYCLE" value="" />
|
|
<parameter name="EXTCLK0_DUTY_CYCLE" value="" />
|
|
<parameter name="HIDDEN_CUSTOM_POST_EDIT" value="altpll_avalon_post_edit" />
|
|
<parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
|
|
<parameter name="VALID_LOCK_MULTIPLIER" value="" />
|
|
<parameter name="PRIMARY_CLOCK" value="" />
|
|
<parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
|
|
<parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
|
|
<parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
|
|
<parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
|
|
<parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
|
|
<parameter name="PORT_extclk3" value="PORT_UNUSED" />
|
|
<parameter name="EXTCLK1_DUTY_CYCLE" value="" />
|
|
<parameter name="PORT_extclk0" value="PORT_UNUSED" />
|
|
<parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
|
|
<parameter name="PORT_extclk2" value="PORT_UNUSED" />
|
|
<parameter name="PORT_extclk1" value="PORT_UNUSED" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_enet_pll.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_altpll/altera_avalon_altpll_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="enet_pll" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 31 starting:altpll "submodules/q_sys_enet_pll"</message>
|
|
<message level="Debug">set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files</message>
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|
<message level="Debug">Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --source=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0010_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on</message>
|
|
<message level="Debug">Command took 1.135s</message>
|
|
<message level="Info" culprit="enet_pll"><![CDATA["<b>q_sys</b>" instantiated <b>altpll</b> "<b>enet_pll</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_eth_tse:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,XCVR_RCFG_JTAG_ENABLE=0,XCVR_SET_CAPABILITY_REG_ENABLE=0,XCVR_SET_CSR_SOFT_LOGIC_ENABLE=0,XCVR_SET_PRBS_SOFT_LOGIC_ENABLE=0,XCVR_SET_USER_IDENTIFIER=0,core_variation=MAC_ONLY,core_version=4865,dev_version=4865,deviceFamily=MAX10,deviceFamilyName=MAX 10,eg_addr=11,eg_fifo=2048,ena_hash=false,enable_alt_reconfig=false,enable_clk_sharing=false,enable_ecc=false,enable_ena=32,enable_gmii_loopback=true,enable_hd_logic=true,enable_lgth_check=true,enable_mac_flow_ctrl=false,enable_mac_vlan=false,enable_magic_detect=true,enable_padding=true,enable_ptp_1step=false,enable_sgmii=true,enable_shift16=true,enable_sup_addr=false,enable_timestamping=false,enable_use_internal_fifo=true,export_pwrdn=false,ext_stat_cnt_ena=false,gbit_only=true,ifGMII=RGMII,ing_addr=11,ing_fifo=2048,isUseMAC=true,isUsePCS=false,max_channels=1,mbit_only=true,mdio_clk_div=40,nf_lvds_iopll_num_channels=4,nf_phyip_rcfg_enable=true,phy_identifier=0,phyip_en_synce_support=false,phyip_pll_base_data_rate=1250 Mbps,phyip_pll_type=CMU,phyip_pma_bonding_mode=x1,reduced_control=false,reduced_interface_ena=true,starting_channel_number=0,stat_cnt_ena=true,synchronizer_depth=3,transceiver_type=NONE,tstamp_fp_width=4,useMDIO=true,use_mac_clken=false,use_misc_ports=true(altera_eth_tse_mac:19.1:CORE_VERSION=4865,CRC32CHECK16BIT=0,CRC32DWIDTH=8,CRC32GENDELAY=6,CRC32S1L2_EXTERN=false,CUST_VERSION=0,DEVICE_FAMILY=MAX10,EG_ADDR=11,EG_FIFO=2048,ENABLE_ECC=false,ENABLE_ENA=32,ENABLE_EXTENDED_STAT_REG=false,ENABLE_GMII_LOOPBACK=true,ENABLE_HD_LOGIC=true,ENABLE_LGTH_CHECK=true,ENABLE_MAC_FLOW_CTRL=false,ENABLE_MAC_RX_VLAN=false,ENABLE_MAC_TXADDR_SET=true,ENABLE_MAC_TX_VLAN=false,ENABLE_MAGIC_DETECT=true,ENABLE_MDIO=true,ENABLE_PADDING=true,ENABLE_SHIFT16=true,ENABLE_SUP_ADDR=false,ENA_HASH=false,GBIT_ONLY=true,ING_ADDR=11,ING_FIFO=2048,INSERT_TA=false,MBIT_ONLY=true,MDIO_CLK_DIV=40,RAM_TYPE=AUTO,REDUCED_CONTROL=false,REDUCED_INTERFACE_ENA=true,RESET_LEVEL=1,STAT_CNT_ENA=true,SYNCHRONIZER_DEPTH=3,USE_SYNC_RESET=true,connect_to_pcs=false,ifGMII=RGMII,use_mac_clken=false,use_misc_ports=true)(altera_gpio_lite:19.1:ASYNC_MODE=none,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=input,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=4,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=false,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=none,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=input,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=1,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=false,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=clear,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=output,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=4,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=true,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(altera_gpio_lite:19.1:ASYNC_MODE=clear,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=output,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=1,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=true,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)"
|
|
instancePathKey="q_sys:.:eth_tse"
|
|
kind="altera_eth_tse"
|
|
version="19.1"
|
|
name="q_sys_eth_tse">
|
|
<parameter name="enable_clk_sharing" value="false" />
|
|
<parameter name="enable_ptp_1step" value="false" />
|
|
<parameter name="phy_identifier" value="0" />
|
|
<parameter name="mdio_clk_div" value="40" />
|
|
<parameter name="gbit_only" value="true" />
|
|
<parameter name="starting_channel_number" value="0" />
|
|
<parameter name="enable_mac_flow_ctrl" value="false" />
|
|
<parameter name="enable_ecc" value="false" />
|
|
<parameter name="enable_magic_detect" value="true" />
|
|
<parameter name="synchronizer_depth" value="3" />
|
|
<parameter name="use_misc_ports" value="true" />
|
|
<parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
|
|
<parameter name="enable_hd_logic" value="true" />
|
|
<parameter name="phyip_en_synce_support" value="false" />
|
|
<parameter name="ena_hash" value="false" />
|
|
<parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
|
|
<parameter name="nf_phyip_rcfg_enable" value="true" />
|
|
<parameter name="reduced_interface_ena" value="true" />
|
|
<parameter name="deviceFamily" value="MAX10" />
|
|
<parameter name="core_version" value="4865" />
|
|
<parameter name="useMDIO" value="true" />
|
|
<parameter name="mbit_only" value="true" />
|
|
<parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE" value="0" />
|
|
<parameter name="enable_use_internal_fifo" value="true" />
|
|
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
|
|
<parameter name="stat_cnt_ena" value="true" />
|
|
<parameter name="nf_lvds_iopll_num_channels" value="4" />
|
|
<parameter name="core_variation" value="MAC_ONLY" />
|
|
<parameter name="enable_sup_addr" value="false" />
|
|
<parameter name="enable_ena" value="32" />
|
|
<parameter name="phyip_pma_bonding_mode" value="x1" />
|
|
<parameter name="isUseMAC" value="true" />
|
|
<parameter name="XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
|
|
<parameter name="ifGMII" value="RGMII" />
|
|
<parameter name="use_mac_clken" value="false" />
|
|
<parameter name="eg_fifo" value="2048" />
|
|
<parameter name="max_channels" value="1" />
|
|
<parameter name="phyip_pll_type" value="CMU" />
|
|
<parameter name="ext_stat_cnt_ena" value="false" />
|
|
<parameter name="enable_mac_vlan" value="false" />
|
|
<parameter name="deviceFamilyName" value="MAX 10" />
|
|
<parameter name="enable_alt_reconfig" value="false" />
|
|
<parameter name="ing_addr" value="11" />
|
|
<parameter name="enable_timestamping" value="false" />
|
|
<parameter name="reduced_control" value="false" />
|
|
<parameter name="XCVR_RCFG_JTAG_ENABLE" value="0" />
|
|
<parameter name="export_pwrdn" value="false" />
|
|
<parameter name="enable_sgmii" value="true" />
|
|
<parameter name="eg_addr" value="11" />
|
|
<parameter name="tstamp_fp_width" value="4" />
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
|
|
<parameter name="enable_gmii_loopback" value="true" />
|
|
<parameter name="enable_padding" value="true" />
|
|
<parameter name="dev_version" value="4865" />
|
|
<parameter name="transceiver_type" value="NONE" />
|
|
<parameter name="isUsePCS" value="false" />
|
|
<parameter name="enable_lgth_check" value="true" />
|
|
<parameter name="enable_shift16" value="true" />
|
|
<parameter name="ing_fifo" value="2048" />
|
|
<parameter name="XCVR_SET_USER_IDENTIFIER" value="0" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_eth_tse.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_mac.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_clk_cntl.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc328checker.v"
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|
type="VERILOG"
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|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc328generator.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc32ctl8.v"
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|
type="VERILOG"
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|
attributes="" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_crc32galois8.v"
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|
type="VERILOG"
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attributes="" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_gmii_io.v"
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type="VERILOG"
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attributes="" />
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<file
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lb_read_cntl.v"
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type="VERILOG"
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attributes="" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lb_wrt_cntl.v"
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|
type="VERILOG"
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attributes="" />
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<file
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_hashing.v"
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type="VERILOG"
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attributes="" />
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<file
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_host_control.v"
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type="VERILOG"
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attributes="" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_host_control_small.v"
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type="VERILOG"
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attributes="" />
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|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_control.v"
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|
type="VERILOG"
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attributes="" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_register_map.v"
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type="VERILOG"
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attributes="" />
|
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_register_map_small.v"
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type="VERILOG"
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attributes="" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_rx_counter_cntl.v"
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|
type="VERILOG"
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attributes="" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_shared_mac_control.v"
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type="VERILOG"
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attributes="" />
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<file
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_shared_register_map.v"
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type="VERILOG"
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attributes="" />
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|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_tx_counter_cntl.v"
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type="VERILOG"
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attributes="" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_lfsr_10.v"
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|
type="VERILOG"
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attributes="" />
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|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_loopback_ff.v"
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|
type="VERILOG"
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|
attributes="" />
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|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_altshifttaps.v"
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|
type="VERILOG"
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|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_fifoless_mac_rx.v"
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|
type="VERILOG"
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|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_rx.v"
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|
type="VERILOG"
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attributes="" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_fifoless_mac_tx.v"
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|
type="VERILOG"
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|
attributes="" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mac_tx.v"
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|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_magic_detection.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio_clk_gen.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mdio_cntl.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_mdio.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mii_rx_if.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_mii_tx_if.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_pipeline_base.v"
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|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_pipeline_stage.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_dpram_16x32.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/ethernet/altera_eth_tse/altera_eth_tse_hw.tcl" />
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<instantiator instantiator="q_sys" as="eth_tse" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 30 starting:altera_eth_tse "submodules/q_sys_eth_tse"</message>
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|
<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
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<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>14</b> connections]]></message>
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<message level="Debug">Transform: MMTransform</message>
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<message level="Debug">Transform: InterruptMapperTransform</message>
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<message level="Debug">Transform: InterruptSyncTransform</message>
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<message level="Debug">Transform: InterruptFanoutTransform</message>
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<message level="Debug">Transform: AvalonStreamingTransform</message>
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<message level="Debug">Transform: ResetAdaptation</message>
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<message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_eth_tse_mac</b> "<b>submodules/altera_eth_tse_mac</b>"]]></message>
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<message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
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<message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
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<message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
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<message level="Debug" culprit="eth_tse"><![CDATA["<b>eth_tse</b>" reuses <b>altera_gpio_lite</b> "<b>submodules/altera_gpio_lite</b>"]]></message>
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<message level="Info" culprit="eth_tse"><![CDATA["<b>q_sys</b>" instantiated <b>altera_eth_tse</b> "<b>eth_tse</b>"]]></message>
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<message level="Debug" culprit="q_sys">queue size: 229 starting:altera_eth_tse_mac "submodules/altera_eth_tse_mac"</message>
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<message level="Info" culprit="i_tse_mac"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_eth_tse_mac</b> "<b>i_tse_mac</b>"]]></message>
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<message level="Debug" culprit="q_sys">queue size: 228 starting:altera_gpio_lite "submodules/altera_gpio_lite"</message>
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<message level="Info" culprit="rgmii_in4_0"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_gpio_lite</b> "<b>rgmii_in4_0</b>"]]></message>
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<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv</b>]]></message>
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</messages>
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</entity>
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<entity
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path="submodules/"
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parameterizationKey="altera_generic_quad_spi_controller:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=Micron512,IO_MODE=QUAD,UNIQUE_ID=q_sys_ext_flash,clkFreq=0,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1(altera_generic_quad_spi_controller:19.1:CS_WIDTH=1,IO_MODE=QUAD(soft_asmiblock:19.1:CS_WIDTH=1,IO_MODE=QUAD))(altera_generic_quad_spi_controller:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_UNUSED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_UNUSED,PORT_ILLEGAL_ERASE=PORT_UNUSED,PORT_ILLEGAL_WRITE=PORT_UNUSED,PORT_RDID_OUT=PORT_UNUSED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_UNUSED,PORT_READ_RDID=PORT_UNUSED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_UNUSED,PORT_SECTOR_ERASE=PORT_UNUSED,PORT_SECTOR_PROTECT=PORT_UNUSED,PORT_SHIFT_BYTES=PORT_UNUSED,PORT_WREN=PORT_UNUSED,PORT_WRITE=PORT_UNUSED,USE_ASMIBLOCK=ON,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true(altera_asmi_parallel:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_UNUSED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_UNUSED,PORT_ILLEGAL_ERASE=PORT_UNUSED,PORT_ILLEGAL_WRITE=PORT_UNUSED,PORT_RDID_OUT=PORT_UNUSED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_UNUSED,PORT_READ_RDID=PORT_UNUSED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_UNUSED,PORT_SECTOR_ERASE=PORT_UNUSED,PORT_SECTOR_PROTECT=PORT_UNUSED,PORT_SHIFT_BYTES=PORT_UNUSED,PORT_WREN=PORT_UNUSED,PORT_WRITE=PORT_UNUSED,USE_ASMIBLOCK=ON,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true))(altera_generic_quad_spi_controller:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None(altera_epcq_controller_core:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None))"
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|
instancePathKey="q_sys:.:ext_flash"
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|
kind="altera_generic_quad_spi_controller"
|
|
version="19.1"
|
|
name="q_sys_ext_flash">
|
|
<parameter name="clkFreq" value="0" />
|
|
<parameter name="CHIP_SELS" value="1" />
|
|
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="IO_MODE" value="QUAD" />
|
|
<parameter name="DDASI" value="1" />
|
|
<parameter name="UNIQUE_ID" value="q_sys_ext_flash" />
|
|
<parameter name="CS_WIDTH" value="1" />
|
|
<parameter
|
|
name="deviceFeaturesSystemInfo"
|
|
value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
|
|
<parameter name="ASI_WIDTH" value="4" />
|
|
<parameter name="ENABLE_4BYTE_ADDR" value="1" />
|
|
<parameter name="ASMI_ADDR_WIDTH" value="32" />
|
|
<parameter name="ADDR_WIDTH" value="24" />
|
|
<parameter name="FLASH_TYPE" value="Micron512" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v"
|
|
type="VERILOG" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/soft_asmiblock.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name.v"
|
|
type="VERILOG" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_epcq_controller_instance_name.v"
|
|
type="VERILOG" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/generic_qspi_controller_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/soft_asmiblock_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_asmi_parallel/altera_asmi_parallel_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_epcq_controller/altera_epcq_controller_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys" as="ext_flash" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 34 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash"</message>
|
|
<message level="Info" culprit="soft_asmiblock_instance_name">"Generating: soft_asmiblock_instance_name"</message>
|
|
<message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_soft_asmiblock_instance_name</b>"]]></message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name">"Generating: asmi_parallel_instance_name"</message>
|
|
<message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_asmi_parallel_instance_name</b>"]]></message>
|
|
<message level="Info" culprit="epcq_controller_instance_name">"Generating: epcq_controller_instance_name"</message>
|
|
<message level="Debug" culprit="ext_flash"><![CDATA["<b>ext_flash</b>" reuses <b>altera_generic_quad_spi_controller</b> "<b>submodules/q_sys_ext_flash_epcq_controller_instance_name</b>"]]></message>
|
|
<message level="Info" culprit="ext_flash"><![CDATA["<b>q_sys</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>ext_flash</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_soft_asmiblock_instance_name"</message>
|
|
<message level="Debug" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" reuses <b>soft_asmiblock</b> "<b>submodules/soft_asmiblock</b>"]]></message>
|
|
<message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock"</message>
|
|
<message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" instantiated <b>soft_asmiblock</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_asmi_parallel_instance_name"</message>
|
|
<message level="Debug" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" reuses <b>altera_asmi_parallel</b> "<b>submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</b>"]]></message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>asmi_parallel_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name"</message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name">generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" instantiated <b>altera_asmi_parallel</b> "<b>asmi_parallel_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_epcq_controller_instance_name"</message>
|
|
<message level="Debug" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" reuses <b>altera_epcq_controller_core</b> "<b>submodules/altera_epcq_controller_arb</b>"]]></message>
|
|
<message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>epcq_controller_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb"</message>
|
|
<message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" instantiated <b>altera_epcq_controller_core</b> "<b>epcq_controller_instance_name</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_timer:19.1:alwaysRun=false,counterSize=32,fixedPeriod=false,loadValue=4999,mult=2.0E-8,period=5000,periodUnits=CLOCKS,periodUnitsString=clocks,resetOutput=false,slave_address_width=3,snapshot=false,systemFrequency=50000000,ticksPerSec=10000.0,timeoutPulseOutput=true,timerPreset=CUSTOM,valueInSecond=0.0,watchdogPulse=2"
|
|
instancePathKey="q_sys:.:frame_timer"
|
|
kind="altera_avalon_timer"
|
|
version="19.1"
|
|
name="q_sys_frame_timer">
|
|
<parameter name="loadValue" value="4999" />
|
|
<parameter name="timeoutPulseOutput" value="true" />
|
|
<parameter name="period" value="5000" />
|
|
<parameter name="periodUnitsString" value="clocks" />
|
|
<parameter name="mult" value="2.0E-8" />
|
|
<parameter name="ticksPerSec" value="10000.0" />
|
|
<parameter name="systemFrequency" value="50000000" />
|
|
<parameter name="alwaysRun" value="false" />
|
|
<parameter name="valueInSecond" value="0.0" />
|
|
<parameter name="fixedPeriod" value="false" />
|
|
<parameter name="counterSize" value="32" />
|
|
<parameter name="periodUnits" value="CLOCKS" />
|
|
<parameter name="watchdogPulse" value="2" />
|
|
<parameter name="slave_address_width" value="3" />
|
|
<parameter name="resetOutput" value="false" />
|
|
<parameter name="snapshot" value="false" />
|
|
<parameter name="timerPreset" value="CUSTOM" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_frame_timer.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="frame_timer" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 36 starting:altera_avalon_timer "submodules/q_sys_frame_timer"</message>
|
|
<message level="Info" culprit="frame_timer">Starting RTL generation for module 'q_sys_frame_timer'</message>
|
|
<message level="Info" culprit="frame_timer"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_frame_timer --dir=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen//q_sys_frame_timer_component_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="frame_timer">Done RTL generation for module 'q_sys_frame_timer'</message>
|
|
<message level="Info" culprit="frame_timer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_timer</b> "<b>frame_timer</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_msgdma:19.1:AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP=<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>,AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP=<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_MM_READ_ADDRESS_MAP=,AUTO_MM_READ_ADDRESS_WIDTH=AddressWidth = -1,AUTO_MM_WRITE_ADDRESS_MAP=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>,AUTO_MM_WRITE_ADDRESS_WIDTH=AddressWidth = 28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CHANNEL_ENABLE=0,CHANNEL_ENABLE_DERIVED=0,CHANNEL_WIDTH=8,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_FIFO_DEPTH=8,ENHANCED_FEATURES=0,ERROR_ENABLE=1,ERROR_ENABLE_DERIVED=1,ERROR_WIDTH=6,EXPOSE_ST_PORT=0,FIX_ADDRESS_WIDTH=32,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=2,PACKET_ENABLE=1,PACKET_ENABLE_DERIVED=1,PREFETCHER_DATA_WIDTH=32,PREFETCHER_ENABLE=1,PREFETCHER_MAX_READ_BURST_COUNT=2,PREFETCHER_READ_BURST_ENABLE=0,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=2,STRIDE_ENABLE=0,STRIDE_ENABLE_DERIVED=0,TRANSFER_TYPE=Aligned Accesses,USE_FIX_ADDRESS_WIDTH=0(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(modular_sgdma_dispatcher:19.1:BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CSR_ADDRESS_WIDTH=3,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_BYTEENABLE_WIDTH=16,DESCRIPTOR_FIFO_DEPTH=8,DESCRIPTOR_INTERFACE=1,DESCRIPTOR_WIDTH=128,ENHANCED_FEATURES=0,GUI_RESPONSE_PORT=2,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=2,PREFETCHER_USE_CASE=1,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=1,STRIDE_ENABLE=0,TRANSFER_TYPE=Aligned Accesses)(altera_msgdma_prefetcher:19.1:ADDRESS_WIDTH=29,AUTO_ADDRESS_WIDTH=29,DATA_BYTEENABLE_WIDTH=4,DATA_WIDTH=32,DESCRIPTOR_WIDTH=128,ENABLE_READ_BURST=0,ENHANCED_FEATURES=0,FIX_ADDRESS_WIDTH=32,GUI_DESCRIPTOR_FIFO_DEPTH=8,GUI_MAX_READ_BURST_COUNT=2,MAX_READ_BURST_COUNT=1,MAX_READ_BURST_COUNT_WIDTH=1,RESPONSE_FIFO_DEPTH=16,RESPONSE_FIFO_DEPTH_LOG2=4,USE_FIX_ADDRESS_WIDTH=0)(dma_write_master:19.1:ACTUAL_BYTES_TRANSFERRED_WIDTH=13,ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=6,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)"
|
|
instancePathKey="q_sys:.:msgdma_rx"
|
|
kind="altera_msgdma"
|
|
version="19.1"
|
|
name="q_sys_msgdma_rx">
|
|
<parameter name="MAX_STRIDE" value="1" />
|
|
<parameter name="PACKET_ENABLE" value="1" />
|
|
<parameter name="ERROR_ENABLE" value="1" />
|
|
<parameter name="CHANNEL_ENABLE_DERIVED" value="0" />
|
|
<parameter name="MODE" value="2" />
|
|
<parameter name="STRIDE_ENABLE" value="0" />
|
|
<parameter
|
|
name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"
|
|
value="<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>" />
|
|
<parameter name="RESPONSE_PORT" value="2" />
|
|
<parameter name="BURST_ENABLE" value="0" />
|
|
<parameter name="FIX_ADDRESS_WIDTH" value="32" />
|
|
<parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
|
|
<parameter name="DATA_WIDTH" value="32" />
|
|
<parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
|
|
<parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
|
|
<parameter name="ERROR_WIDTH" value="6" />
|
|
<parameter name="MAX_BYTE" value="2048" />
|
|
<parameter name="PREFETCHER_ENABLE" value="1" />
|
|
<parameter name="ERROR_ENABLE_DERIVED" value="1" />
|
|
<parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="DATA_FIFO_DEPTH" value="32" />
|
|
<parameter name="CHANNEL_WIDTH" value="8" />
|
|
<parameter
|
|
name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
|
|
value="AddressWidth = 29" />
|
|
<parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
|
|
<parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
|
|
<parameter name="CHANNEL_ENABLE" value="0" />
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
|
|
<parameter name="ENHANCED_FEATURES" value="0" />
|
|
<parameter name="EXPOSE_ST_PORT" value="0" />
|
|
<parameter name="PACKET_ENABLE_DERIVED" value="1" />
|
|
<parameter name="PREFETCHER_DATA_WIDTH" value="32" />
|
|
<parameter name="BURST_WRAPPING_SUPPORT" value="0" />
|
|
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
|
|
<parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
|
|
<parameter
|
|
name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"
|
|
value="<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>" />
|
|
<parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
|
|
<parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
|
|
<parameter
|
|
name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
|
|
value="AddressWidth = 29" />
|
|
<parameter name="MAX_BURST_COUNT" value="2" />
|
|
<parameter name="STRIDE_ENABLE_DERIVED" value="0" />
|
|
<parameter
|
|
name="AUTO_MM_WRITE_ADDRESS_MAP"
|
|
value="<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_msgdma_rx.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/dispatcher.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/descriptor_buffers.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/csr_block.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/response_block.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/fifo_with_byteenables.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_signal_breakout.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_signal_breakout.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_read.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_write_back.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_fifo.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_interrrupt.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_csr.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_master.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/byte_enable_generator.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/ST_to_MM_Adapter.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_burst_control.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/top/altera_msgdma_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/dispatcher/dispatcher_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/prefetcher/altera_msgdma_prefetcher_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/write_master/write_master_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys" as="msgdma_rx" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 35 starting:altera_msgdma "submodules/q_sys_msgdma_rx"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>11</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>modular_sgdma_dispatcher</b> "<b>submodules/dispatcher</b>"]]></message>
|
|
<message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>altera_msgdma_prefetcher</b> "<b>submodules/altera_msgdma_prefetcher</b>"]]></message>
|
|
<message level="Debug" culprit="msgdma_rx"><![CDATA["<b>msgdma_rx</b>" reuses <b>dma_write_master</b> "<b>submodules/write_master</b>"]]></message>
|
|
<message level="Info" culprit="msgdma_rx"><![CDATA["<b>q_sys</b>" instantiated <b>altera_msgdma</b> "<b>msgdma_rx</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher"</message>
|
|
<message level="Info" culprit="dispatcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>modular_sgdma_dispatcher</b> "<b>dispatcher_internal</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"</message>
|
|
<message level="Info" culprit="prefetcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>altera_msgdma_prefetcher</b> "<b>prefetcher_internal</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 222 starting:dma_write_master "submodules/write_master"</message>
|
|
<message level="Info" culprit="write_mstr_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>dma_write_master</b> "<b>write_mstr_internal</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_msgdma:19.1:AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP=<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>,AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP=<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>,AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH=AddressWidth = 29,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=6,AUTO_MM_READ_ADDRESS_MAP=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>,AUTO_MM_READ_ADDRESS_WIDTH=AddressWidth = 28,AUTO_MM_WRITE_ADDRESS_MAP=,AUTO_MM_WRITE_ADDRESS_WIDTH=AddressWidth = -1,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CHANNEL_ENABLE=0,CHANNEL_ENABLE_DERIVED=0,CHANNEL_WIDTH=8,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_FIFO_DEPTH=8,ENHANCED_FEATURES=0,ERROR_ENABLE=1,ERROR_ENABLE_DERIVED=1,ERROR_WIDTH=1,EXPOSE_ST_PORT=0,FIX_ADDRESS_WIDTH=32,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=1,PACKET_ENABLE=1,PACKET_ENABLE_DERIVED=1,PREFETCHER_DATA_WIDTH=32,PREFETCHER_ENABLE=1,PREFETCHER_MAX_READ_BURST_COUNT=2,PREFETCHER_READ_BURST_ENABLE=0,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=2,STRIDE_ENABLE=0,STRIDE_ENABLE_DERIVED=0,TRANSFER_TYPE=Aligned Accesses,USE_FIX_ADDRESS_WIDTH=0(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(modular_sgdma_dispatcher:19.1:BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CSR_ADDRESS_WIDTH=3,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_BYTEENABLE_WIDTH=16,DESCRIPTOR_FIFO_DEPTH=8,DESCRIPTOR_INTERFACE=1,DESCRIPTOR_WIDTH=128,ENHANCED_FEATURES=0,GUI_RESPONSE_PORT=2,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=1,PREFETCHER_USE_CASE=1,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=1,STRIDE_ENABLE=0,TRANSFER_TYPE=Aligned Accesses)(altera_msgdma_prefetcher:19.1:ADDRESS_WIDTH=29,AUTO_ADDRESS_WIDTH=29,DATA_BYTEENABLE_WIDTH=4,DATA_WIDTH=32,DESCRIPTOR_WIDTH=128,ENABLE_READ_BURST=0,ENHANCED_FEATURES=0,FIX_ADDRESS_WIDTH=32,GUI_DESCRIPTOR_FIFO_DEPTH=8,GUI_MAX_READ_BURST_COUNT=2,MAX_READ_BURST_COUNT=1,MAX_READ_BURST_COUNT_WIDTH=1,RESPONSE_FIFO_DEPTH=16,RESPONSE_FIFO_DEPTH_LOG2=4,USE_FIX_ADDRESS_WIDTH=0)(dma_read_master:19.1:ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,CHANNEL_ENABLE=0,CHANNEL_WIDTH=8,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=1,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(clock:19.1:)(reset:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)"
|
|
instancePathKey="q_sys:.:msgdma_tx"
|
|
kind="altera_msgdma"
|
|
version="19.1"
|
|
name="q_sys_msgdma_tx">
|
|
<parameter name="MAX_STRIDE" value="1" />
|
|
<parameter name="PACKET_ENABLE" value="1" />
|
|
<parameter name="ERROR_ENABLE" value="1" />
|
|
<parameter name="CHANNEL_ENABLE_DERIVED" value="0" />
|
|
<parameter name="MODE" value="1" />
|
|
<parameter name="STRIDE_ENABLE" value="0" />
|
|
<parameter
|
|
name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP"
|
|
value="<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>" />
|
|
<parameter name="RESPONSE_PORT" value="2" />
|
|
<parameter name="BURST_ENABLE" value="0" />
|
|
<parameter name="FIX_ADDRESS_WIDTH" value="32" />
|
|
<parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
|
|
<parameter name="DATA_WIDTH" value="32" />
|
|
<parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
|
|
<parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
|
|
<parameter name="ERROR_WIDTH" value="1" />
|
|
<parameter name="MAX_BYTE" value="2048" />
|
|
<parameter name="PREFETCHER_ENABLE" value="1" />
|
|
<parameter name="ERROR_ENABLE_DERIVED" value="1" />
|
|
<parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="DATA_FIFO_DEPTH" value="32" />
|
|
<parameter name="CHANNEL_WIDTH" value="8" />
|
|
<parameter
|
|
name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
|
|
value="AddressWidth = 29" />
|
|
<parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
|
|
<parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
|
|
<parameter name="CHANNEL_ENABLE" value="0" />
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
|
|
<parameter name="ENHANCED_FEATURES" value="0" />
|
|
<parameter name="EXPOSE_ST_PORT" value="0" />
|
|
<parameter name="PACKET_ENABLE_DERIVED" value="1" />
|
|
<parameter name="PREFETCHER_DATA_WIDTH" value="32" />
|
|
<parameter name="BURST_WRAPPING_SUPPORT" value="0" />
|
|
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
|
|
<parameter
|
|
name="AUTO_MM_READ_ADDRESS_MAP"
|
|
value="<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' /></address-map>" />
|
|
<parameter
|
|
name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP"
|
|
value="<address-map><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' /></address-map>" />
|
|
<parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
|
|
<parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
|
|
<parameter
|
|
name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
|
|
value="AddressWidth = 29" />
|
|
<parameter name="MAX_BURST_COUNT" value="2" />
|
|
<parameter name="STRIDE_ENABLE_DERIVED" value="0" />
|
|
<parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_msgdma_tx.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/dispatcher.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/descriptor_buffers.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/csr_block.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/response_block.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/fifo_with_byteenables.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_signal_breakout.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_signal_breakout.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_read.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_write_back.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_fifo.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_interrrupt.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_csr.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_master.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/MM_to_ST_Adapter.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_burst_control.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/top/altera_msgdma_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/dispatcher/dispatcher_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/prefetcher/altera_msgdma_prefetcher_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/read_master/read_master_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys" as="msgdma_tx" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 37 starting:altera_msgdma "submodules/q_sys_msgdma_tx"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>11</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>modular_sgdma_dispatcher</b> "<b>submodules/dispatcher</b>"]]></message>
|
|
<message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>altera_msgdma_prefetcher</b> "<b>submodules/altera_msgdma_prefetcher</b>"]]></message>
|
|
<message level="Debug" culprit="msgdma_tx"><![CDATA["<b>msgdma_tx</b>" reuses <b>dma_read_master</b> "<b>submodules/read_master</b>"]]></message>
|
|
<message level="Info" culprit="msgdma_tx"><![CDATA["<b>q_sys</b>" instantiated <b>altera_msgdma</b> "<b>msgdma_tx</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher"</message>
|
|
<message level="Info" culprit="dispatcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>modular_sgdma_dispatcher</b> "<b>dispatcher_internal</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"</message>
|
|
<message level="Info" culprit="prefetcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>altera_msgdma_prefetcher</b> "<b>prefetcher_internal</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 219 starting:dma_read_master "submodules/read_master"</message>
|
|
<message level="Info" culprit="read_mstr_internal"><![CDATA["<b>msgdma_tx</b>" instantiated <b>dma_read_master</b> "<b>read_mstr_internal</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_onchip_flash:19.1:ADDR_RANGE1_END_ADDR=360447,ADDR_RANGE1_OFFSET=2048,ADDR_RANGE2_END_ADDR=360447,ADDR_RANGE2_OFFSET=0,ADDR_RANGE3_OFFSET=0,AUTO_CLOCK_RATE=50000000,AVMM_DATA_ADDR_WIDTH=19,AVMM_DATA_BURSTCOUNT_WIDTH=4,AVMM_DATA_DATA_WIDTH=32,CLOCK_FREQUENCY=50.0,CONFIGURATION_MODE=Single Uncompressed Image,CONFIGURATION_SCHEME=Internal Configuration,DATA_INTERFACE=Parallel,DEVICE_FAMILY=MAX 10,DEVICE_ID=50,FLASH_ADDR_ALIGNMENT_BITS=2,FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX=60,FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX=17500000,FLASH_READ_CYCLE_MAX_INDEX=5,FLASH_RESET_CYCLE_MAX_INDEX=12,FLASH_SEQ_READ_DATA_COUNT=4,FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX=15250,INIT_FILENAME=,INIT_FILENAME_SIM=,IS_COMPRESSED_IMAGE=False,IS_DUAL_BOOT=False,IS_ERAM_SKIP=True,MAX_UFM_VALID_ADDR=114687,MAX_VALID_ADDR=360447,MIN_UFM_VALID_ADDR=0,MIN_VALID_ADDR=0,PARALLEL_MODE=true,PART_NAME=10M50DAF484C6GES,READ_AND_WRITE_MODE=true,READ_BURST_COUNT=8,READ_BURST_MODE=Incrementing,SECTOR1_END_ADDR=8191,SECTOR1_MAP=1,SECTOR1_START_ADDR=0,SECTOR2_END_ADDR=16383,SECTOR2_MAP=2,SECTOR2_START_ADDR=8192,SECTOR3_END_ADDR=114687,SECTOR3_MAP=3,SECTOR3_START_ADDR=16384,SECTOR4_END_ADDR=188415,SECTOR4_MAP=4,SECTOR4_START_ADDR=114688,SECTOR5_END_ADDR=360447,SECTOR5_MAP=5,SECTOR5_START_ADDR=188416,SECTOR_ACCESS_MODE=Read and write,Read and write,Read and write,Read and write,Read and write,SECTOR_ADDRESS_MAPPING=0x00000 - 0x07fff,0x08000 - 0x0ffff,0x10000 - 0x6ffff,0x70000 - 0xb7fff,0xb8000 - 0x15ffff,SECTOR_ID=1,2,3,4,5,SECTOR_READ_PROTECTION_MODE=0,SECTOR_STORAGE_TYPE=UFM,UFM,UFM,CFM,CFM,WRAPPING_BURST_MODE=false,autoInitializationFileName=q_sys_onchip_flash,initFlashContent=false,initializationFileName=D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex,initializationFileNameForSim=altera_onchip_flash.dat,useNonDefaultInitFile=false"
|
|
instancePathKey="q_sys:.:onchip_flash"
|
|
kind="altera_onchip_flash"
|
|
version="19.1"
|
|
name="altera_onchip_flash">
|
|
<parameter name="SECTOR_READ_PROTECTION_MODE" value="0" />
|
|
<parameter name="MIN_UFM_VALID_ADDR" value="0" />
|
|
<parameter name="AVMM_DATA_ADDR_WIDTH" value="19" />
|
|
<parameter name="SECTOR3_START_ADDR" value="16384" />
|
|
<parameter name="AUTO_CLOCK_RATE" value="50000000" />
|
|
<parameter name="FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX" value="17500000" />
|
|
<parameter name="SECTOR1_END_ADDR" value="8191" />
|
|
<parameter name="SECTOR4_END_ADDR" value="188415" />
|
|
<parameter name="initializationFileNameForSim" value="altera_onchip_flash.dat" />
|
|
<parameter name="MAX_VALID_ADDR" value="360447" />
|
|
<parameter name="DATA_INTERFACE" value="Parallel" />
|
|
<parameter name="AVMM_DATA_DATA_WIDTH" value="32" />
|
|
<parameter name="SECTOR1_MAP" value="1" />
|
|
<parameter name="INIT_FILENAME_SIM" value="" />
|
|
<parameter
|
|
name="initializationFileName"
|
|
value="D:/projekty/HIT/v2.0/fpga/software/hit20_v3/mem_init/q_sys_onchip_flash.hex" />
|
|
<parameter name="MIN_VALID_ADDR" value="0" />
|
|
<parameter name="useNonDefaultInitFile" value="false" />
|
|
<parameter name="SECTOR2_MAP" value="2" />
|
|
<parameter name="SECTOR3_END_ADDR" value="114687" />
|
|
<parameter name="CONFIGURATION_SCHEME" value="Internal Configuration" />
|
|
<parameter name="SECTOR3_MAP" value="3" />
|
|
<parameter name="DEVICE_ID" value="50" />
|
|
<parameter name="WRAPPING_BURST_MODE" value="false" />
|
|
<parameter name="SECTOR5_MAP" value="5" />
|
|
<parameter name="FLASH_SEQ_READ_DATA_COUNT" value="4" />
|
|
<parameter name="FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX" value="15250" />
|
|
<parameter name="autoInitializationFileName" value="q_sys_onchip_flash" />
|
|
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ADDR_RANGE3_OFFSET" value="0" />
|
|
<parameter name="ADDR_RANGE2_OFFSET" value="0" />
|
|
<parameter name="SECTOR2_END_ADDR" value="16383" />
|
|
<parameter name="SECTOR4_MAP" value="4" />
|
|
<parameter name="FLASH_RESET_CYCLE_MAX_INDEX" value="12" />
|
|
<parameter
|
|
name="SECTOR_ADDRESS_MAPPING"
|
|
value="0x00000 - 0x07fff,0x08000 - 0x0ffff,0x10000 - 0x6ffff,0x70000 - 0xb7fff,0xb8000 - 0x15ffff" />
|
|
<parameter name="IS_ERAM_SKIP" value="True" />
|
|
<parameter name="READ_BURST_MODE" value="Incrementing" />
|
|
<parameter name="READ_AND_WRITE_MODE" value="true" />
|
|
<parameter name="FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX" value="60" />
|
|
<parameter name="SECTOR5_START_ADDR" value="188416" />
|
|
<parameter name="PART_NAME" value="10M50DAF484C6GES" />
|
|
<parameter name="ADDR_RANGE1_OFFSET" value="2048" />
|
|
<parameter name="MAX_UFM_VALID_ADDR" value="114687" />
|
|
<parameter name="INIT_FILENAME" value="" />
|
|
<parameter name="CONFIGURATION_MODE" value="Single Uncompressed Image" />
|
|
<parameter name="PARALLEL_MODE" value="true" />
|
|
<parameter name="SECTOR4_START_ADDR" value="114688" />
|
|
<parameter name="FLASH_ADDR_ALIGNMENT_BITS" value="2" />
|
|
<parameter
|
|
name="SECTOR_ACCESS_MODE"
|
|
value="Read and write,Read and write,Read and write,Read and write,Read and write" />
|
|
<parameter name="initFlashContent" value="false" />
|
|
<parameter name="SECTOR1_START_ADDR" value="0" />
|
|
<parameter name="ADDR_RANGE1_END_ADDR" value="360447" />
|
|
<parameter name="IS_COMPRESSED_IMAGE" value="False" />
|
|
<parameter name="SECTOR_ID" value="1,2,3,4,5" />
|
|
<parameter name="READ_BURST_COUNT" value="8" />
|
|
<parameter name="FLASH_READ_CYCLE_MAX_INDEX" value="5" />
|
|
<parameter name="AVMM_DATA_BURSTCOUNT_WIDTH" value="4" />
|
|
<parameter name="CLOCK_FREQUENCY" value="50.0" />
|
|
<parameter name="SECTOR_STORAGE_TYPE" value="UFM,UFM,UFM,CFM,CFM" />
|
|
<parameter name="ADDR_RANGE2_END_ADDR" value="360447" />
|
|
<parameter name="SECTOR5_END_ADDR" value="360447" />
|
|
<parameter name="SECTOR2_START_ADDR" value="8192" />
|
|
<parameter name="IS_DUAL_BOOT" value="False" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash_util.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_onchip_flash.sdc"
|
|
type="SDC"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rtl/altera_onchip_flash_block.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="onchip_flash" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 39 starting:altera_onchip_flash "submodules/altera_onchip_flash"</message>
|
|
<message level="Info" culprit="onchip_flash">Generating top-level entity altera_onchip_flash</message>
|
|
<message level="Info" culprit="onchip_flash"><![CDATA["<b>q_sys</b>" instantiated <b>altera_onchip_flash</b> "<b>onchip_flash</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_pio:19.1:bitClearingEdgeCapReg=false,bitModifyingOutReg=true,captureEdge=false,clockRate=50000000,derived_capture=false,derived_do_test_bench_wiring=false,derived_edge_type=NONE,derived_has_in=false,derived_has_irq=false,derived_has_out=true,derived_has_tri=false,derived_irq_type=NONE,direction=Output,edgeType=RISING,generateIRQ=false,irqType=LEVEL,resetValue=0,simDoTestBenchWiring=false,simDrivenValue=0,width=8"
|
|
instancePathKey="q_sys:.:output_pio"
|
|
kind="altera_avalon_pio"
|
|
version="19.1"
|
|
name="q_sys_output_pio">
|
|
<parameter name="derived_do_test_bench_wiring" value="false" />
|
|
<parameter name="generateIRQ" value="false" />
|
|
<parameter name="derived_has_irq" value="false" />
|
|
<parameter name="captureEdge" value="false" />
|
|
<parameter name="clockRate" value="50000000" />
|
|
<parameter name="derived_has_out" value="true" />
|
|
<parameter name="derived_has_in" value="false" />
|
|
<parameter name="resetValue" value="0" />
|
|
<parameter name="derived_has_tri" value="false" />
|
|
<parameter name="derived_capture" value="false" />
|
|
<parameter name="simDoTestBenchWiring" value="false" />
|
|
<parameter name="bitModifyingOutReg" value="true" />
|
|
<parameter name="simDrivenValue" value="0" />
|
|
<parameter name="derived_edge_type" value="NONE" />
|
|
<parameter name="irqType" value="LEVEL" />
|
|
<parameter name="derived_irq_type" value="NONE" />
|
|
<parameter name="edgeType" value="RISING" />
|
|
<parameter name="width" value="8" />
|
|
<parameter name="bitClearingEdgeCapReg" value="false" />
|
|
<parameter name="direction" value="Output" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_output_pio.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="output_pio" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 38 starting:altera_avalon_pio "submodules/q_sys_output_pio"</message>
|
|
<message level="Info" culprit="output_pio">Starting RTL generation for module 'q_sys_output_pio'</message>
|
|
<message level="Info" culprit="output_pio"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_output_pio --dir=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen//q_sys_output_pio_component_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="output_pio">Done RTL generation for module 'q_sys_output_pio'</message>
|
|
<message level="Info" culprit="output_pio"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_pio</b> "<b>output_pio</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="sensor_recon:1:"
|
|
instancePathKey="q_sys:.:sensor_interface"
|
|
kind="sensor_recon"
|
|
version="1"
|
|
name="sensor_algo">
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/rms.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/stl2sts.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/calibration.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/algo_top_cl_cali_rms.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sensor_interface.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/serial_rx.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/serial_tx.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sensor_algo.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/bkg_subtraction_pipe.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/cluster_locate.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/data_caled_ram.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/st_splitter16.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_splitter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/div.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/sqrt.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/ram4bkg.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/sensor_algo_qsys/sensor_recon_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="sensor_interface" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 37 starting:sensor_recon "submodules/sensor_algo"</message>
|
|
<message level="Info" culprit="sensor_interface"><![CDATA["<b>q_sys</b>" instantiated <b>sensor_recon</b> "<b>sensor_interface</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_timer:19.1:alwaysRun=false,counterSize=32,fixedPeriod=false,loadValue=499999,mult=0.001,period=10,periodUnits=MSEC,periodUnitsString=ms,resetOutput=false,slave_address_width=3,snapshot=true,systemFrequency=50000000,ticksPerSec=100.0,timeoutPulseOutput=false,timerPreset=FULL_FEATURED,valueInSecond=0.001,watchdogPulse=2"
|
|
instancePathKey="q_sys:.:sys_clk_timer"
|
|
kind="altera_avalon_timer"
|
|
version="19.1"
|
|
name="q_sys_sys_clk_timer">
|
|
<parameter name="loadValue" value="499999" />
|
|
<parameter name="timeoutPulseOutput" value="false" />
|
|
<parameter name="period" value="10" />
|
|
<parameter name="periodUnitsString" value="ms" />
|
|
<parameter name="mult" value="0.001" />
|
|
<parameter name="ticksPerSec" value="100.0" />
|
|
<parameter name="systemFrequency" value="50000000" />
|
|
<parameter name="alwaysRun" value="false" />
|
|
<parameter name="valueInSecond" value="0.001" />
|
|
<parameter name="fixedPeriod" value="false" />
|
|
<parameter name="counterSize" value="32" />
|
|
<parameter name="periodUnits" value="MSEC" />
|
|
<parameter name="watchdogPulse" value="2" />
|
|
<parameter name="slave_address_width" value="3" />
|
|
<parameter name="resetOutput" value="false" />
|
|
<parameter name="snapshot" value="true" />
|
|
<parameter name="timerPreset" value="FULL_FEATURED" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_sys_clk_timer.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="sys_clk_timer" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 36 starting:altera_avalon_timer "submodules/q_sys_sys_clk_timer"</message>
|
|
<message level="Info" culprit="sys_clk_timer">Starting RTL generation for module 'q_sys_sys_clk_timer'</message>
|
|
<message level="Info" culprit="sys_clk_timer"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_sys_clk_timer --dir=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen//q_sys_sys_clk_timer_component_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="sys_clk_timer">Done RTL generation for module 'q_sys_sys_clk_timer'</message>
|
|
<message level="Info" culprit="sys_clk_timer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_timer</b> "<b>sys_clk_timer</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_sysid_qsys:19.1:id=-87110914,timestamp=1728634208"
|
|
instancePathKey="q_sys:.:sysid"
|
|
kind="altera_avalon_sysid_qsys"
|
|
version="19.1"
|
|
name="q_sys_sysid">
|
|
<parameter name="id" value="-87110914" />
|
|
<parameter name="timestamp" value="1728634208" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_sysid.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="sysid" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 35 starting:altera_avalon_sysid_qsys "submodules/q_sys_sysid"</message>
|
|
<message level="Info" culprit="sysid"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_sysid_qsys</b> "<b>sysid</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="multiplexer:19.1:bitsPerSymbol=8,errorWidth=1,inErrorWidth=1,inUseEmpty=false,inUseEmptyPort=AUTO,inUsePackets=true,numInputInterfaces=2,outChannelWidth=1,packetScheduling=true,schedulingSize=512,symbolsPerBeat=4,useHighBitsOfChannel=true,usePackets=true"
|
|
instancePathKey="q_sys:.:tx_multiplexer"
|
|
kind="multiplexer"
|
|
version="19.1"
|
|
name="q_sys_tx_multiplexer">
|
|
<parameter name="inErrorWidth" value="1" />
|
|
<parameter name="usePackets" value="true" />
|
|
<parameter name="numInputInterfaces" value="2" />
|
|
<parameter name="schedulingSize" value="512" />
|
|
<parameter name="bitsPerSymbol" value="8" />
|
|
<parameter name="packetScheduling" value="true" />
|
|
<parameter name="errorWidth" value="1" />
|
|
<parameter name="outChannelWidth" value="1" />
|
|
<parameter name="inUseEmptyPort" value="AUTO" />
|
|
<parameter name="useHighBitsOfChannel" value="true" />
|
|
<parameter name="symbolsPerBeat" value="4" />
|
|
<parameter name="inUseEmpty" value="false" />
|
|
<parameter name="inUsePackets" value="true" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_tx_multiplexer.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_multiplexer/avalon-st_multiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="tx_multiplexer" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 34 starting:multiplexer "submodules/q_sys_tx_multiplexer"</message>
|
|
<message level="Info" culprit="tx_multiplexer"><![CDATA["<b>q_sys</b>" instantiated <b>multiplexer</b> "<b>tx_multiplexer</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="udp_generator:1.0:"
|
|
instancePathKey="q_sys:.:udp_generator"
|
|
kind="udp_generator"
|
|
version="1.0"
|
|
name="udp_generator">
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/udp_generator.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/udp_generator_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="udp_generator" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 33 starting:udp_generator "submodules/udp_generator"</message>
|
|
<message level="Info" culprit="udp_generator"><![CDATA["<b>q_sys</b>" instantiated <b>udp_generator</b> "<b>udp_generator</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_mm_interconnect:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,COMPOSE_CONTENTS=add_instance {sensor_interface_calibration_ram_interface_translator} {altera_merlin_master_translator};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_DATA_W} {16};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_ADDRESS_W} {10};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READDATA} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READ} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_CLKEN} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_LOCK} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {SYNC_RESET} {0};add_instance {calibration_ram_s2_translator} {altera_merlin_slave_translator};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {calibration_ram_s2_translator} {AV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_ADDRESS_W} {10};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {AV_READLATENCY} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READDATA} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READ} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITE} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_ADDRESS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_LOCK} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {calibration_ram_s2_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sensor_interface_rst_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {sys_clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {sys_clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {sys_clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0} {calibration_ram_s2_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sensor_interface_rst_reset_bridge.out_reset} {sensor_interface_calibration_ram_interface_translator.reset} {reset};add_connection {sensor_interface_rst_reset_bridge.out_reset} {calibration_ram_s2_translator.reset} {reset};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_calibration_ram_interface_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s2_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_rst_reset_bridge.clk} {clock};add_interface {sys_clk_clk} {clock} {slave};set_interface_property {sys_clk_clk} {EXPORT_OF} {sys_clk_clk_clock_bridge.in_clk};add_interface {sensor_interface_rst_reset_bridge_in_reset} {reset} {slave};set_interface_property {sensor_interface_rst_reset_bridge_in_reset} {EXPORT_OF} {sensor_interface_rst_reset_bridge.in_reset};add_interface {sensor_interface_calibration_ram_interface} {avalon} {slave};set_interface_property {sensor_interface_calibration_ram_interface} {EXPORT_OF} {sensor_interface_calibration_ram_interface_translator.avalon_anti_master_0};add_interface {calibration_ram_s2} {avalon} {master};set_interface_property {calibration_ram_s2} {EXPORT_OF} {calibration_ram_s2_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.calibration_ram.s2} {0};set_module_assignment {interconnect_id.sensor_interface.calibration_ram_interface} {0};(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=2,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=2,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=10,UAV_BURSTCOUNT_W=2,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=2,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=2,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=10,UAV_BURSTCOUNT_W=2,UAV_BYTEENABLE_W=2,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=16,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=50000000,NUM_CLOCK_OUTPUTS=1)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(reset:19.1:)(reset:19.1:)(clock:19.1:)(clock:19.1:)(clock:19.1:)"
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instancePathKey="q_sys:.:mm_interconnect_0"
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kind="altera_mm_interconnect"
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version="19.1"
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name="q_sys_mm_interconnect_0">
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<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
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<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
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<parameter
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name="COMPOSE_CONTENTS"
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value="add_instance {sensor_interface_calibration_ram_interface_translator} {altera_merlin_master_translator};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_DATA_W} {16};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_ADDRESS_W} {10};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READDATA} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READ} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_CLKEN} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_LOCK} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sensor_interface_calibration_ram_interface_translator} {SYNC_RESET} {0};add_instance {calibration_ram_s2_translator} {altera_merlin_slave_translator};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {calibration_ram_s2_translator} {AV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_ADDRESS_W} {10};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s2_translator} {AV_READLATENCY} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READDATA} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READ} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITE} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_ADDRESS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_LOCK} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {calibration_ram_s2_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {calibration_ram_s2_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s2_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s2_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {calibration_ram_s2_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sensor_interface_rst_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {sensor_interface_rst_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {sys_clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {sys_clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {sys_clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0} {calibration_ram_s2_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0/calibration_ram_s2_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sensor_interface_rst_reset_bridge.out_reset} {sensor_interface_calibration_ram_interface_translator.reset} {reset};add_connection {sensor_interface_rst_reset_bridge.out_reset} {calibration_ram_s2_translator.reset} {reset};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_calibration_ram_interface_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s2_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_rst_reset_bridge.clk} {clock};add_interface {sys_clk_clk} {clock} {slave};set_interface_property {sys_clk_clk} {EXPORT_OF} {sys_clk_clk_clock_bridge.in_clk};add_interface {sensor_interface_rst_reset_bridge_in_reset} {reset} {slave};set_interface_property {sensor_interface_rst_reset_bridge_in_reset} {EXPORT_OF} {sensor_interface_rst_reset_bridge.in_reset};add_interface {sensor_interface_calibration_ram_interface} {avalon} {slave};set_interface_property {sensor_interface_calibration_ram_interface} {EXPORT_OF} {sensor_interface_calibration_ram_interface_translator.avalon_anti_master_0};add_interface {calibration_ram_s2} {avalon} {master};set_interface_property {calibration_ram_s2} {EXPORT_OF} {calibration_ram_s2_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.calibration_ram.s2} {0};set_module_assignment {interconnect_id.sensor_interface.calibration_ram_interface} {0};" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_0.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
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|
</childSourceFiles>
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<instantiator instantiator="q_sys" as="mm_interconnect_0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 32 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_0"</message>
|
|
<message level="Progress" culprit="min"></message>
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|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
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|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>4</b> modules, <b>6</b> connections]]></message>
|
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<message level="Debug">Transform: MMTransform</message>
|
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<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
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<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
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<message level="Debug">Transform: DefaultSlaveTransform</message>
|
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<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
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<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
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<message level="Debug">Transform: RouterTransform</message>
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<message level="Debug">Transform: TrafficLimiterTransform</message>
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|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
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<message level="Debug">Transform: NetworkToSwitchTransform</message>
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<message level="Debug">Transform: WidthTransform</message>
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<message level="Debug">Transform: RouterTableTransform</message>
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<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
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|
<message level="Debug">Transform: ClockCrossingTransform</message>
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|
<message level="Debug">Transform: PipelineTransform</message>
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|
<message level="Debug">Transform: SpotPipelineTransform</message>
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<message level="Debug">Transform: PerformanceMonitorTransform</message>
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<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
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<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
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<message level="Debug">Transform: InterconnectConnectionsTagger</message>
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<message level="Debug">Transform: HierarchyTransform</message>
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<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>4</b> modules, <b>6</b> connections]]></message>
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<message level="Debug">Transform: InterruptMapperTransform</message>
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<message level="Debug">Transform: InterruptSyncTransform</message>
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<message level="Debug">Transform: InterruptFanoutTransform</message>
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<message level="Debug">Transform: AvalonStreamingTransform</message>
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<message level="Debug">Transform: ResetAdaptation</message>
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<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
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<message level="Info" culprit="mm_interconnect_0"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"]]></message>
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<message level="Debug" culprit="q_sys">queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
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<message
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level="Info"
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culprit="sensor_interface_calibration_ram_interface_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>sensor_interface_calibration_ram_interface_translator</b>"]]></message>
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<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
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<message level="Debug" culprit="q_sys">queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
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<message level="Info" culprit="calibration_ram_s2_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>calibration_ram_s2_translator</b>"]]></message>
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<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
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</messages>
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</entity>
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<entity
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path="submodules/"
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parameterizationKey="altera_mm_interconnect:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,COMPOSE_CONTENTS=add_instance {cpu_data_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_data_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_data_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_data_master_translator} {SYNC_RESET} {0};add_instance {cpu_instruction_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {cpu_instruction_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_instruction_master_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_mm_read_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESS_W} {28};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_mm_write_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESS_W} {28};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_descriptor_read_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_descriptor_read_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_descriptor_write_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITERESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_descriptor_write_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITERESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {SYNC_RESET} {0};add_instance {ddr3_ram_avl_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESS_W} {25};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_DATA_W} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_BURSTCOUNT_W} {5};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READDATA} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READ} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITE} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BEGINBURSTTRANSFER} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_LOCK} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {ext_flash_avl_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READ} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {ext_flash_avl_mem_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESS_W} {24};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTCOUNT_W} {7};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_BURSTCOUNT_W} {9};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READDATA} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READ} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITE} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_LOCK} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_CONSTANT_BURST_BEHAVIOR} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {eth_tse_control_port_translator} {altera_merlin_slave_translator};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {eth_tse_control_port_translator} {AV_DATA_W} {32};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_DATA_W} {32};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {eth_tse_control_port_translator} {AV_READLATENCY} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READDATA} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READ} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITE} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_ADDRESS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_LOCK} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {eth_tse_control_port_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sysid_control_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESS_W} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_DATA_W} {32};set_instance_parameter_value {sysid_control_slave_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {sysid_control_slave_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sysid_control_slave_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sysid_control_slave_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sysid_control_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_READDATA} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READ} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sysid_control_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sysid_control_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sysid_control_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sysid_control_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_tx_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_rx_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {onchip_flash_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESS_W} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {onchip_flash_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READ} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_flash_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {udp_generator_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {udp_generator_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {udp_generator_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {udp_generator_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {udp_generator_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {udp_generator_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {udp_generator_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_READ} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {udp_generator_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {udp_generator_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {udp_generator_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {udp_generator_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sensor_interface_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESS_W} {2};set_instance_parameter_value {sensor_interface_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sensor_interface_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READ} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sensor_interface_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {onchip_flash_data_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESS_W} {19};set_instance_parameter_value {onchip_flash_data_translator} {AV_DATA_W} {32};set_instance_parameter_value {onchip_flash_data_translator} {UAV_DATA_W} {32};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTCOUNT_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {onchip_flash_data_translator} {UAV_BURSTCOUNT_W} {6};set_instance_parameter_value {onchip_flash_data_translator} {AV_READLATENCY} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READ} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_data_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_flash_data_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_flash_data_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_data_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_flash_data_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {cpu_debug_mem_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_DATA_W} {32};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READ} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_tx_prefetcher_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_rx_prefetcher_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {descriptor_memory_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESS_W} {11};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READ} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sys_clk_timer_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READ} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {output_pio_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {output_pio_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {output_pio_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {output_pio_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {output_pio_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {output_pio_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {output_pio_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_READ} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {output_pio_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {output_pio_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {output_pio_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {output_pio_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {button_pio_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESS_W} {2};set_instance_parameter_value {button_pio_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {button_pio_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {button_pio_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {button_pio_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {button_pio_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {button_pio_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READ} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {button_pio_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {button_pio_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {button_pio_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {button_pio_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {debug_uart_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {debug_uart_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {debug_uart_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {debug_uart_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {debug_uart_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {debug_uart_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {debug_uart_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_READ} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_BEGINTRANSFER} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {debug_uart_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {debug_uart_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {debug_uart_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {debug_uart_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {frame_timer_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {frame_timer_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {frame_timer_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {frame_timer_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {frame_timer_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {frame_timer_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {frame_timer_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_READ} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {frame_timer_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {frame_timer_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {frame_timer_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {frame_timer_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {calibration_ram_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {calibration_ram_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READ} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {calibration_ram_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {cpu_data_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_data_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_data_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_data_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_data_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_data_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {cpu_data_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {cpu_data_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {cpu_data_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {cpu_data_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_data_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_data_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_data_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_data_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_data_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_data_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_data_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_data_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_data_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_data_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_data_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_agent} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_data_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="7"
|
|
name="ext_flash_avl_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d20"
|
|
end="0x00000000018403d40"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="8"
|
|
name="ext_flash_avl_mem_translator.avalon_universal_slave_0"
|
|
start="0x0000000014000000"
|
|
end="0x00000000018000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="6"
|
|
name="eth_tse_control_port_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403000"
|
|
end="0x00000000018403400"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="19"
|
|
name="sysid_control_slave_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d68"
|
|
end="0x00000000018403d70"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="12"
|
|
name="msgdma_tx_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d00"
|
|
end="0x00000000018403d20"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="10"
|
|
name="msgdma_rx_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403ce0"
|
|
end="0x00000000018403d00"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="14"
|
|
name="onchip_flash_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d60"
|
|
end="0x00000000018403d68"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="20"
|
|
name="udp_generator_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403cc0"
|
|
end="0x00000000018403ce0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="17"
|
|
name="sensor_interface_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d50"
|
|
end="0x00000000018403d60"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="15"
|
|
name="onchip_flash_data_translator.avalon_universal_slave_0"
|
|
start="0x0000000018200000"
|
|
end="0x00000000018400000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="2"
|
|
name="cpu_debug_mem_slave_translator.avalon_universal_slave_0"
|
|
start="0x0000000018402800"
|
|
end="0x00000000018403000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="13"
|
|
name="msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403ca0"
|
|
end="0x00000000018403cc0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="11"
|
|
name="msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c80"
|
|
end="0x00000000018403ca0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="18"
|
|
name="sys_clk_timer_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c60"
|
|
end="0x00000000018403c80"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="16"
|
|
name="output_pio_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c40"
|
|
end="0x00000000018403c60"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="0"
|
|
name="button_pio_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d40"
|
|
end="0x00000000018403d50"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="4"
|
|
name="debug_uart_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c20"
|
|
end="0x00000000018403c40"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="9"
|
|
name="frame_timer_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c00"
|
|
end="0x00000000018403c20"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="1"
|
|
name="calibration_ram_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403400"
|
|
end="0x00000000018403800"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {cpu_data_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_data_master_agent} {ID} {0};set_instance_parameter_value {cpu_data_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {cpu_data_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_data_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_data_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_agent} {USE_WRITERESPONSE} {0};add_instance {cpu_instruction_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_instruction_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_instruction_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="8"
|
|
name="ext_flash_avl_mem_translator.avalon_universal_slave_0"
|
|
start="0x0000000014000000"
|
|
end="0x00000000018000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="15"
|
|
name="onchip_flash_data_translator.avalon_universal_slave_0"
|
|
start="0x0000000018200000"
|
|
end="0x00000000018400000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="2"
|
|
name="cpu_debug_mem_slave_translator.avalon_universal_slave_0"
|
|
start="0x0000000018402800"
|
|
end="0x00000000018403000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {cpu_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_instruction_master_agent} {ID} {1};set_instance_parameter_value {cpu_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {cpu_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_mm_read_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_tx_mm_read_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ID} {7};set_instance_parameter_value {msgdma_tx_mm_read_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_mm_read_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_mm_read_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_rx_mm_write_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_rx_mm_write_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ID} {4};set_instance_parameter_value {msgdma_rx_mm_write_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_mm_write_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_mm_write_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_descriptor_read_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ID} {5};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_rx_descriptor_read_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ID} {2};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_descriptor_write_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ID} {6};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {USE_WRITERESPONSE} {1};add_instance {msgdma_rx_descriptor_write_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ID} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {USE_WRITERESPONSE} {1};add_instance {ddr3_ram_avl_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ddr3_ram_avl_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ddr3_ram_avl_agent} {ST_DATA_W} {121};set_instance_parameter_value {ddr3_ram_avl_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {AVS_BURSTCOUNT_W} {5};set_instance_parameter_value {ddr3_ram_avl_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ddr3_ram_avl_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ddr3_ram_avl_agent} {MAX_BYTE_CNT} {16};set_instance_parameter_value {ddr3_ram_avl_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {ddr3_ram_avl_agent} {ID} {3};set_instance_parameter_value {ddr3_ram_avl_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {ECC_ENABLE} {0};add_instance {ddr3_ram_avl_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {FIFO_DEPTH} {33};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ddr3_ram_avl_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {FIFO_DEPTH} {64};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {EMPTY_LATENCY} {3};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ext_flash_avl_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {ext_flash_avl_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ext_flash_avl_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {ext_flash_avl_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {ext_flash_avl_csr_agent} {ID} {7};set_instance_parameter_value {ext_flash_avl_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {ECC_ENABLE} {0};add_instance {ext_flash_avl_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_csr_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_mem_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ext_flash_avl_mem_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_mem_agent} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_mem_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {AVS_BURSTCOUNT_W} {9};set_instance_parameter_value {ext_flash_avl_mem_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {ext_flash_avl_mem_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_mem_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ext_flash_avl_mem_agent} {MAX_BYTE_CNT} {256};set_instance_parameter_value {ext_flash_avl_mem_agent} {MAX_BURSTWRAP} {255};set_instance_parameter_value {ext_flash_avl_mem_agent} {ID} {8};set_instance_parameter_value {ext_flash_avl_mem_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {ECC_ENABLE} {0};add_instance {ext_flash_avl_mem_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_mem_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {eth_tse_control_port_agent} {altera_merlin_slave_agent};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DATA_H} {31};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DATA_L} {0};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {eth_tse_control_port_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {eth_tse_control_port_agent} {ST_DATA_W} {121};set_instance_parameter_value {eth_tse_control_port_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {eth_tse_control_port_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {eth_tse_control_port_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {eth_tse_control_port_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {eth_tse_control_port_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {eth_tse_control_port_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {eth_tse_control_port_agent} {ID} {6};set_instance_parameter_value {eth_tse_control_port_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_agent} {ECC_ENABLE} {0};add_instance {eth_tse_control_port_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sysid_control_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sysid_control_slave_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sysid_control_slave_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sysid_control_slave_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sysid_control_slave_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sysid_control_slave_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sysid_control_slave_agent} {ST_DATA_W} {121};set_instance_parameter_value {sysid_control_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sysid_control_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sysid_control_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sysid_control_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sysid_control_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sysid_control_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sysid_control_slave_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sysid_control_slave_agent} {ID} {19};set_instance_parameter_value {sysid_control_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sysid_control_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sysid_control_slave_agent} {ECC_ENABLE} {0};add_instance {sysid_control_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_tx_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_tx_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_tx_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_tx_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_tx_csr_agent} {ID} {12};set_instance_parameter_value {msgdma_tx_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_tx_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_rx_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_rx_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_rx_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_rx_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_rx_csr_agent} {ID} {10};set_instance_parameter_value {msgdma_rx_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_rx_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {onchip_flash_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_flash_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {onchip_flash_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {onchip_flash_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {onchip_flash_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_flash_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_flash_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_flash_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {onchip_flash_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {onchip_flash_csr_agent} {ID} {14};set_instance_parameter_value {onchip_flash_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_agent} {ECC_ENABLE} {0};add_instance {onchip_flash_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {udp_generator_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {udp_generator_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {udp_generator_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {udp_generator_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {udp_generator_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {udp_generator_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {udp_generator_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {udp_generator_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {udp_generator_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {udp_generator_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {udp_generator_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {udp_generator_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {udp_generator_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {udp_generator_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {udp_generator_csr_agent} {ID} {20};set_instance_parameter_value {udp_generator_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {udp_generator_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {udp_generator_csr_agent} {ECC_ENABLE} {0};add_instance {udp_generator_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sensor_interface_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sensor_interface_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sensor_interface_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {sensor_interface_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sensor_interface_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sensor_interface_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sensor_interface_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sensor_interface_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sensor_interface_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sensor_interface_csr_agent} {ID} {17};set_instance_parameter_value {sensor_interface_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_agent} {ECC_ENABLE} {0};add_instance {sensor_interface_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {onchip_flash_data_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {onchip_flash_data_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {onchip_flash_data_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {onchip_flash_data_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {onchip_flash_data_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DATA_H} {31};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_flash_data_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {onchip_flash_data_agent} {ST_DATA_W} {121};set_instance_parameter_value {onchip_flash_data_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_agent} {AVS_BURSTCOUNT_W} {6};set_instance_parameter_value {onchip_flash_data_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_data_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_flash_data_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_flash_data_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_flash_data_agent} {MAX_BYTE_CNT} {32};set_instance_parameter_value {onchip_flash_data_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {onchip_flash_data_agent} {ID} {15};set_instance_parameter_value {onchip_flash_data_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_data_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_data_agent} {ECC_ENABLE} {0};add_instance {onchip_flash_data_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {cpu_debug_mem_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_debug_mem_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ID} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ECC_ENABLE} {0};add_instance {cpu_debug_mem_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_tx_prefetcher_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ID} {13};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_rx_prefetcher_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ID} {11};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {descriptor_memory_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {descriptor_memory_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {descriptor_memory_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {descriptor_memory_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {descriptor_memory_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {descriptor_memory_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {descriptor_memory_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {descriptor_memory_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {descriptor_memory_s1_agent} {ID} {5};set_instance_parameter_value {descriptor_memory_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {ECC_ENABLE} {0};add_instance {descriptor_memory_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sys_clk_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sys_clk_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sys_clk_timer_s1_agent} {ID} {18};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {ECC_ENABLE} {0};add_instance {sys_clk_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {output_pio_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {output_pio_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {output_pio_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {output_pio_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {output_pio_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {output_pio_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {output_pio_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {output_pio_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {output_pio_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {output_pio_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {output_pio_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {output_pio_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {output_pio_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {output_pio_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {output_pio_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {output_pio_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {output_pio_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {output_pio_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {output_pio_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {output_pio_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {output_pio_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {output_pio_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {output_pio_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {output_pio_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {output_pio_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {output_pio_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {output_pio_s1_agent} {ID} {16};set_instance_parameter_value {output_pio_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {output_pio_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {output_pio_s1_agent} {ECC_ENABLE} {0};add_instance {output_pio_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {button_pio_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {button_pio_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {button_pio_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {button_pio_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {button_pio_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {button_pio_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {button_pio_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {button_pio_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {button_pio_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {button_pio_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {button_pio_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {button_pio_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {button_pio_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {button_pio_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {button_pio_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {button_pio_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {button_pio_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {button_pio_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {button_pio_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {button_pio_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {button_pio_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {button_pio_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {button_pio_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {button_pio_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {button_pio_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {button_pio_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {button_pio_s1_agent} {ID} {0};set_instance_parameter_value {button_pio_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {button_pio_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {button_pio_s1_agent} {ECC_ENABLE} {0};add_instance {button_pio_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {debug_uart_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {debug_uart_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {debug_uart_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {debug_uart_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {debug_uart_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {debug_uart_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {debug_uart_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {debug_uart_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {debug_uart_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {debug_uart_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {debug_uart_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {debug_uart_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {debug_uart_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {debug_uart_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {debug_uart_s1_agent} {ID} {4};set_instance_parameter_value {debug_uart_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {debug_uart_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {debug_uart_s1_agent} {ECC_ENABLE} {0};add_instance {debug_uart_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {frame_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {frame_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {frame_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {frame_timer_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {frame_timer_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {frame_timer_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {frame_timer_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {frame_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {frame_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {frame_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {frame_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {frame_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {frame_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {frame_timer_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {frame_timer_s1_agent} {ID} {9};set_instance_parameter_value {frame_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {frame_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {frame_timer_s1_agent} {ECC_ENABLE} {0};add_instance {frame_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {calibration_ram_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_LOCK} {51};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BEGIN_BURST} {78};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_PROTECTION_H} {93};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_PROTECTION_L} {91};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_POSTED} {48};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_READ} {50};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SRC_ID_H} {84};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SRC_ID_L} {80};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DEST_ID_H} {89};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DEST_ID_L} {85};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {calibration_ram_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_agent} {ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_agent} {AVS_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {calibration_ram_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {calibration_ram_s1_agent} {MAX_BYTE_CNT} {2};set_instance_parameter_value {calibration_ram_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {calibration_ram_s1_agent} {ID} {1};set_instance_parameter_value {calibration_ram_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_agent} {ECC_ENABLE} {0};add_instance {calibration_ram_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {104};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {3 8 15 5 2 6 1 9 4 16 18 11 13 20 10 12 7 0 17 14 19 };set_instance_parameter_value {router} {CHANNEL_ID} {000000000000000000001 000000000000000000100 000000000010000000000 000000100000000000000 000000000100000000000 000000000000000001000 100000000000000000000 010000000000000000000 001000000000000000000 000010000000000000000 000001000000000000000 000000010000000000000 000000001000000000000 000000000000100000000 000000000000001000000 000000000000000100000 000000000000000000010 000100000000000000000 000000000001000000000 000000000000010000000 000000000000000010000 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both both both both both both both both both both both both both both both both both read both both read };set_instance_parameter_value {router} {START_ADDRESS} {0x8000000 0x14000000 0x18200000 0x18400000 0x18402800 0x18403000 0x18403400 0x18403c00 0x18403c20 0x18403c40 0x18403c60 0x18403c80 0x18403ca0 0x18403cc0 0x18403ce0 0x18403d00 0x18403d20 0x18403d40 0x18403d50 0x18403d60 0x18403d68 };set_instance_parameter_value {router} {END_ADDRESS} {0x10000000 0x18000000 0x18400000 0x18402000 0x18403000 0x18403400 0x18403800 0x18403c20 0x18403c40 0x18403c60 0x18403c80 0x18403ca0 0x18403cc0 0x18403ce0 0x18403d00 0x18403d20 0x18403d40 0x18403d50 0x18403d60 0x18403d68 0x18403d70 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {64};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router} {PKT_TRANS_READ} {68};set_instance_parameter_value {router} {ST_DATA_W} {121};set_instance_parameter_value {router} {ST_CHANNEL_W} {21};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {3};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {3 8 15 2 };set_instance_parameter_value {router_001} {CHANNEL_ID} {0001 0010 0100 1000 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both both both both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x8000000 0x14000000 0x18200000 0x18402800 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x10000000 0x18000000 0x18400000 0x18403000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {64};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_001} {ST_DATA_W} {121};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {3 };set_instance_parameter_value {router_002} {CHANNEL_ID} {1 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x8000000 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x10000000 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {64};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_002} {ST_DATA_W} {121};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_002} {DECODER_TYPE} {0};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {3 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_003} {START_ADDRESS} {0x8000000 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x10000000 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {64};set_instance_parameter_value {router_003} {PKT_ADDR_L} {36};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_003} {ST_DATA_W} {121};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_003} {DECODER_TYPE} {0};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {5 };set_instance_parameter_value {router_004} {CHANNEL_ID} {1 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_004} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {64};set_instance_parameter_value {router_004} {PKT_ADDR_L} {36};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_004} {ST_DATA_W} {121};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_004} {DECODER_TYPE} {0};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {router_005} {altera_merlin_router};set_instance_parameter_value {router_005} {DESTINATION_ID} {5 };set_instance_parameter_value {router_005} {CHANNEL_ID} {1 };set_instance_parameter_value {router_005} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_005} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_005} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_005} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_005} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_005} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_005} {SPAN_OFFSET} {};set_instance_parameter_value {router_005} {PKT_ADDR_H} {64};set_instance_parameter_value {router_005} {PKT_ADDR_L} {36};set_instance_parameter_value {router_005} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_005} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_005} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_005} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_005} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_005} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_005} {ST_DATA_W} {121};set_instance_parameter_value {router_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_005} {DECODER_TYPE} {0};set_instance_parameter_value {router_005} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_005} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_005} {MEMORY_ALIASING_DECODE} {0};add_instance {router_006} {altera_merlin_router};set_instance_parameter_value {router_006} {DESTINATION_ID} {5 };set_instance_parameter_value {router_006} {CHANNEL_ID} {1 };set_instance_parameter_value {router_006} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_006} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_006} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_006} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_006} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_006} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_006} {SPAN_OFFSET} {};set_instance_parameter_value {router_006} {PKT_ADDR_H} {64};set_instance_parameter_value {router_006} {PKT_ADDR_L} {36};set_instance_parameter_value {router_006} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_006} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_006} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_006} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_006} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_006} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_006} {ST_DATA_W} {121};set_instance_parameter_value {router_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_006} {DECODER_TYPE} {0};set_instance_parameter_value {router_006} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_006} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_006} {MEMORY_ALIASING_DECODE} {0};add_instance {router_007} {altera_merlin_router};set_instance_parameter_value {router_007} {DESTINATION_ID} {5 };set_instance_parameter_value {router_007} {CHANNEL_ID} {1 };set_instance_parameter_value {router_007} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_007} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_007} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_007} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_007} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_007} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_007} {SPAN_OFFSET} {};set_instance_parameter_value {router_007} {PKT_ADDR_H} {64};set_instance_parameter_value {router_007} {PKT_ADDR_L} {36};set_instance_parameter_value {router_007} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_007} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_007} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_007} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_007} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_007} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_007} {ST_DATA_W} {121};set_instance_parameter_value {router_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_007} {DECODER_TYPE} {0};set_instance_parameter_value {router_007} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_007} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_007} {MEMORY_ALIASING_DECODE} {0};add_instance {router_008} {altera_merlin_router};set_instance_parameter_value {router_008} {DESTINATION_ID} {0 1 7 4 };set_instance_parameter_value {router_008} {CHANNEL_ID} {0001 0010 0100 1000 };set_instance_parameter_value {router_008} {TYPE_OF_TRANSACTION} {both read read write };set_instance_parameter_value {router_008} {START_ADDRESS} {0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_008} {END_ADDRESS} {0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_008} {NON_SECURED_TAG} {1 1 1 1 };set_instance_parameter_value {router_008} {SECURED_RANGE_PAIRS} {0 0 0 0 };set_instance_parameter_value {router_008} {SECURED_RANGE_LIST} {0 0 0 0 };set_instance_parameter_value {router_008} {SPAN_OFFSET} {};set_instance_parameter_value {router_008} {PKT_ADDR_H} {64};set_instance_parameter_value {router_008} {PKT_ADDR_L} {36};set_instance_parameter_value {router_008} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_008} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_008} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_008} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_008} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_008} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_008} {ST_DATA_W} {121};set_instance_parameter_value {router_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_008} {DECODER_TYPE} {1};set_instance_parameter_value {router_008} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_008} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_008} {MEMORY_ALIASING_DECODE} {0};add_instance {router_009} {altera_merlin_router};set_instance_parameter_value {router_009} {DESTINATION_ID} {0 };set_instance_parameter_value {router_009} {CHANNEL_ID} {1 };set_instance_parameter_value {router_009} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_009} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_009} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_009} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_009} {SPAN_OFFSET} {};set_instance_parameter_value {router_009} {PKT_ADDR_H} {64};set_instance_parameter_value {router_009} {PKT_ADDR_L} {36};set_instance_parameter_value {router_009} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_009} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_009} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_009} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_009} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_009} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_009} {ST_DATA_W} {121};set_instance_parameter_value {router_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_009} {DECODER_TYPE} {1};set_instance_parameter_value {router_009} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_009} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_009} {MEMORY_ALIASING_DECODE} {0};add_instance {router_010} {altera_merlin_router};set_instance_parameter_value {router_010} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_010} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_010} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_010} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_010} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_010} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_010} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_010} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_010} {SPAN_OFFSET} {};set_instance_parameter_value {router_010} {PKT_ADDR_H} {64};set_instance_parameter_value {router_010} {PKT_ADDR_L} {36};set_instance_parameter_value {router_010} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_010} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_010} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_010} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_010} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_010} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_010} {ST_DATA_W} {121};set_instance_parameter_value {router_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_010} {DECODER_TYPE} {1};set_instance_parameter_value {router_010} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_010} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_010} {MEMORY_ALIASING_DECODE} {0};add_instance {router_011} {altera_merlin_router};set_instance_parameter_value {router_011} {DESTINATION_ID} {0 };set_instance_parameter_value {router_011} {CHANNEL_ID} {1 };set_instance_parameter_value {router_011} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_011} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_011} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_011} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_011} {SPAN_OFFSET} {};set_instance_parameter_value {router_011} {PKT_ADDR_H} {64};set_instance_parameter_value {router_011} {PKT_ADDR_L} {36};set_instance_parameter_value {router_011} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_011} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_011} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_011} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_011} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_011} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_011} {ST_DATA_W} {121};set_instance_parameter_value {router_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_011} {DECODER_TYPE} {1};set_instance_parameter_value {router_011} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_011} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_011} {MEMORY_ALIASING_DECODE} {0};add_instance {router_012} {altera_merlin_router};set_instance_parameter_value {router_012} {DESTINATION_ID} {0 };set_instance_parameter_value {router_012} {CHANNEL_ID} {1 };set_instance_parameter_value {router_012} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_012} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_012} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_012} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_012} {SPAN_OFFSET} {};set_instance_parameter_value {router_012} {PKT_ADDR_H} {64};set_instance_parameter_value {router_012} {PKT_ADDR_L} {36};set_instance_parameter_value {router_012} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_012} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_012} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_012} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_012} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_012} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_012} {ST_DATA_W} {121};set_instance_parameter_value {router_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_012} {DECODER_TYPE} {1};set_instance_parameter_value {router_012} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_012} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_012} {MEMORY_ALIASING_DECODE} {0};add_instance {router_013} {altera_merlin_router};set_instance_parameter_value {router_013} {DESTINATION_ID} {0 };set_instance_parameter_value {router_013} {CHANNEL_ID} {1 };set_instance_parameter_value {router_013} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_013} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_013} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_013} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_013} {SPAN_OFFSET} {};set_instance_parameter_value {router_013} {PKT_ADDR_H} {64};set_instance_parameter_value {router_013} {PKT_ADDR_L} {36};set_instance_parameter_value {router_013} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_013} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_013} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_013} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_013} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_013} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_013} {ST_DATA_W} {121};set_instance_parameter_value {router_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_013} {DECODER_TYPE} {1};set_instance_parameter_value {router_013} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_013} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_013} {MEMORY_ALIASING_DECODE} {0};add_instance {router_014} {altera_merlin_router};set_instance_parameter_value {router_014} {DESTINATION_ID} {0 };set_instance_parameter_value {router_014} {CHANNEL_ID} {1 };set_instance_parameter_value {router_014} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_014} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_014} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_014} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_014} {SPAN_OFFSET} {};set_instance_parameter_value {router_014} {PKT_ADDR_H} {64};set_instance_parameter_value {router_014} {PKT_ADDR_L} {36};set_instance_parameter_value {router_014} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_014} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_014} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_014} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_014} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_014} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_014} {ST_DATA_W} {121};set_instance_parameter_value {router_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_014} {DECODER_TYPE} {1};set_instance_parameter_value {router_014} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_014} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_014} {MEMORY_ALIASING_DECODE} {0};add_instance {router_015} {altera_merlin_router};set_instance_parameter_value {router_015} {DESTINATION_ID} {0 };set_instance_parameter_value {router_015} {CHANNEL_ID} {1 };set_instance_parameter_value {router_015} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_015} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_015} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_015} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_015} {SPAN_OFFSET} {};set_instance_parameter_value {router_015} {PKT_ADDR_H} {64};set_instance_parameter_value {router_015} {PKT_ADDR_L} {36};set_instance_parameter_value {router_015} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_015} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_015} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_015} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_015} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_015} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_015} {ST_DATA_W} {121};set_instance_parameter_value {router_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_015} {DECODER_TYPE} {1};set_instance_parameter_value {router_015} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_015} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_015} {MEMORY_ALIASING_DECODE} {0};add_instance {router_016} {altera_merlin_router};set_instance_parameter_value {router_016} {DESTINATION_ID} {0 };set_instance_parameter_value {router_016} {CHANNEL_ID} {1 };set_instance_parameter_value {router_016} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_016} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_016} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_016} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_016} {SPAN_OFFSET} {};set_instance_parameter_value {router_016} {PKT_ADDR_H} {64};set_instance_parameter_value {router_016} {PKT_ADDR_L} {36};set_instance_parameter_value {router_016} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_016} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_016} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_016} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_016} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_016} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_016} {ST_DATA_W} {121};set_instance_parameter_value {router_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_016} {DECODER_TYPE} {1};set_instance_parameter_value {router_016} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_016} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_016} {MEMORY_ALIASING_DECODE} {0};add_instance {router_017} {altera_merlin_router};set_instance_parameter_value {router_017} {DESTINATION_ID} {0 };set_instance_parameter_value {router_017} {CHANNEL_ID} {1 };set_instance_parameter_value {router_017} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_017} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_017} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_017} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_017} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_017} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_017} {SPAN_OFFSET} {};set_instance_parameter_value {router_017} {PKT_ADDR_H} {64};set_instance_parameter_value {router_017} {PKT_ADDR_L} {36};set_instance_parameter_value {router_017} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_017} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_017} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_017} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_017} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_017} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_017} {ST_DATA_W} {121};set_instance_parameter_value {router_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_017} {DECODER_TYPE} {1};set_instance_parameter_value {router_017} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_017} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_017} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_017} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_017} {MEMORY_ALIASING_DECODE} {0};add_instance {router_018} {altera_merlin_router};set_instance_parameter_value {router_018} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_018} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_018} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_018} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_018} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_018} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_018} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_018} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_018} {SPAN_OFFSET} {};set_instance_parameter_value {router_018} {PKT_ADDR_H} {64};set_instance_parameter_value {router_018} {PKT_ADDR_L} {36};set_instance_parameter_value {router_018} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_018} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_018} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_018} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_018} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_018} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_018} {ST_DATA_W} {121};set_instance_parameter_value {router_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_018} {DECODER_TYPE} {1};set_instance_parameter_value {router_018} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_018} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_018} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_018} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_018} {MEMORY_ALIASING_DECODE} {0};add_instance {router_019} {altera_merlin_router};set_instance_parameter_value {router_019} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_019} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_019} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_019} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_019} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_019} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_019} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_019} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_019} {SPAN_OFFSET} {};set_instance_parameter_value {router_019} {PKT_ADDR_H} {64};set_instance_parameter_value {router_019} {PKT_ADDR_L} {36};set_instance_parameter_value {router_019} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_019} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_019} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_019} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_019} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_019} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_019} {ST_DATA_W} {121};set_instance_parameter_value {router_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_019} {DECODER_TYPE} {1};set_instance_parameter_value {router_019} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_019} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_019} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_019} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_019} {MEMORY_ALIASING_DECODE} {0};add_instance {router_020} {altera_merlin_router};set_instance_parameter_value {router_020} {DESTINATION_ID} {0 };set_instance_parameter_value {router_020} {CHANNEL_ID} {1 };set_instance_parameter_value {router_020} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_020} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_020} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_020} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_020} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_020} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_020} {SPAN_OFFSET} {};set_instance_parameter_value {router_020} {PKT_ADDR_H} {64};set_instance_parameter_value {router_020} {PKT_ADDR_L} {36};set_instance_parameter_value {router_020} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_020} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_020} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_020} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_020} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_020} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_020} {ST_DATA_W} {121};set_instance_parameter_value {router_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_020} {DECODER_TYPE} {1};set_instance_parameter_value {router_020} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_020} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_020} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_020} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_020} {MEMORY_ALIASING_DECODE} {0};add_instance {router_021} {altera_merlin_router};set_instance_parameter_value {router_021} {DESTINATION_ID} {0 };set_instance_parameter_value {router_021} {CHANNEL_ID} {1 };set_instance_parameter_value {router_021} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_021} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_021} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_021} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_021} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_021} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_021} {SPAN_OFFSET} {};set_instance_parameter_value {router_021} {PKT_ADDR_H} {64};set_instance_parameter_value {router_021} {PKT_ADDR_L} {36};set_instance_parameter_value {router_021} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_021} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_021} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_021} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_021} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_021} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_021} {ST_DATA_W} {121};set_instance_parameter_value {router_021} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_021} {DECODER_TYPE} {1};set_instance_parameter_value {router_021} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_021} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_021} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_021} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_021} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_021} {MEMORY_ALIASING_DECODE} {0};add_instance {router_022} {altera_merlin_router};set_instance_parameter_value {router_022} {DESTINATION_ID} {0 5 2 6 3 };set_instance_parameter_value {router_022} {CHANNEL_ID} {00001 00010 00100 01000 10000 };set_instance_parameter_value {router_022} {TYPE_OF_TRANSACTION} {both read read write write };set_instance_parameter_value {router_022} {START_ADDRESS} {0x0 0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_022} {END_ADDRESS} {0x0 0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_022} {NON_SECURED_TAG} {1 1 1 1 1 };set_instance_parameter_value {router_022} {SECURED_RANGE_PAIRS} {0 0 0 0 0 };set_instance_parameter_value {router_022} {SECURED_RANGE_LIST} {0 0 0 0 0 };set_instance_parameter_value {router_022} {SPAN_OFFSET} {};set_instance_parameter_value {router_022} {PKT_ADDR_H} {64};set_instance_parameter_value {router_022} {PKT_ADDR_L} {36};set_instance_parameter_value {router_022} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_022} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_022} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_022} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_022} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_022} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_022} {ST_DATA_W} {121};set_instance_parameter_value {router_022} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_022} {DECODER_TYPE} {1};set_instance_parameter_value {router_022} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_022} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_022} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_022} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_022} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_022} {MEMORY_ALIASING_DECODE} {0};add_instance {router_023} {altera_merlin_router};set_instance_parameter_value {router_023} {DESTINATION_ID} {0 };set_instance_parameter_value {router_023} {CHANNEL_ID} {1 };set_instance_parameter_value {router_023} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_023} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_023} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_023} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_023} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_023} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_023} {SPAN_OFFSET} {};set_instance_parameter_value {router_023} {PKT_ADDR_H} {64};set_instance_parameter_value {router_023} {PKT_ADDR_L} {36};set_instance_parameter_value {router_023} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_023} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_023} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_023} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_023} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_023} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_023} {ST_DATA_W} {121};set_instance_parameter_value {router_023} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_023} {DECODER_TYPE} {1};set_instance_parameter_value {router_023} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_023} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_023} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_023} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_023} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_023} {MEMORY_ALIASING_DECODE} {0};add_instance {router_024} {altera_merlin_router};set_instance_parameter_value {router_024} {DESTINATION_ID} {0 };set_instance_parameter_value {router_024} {CHANNEL_ID} {1 };set_instance_parameter_value {router_024} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_024} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_024} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_024} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_024} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_024} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_024} {SPAN_OFFSET} {};set_instance_parameter_value {router_024} {PKT_ADDR_H} {64};set_instance_parameter_value {router_024} {PKT_ADDR_L} {36};set_instance_parameter_value {router_024} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_024} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_024} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_024} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_024} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_024} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_024} {ST_DATA_W} {121};set_instance_parameter_value {router_024} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_024} {DECODER_TYPE} {1};set_instance_parameter_value {router_024} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_024} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_024} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_024} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_024} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_024} {MEMORY_ALIASING_DECODE} {0};add_instance {router_025} {altera_merlin_router};set_instance_parameter_value {router_025} {DESTINATION_ID} {0 };set_instance_parameter_value {router_025} {CHANNEL_ID} {1 };set_instance_parameter_value {router_025} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_025} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_025} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_025} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_025} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_025} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_025} {SPAN_OFFSET} {};set_instance_parameter_value {router_025} {PKT_ADDR_H} {64};set_instance_parameter_value {router_025} {PKT_ADDR_L} {36};set_instance_parameter_value {router_025} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_025} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_025} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_025} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_025} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_025} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_025} {ST_DATA_W} {121};set_instance_parameter_value {router_025} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_025} {DECODER_TYPE} {1};set_instance_parameter_value {router_025} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_025} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_025} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_025} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_025} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_025} {MEMORY_ALIASING_DECODE} {0};add_instance {router_026} {altera_merlin_router};set_instance_parameter_value {router_026} {DESTINATION_ID} {0 };set_instance_parameter_value {router_026} {CHANNEL_ID} {1 };set_instance_parameter_value {router_026} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_026} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_026} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_026} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_026} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_026} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_026} {SPAN_OFFSET} {};set_instance_parameter_value {router_026} {PKT_ADDR_H} {64};set_instance_parameter_value {router_026} {PKT_ADDR_L} {36};set_instance_parameter_value {router_026} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_026} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_026} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_026} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_026} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_026} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_026} {ST_DATA_W} {121};set_instance_parameter_value {router_026} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_026} {DECODER_TYPE} {1};set_instance_parameter_value {router_026} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_026} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_026} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_026} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_026} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_026} {MEMORY_ALIASING_DECODE} {0};add_instance {router_027} {altera_merlin_router};set_instance_parameter_value {router_027} {DESTINATION_ID} {0 };set_instance_parameter_value {router_027} {CHANNEL_ID} {1 };set_instance_parameter_value {router_027} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_027} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_027} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_027} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_027} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_027} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_027} {SPAN_OFFSET} {};set_instance_parameter_value {router_027} {PKT_ADDR_H} {64};set_instance_parameter_value {router_027} {PKT_ADDR_L} {36};set_instance_parameter_value {router_027} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_027} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_027} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_027} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_027} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_027} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_027} {ST_DATA_W} {121};set_instance_parameter_value {router_027} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_027} {DECODER_TYPE} {1};set_instance_parameter_value {router_027} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_027} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_027} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_027} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_027} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_027} {MEMORY_ALIASING_DECODE} {0};add_instance {router_028} {altera_merlin_router};set_instance_parameter_value {router_028} {DESTINATION_ID} {0 };set_instance_parameter_value {router_028} {CHANNEL_ID} {1 };set_instance_parameter_value {router_028} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_028} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_028} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_028} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_028} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_028} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_028} {SPAN_OFFSET} {};set_instance_parameter_value {router_028} {PKT_ADDR_H} {46};set_instance_parameter_value {router_028} {PKT_ADDR_L} {18};set_instance_parameter_value {router_028} {PKT_PROTECTION_H} {93};set_instance_parameter_value {router_028} {PKT_PROTECTION_L} {91};set_instance_parameter_value {router_028} {PKT_DEST_ID_H} {89};set_instance_parameter_value {router_028} {PKT_DEST_ID_L} {85};set_instance_parameter_value {router_028} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {router_028} {PKT_TRANS_READ} {50};set_instance_parameter_value {router_028} {ST_DATA_W} {103};set_instance_parameter_value {router_028} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_028} {DECODER_TYPE} {1};set_instance_parameter_value {router_028} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_028} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_028} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_028} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_028} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {router_028} {MEMORY_ALIASING_DECODE} {0};add_instance {cpu_data_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {cpu_data_master_limiter} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_data_master_limiter} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_data_master_limiter} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_data_master_limiter} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_data_master_limiter} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_data_master_limiter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_data_master_limiter} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_data_master_limiter} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_data_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {cpu_data_master_limiter} {MAX_OUTSTANDING_RESPONSES} {36};set_instance_parameter_value {cpu_data_master_limiter} {PIPELINED} {0};set_instance_parameter_value {cpu_data_master_limiter} {ST_DATA_W} {121};set_instance_parameter_value {cpu_data_master_limiter} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_data_master_limiter} {VALID_WIDTH} {21};set_instance_parameter_value {cpu_data_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {cpu_data_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {cpu_data_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {cpu_data_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {cpu_data_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_data_master_limiter} {REORDER} {0};add_instance {cpu_instruction_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_instruction_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {MAX_OUTSTANDING_RESPONSES} {36};set_instance_parameter_value {cpu_instruction_master_limiter} {PIPELINED} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {ST_DATA_W} {121};set_instance_parameter_value {cpu_instruction_master_limiter} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_instruction_master_limiter} {VALID_WIDTH} {21};set_instance_parameter_value {cpu_instruction_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_limiter} {REORDER} {0};add_instance {ext_flash_avl_mem_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_BURSTWRAP_H} {87};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {COMPRESSED_READ_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BURSTWRAP_CONST_MASK} {3};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BURSTWRAP_CONST_VALUE} {3};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {calibration_ram_s1_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BEGIN_BURST} {78};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_READ} {50};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_BYTE_CNT_H} {54};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {COMPRESSED_READ_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BURSTWRAP_CONST_MASK} {511};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BURSTWRAP_CONST_VALUE} {511};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {21};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {21};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {4};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {21};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_002} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_002} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_003} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_004} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_005} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_006} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_007} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {4};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_003} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_003} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_003} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_004} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_004} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_004} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_005} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_005} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_005} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_006} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_006} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_006} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_007} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_007} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_007} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_008} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_008} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_008} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_008} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_008} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_008} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_009} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_009} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_009} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_009} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_009} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_009} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_010} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_010} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_010} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_010} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_010} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_010} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_011} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_011} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_011} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_011} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_011} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_011} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_012} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_012} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_012} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_012} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_012} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_012} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_013} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_013} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_013} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_013} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_013} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_013} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_014} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_014} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_014} {NUM_INPUTS} {5};set_instance_parameter_value {cmd_mux_014} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_014} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_014} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SHARES} {1 1 1 1 1 };set_instance_parameter_value {cmd_mux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_015} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_015} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_015} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_015} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_015} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_015} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_015} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_015} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_016} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_016} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_016} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_016} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_016} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_016} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_016} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_016} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_017} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_017} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_017} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_017} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_017} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_017} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_017} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_017} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_018} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_018} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_018} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_018} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_018} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_018} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_018} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_018} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_019} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_019} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_019} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_019} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_019} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_019} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_019} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_019} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_020} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_020} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_020} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_020} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_020} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_020} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_020} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_020} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {4};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_003} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_004} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_005} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_006} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_007} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_008} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_008} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_008} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_008} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_009} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_009} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_009} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_009} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_010} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_010} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_010} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_010} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_011} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_011} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_011} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_011} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_012} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_012} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_012} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_012} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_013} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_013} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_013} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_013} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_014} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_014} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_014} {NUM_OUTPUTS} {5};set_instance_parameter_value {rsp_demux_014} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_015} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_015} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_015} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_015} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_016} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_016} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_016} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_016} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_017} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_017} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_017} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_017} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_018} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_018} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_018} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_018} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_019} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_019} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_019} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_019} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_020} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_020} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_020} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_020} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {21};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {4};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_002} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_002} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_002} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_002} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_002} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_003} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_003} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_003} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_003} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_004} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_004} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_004} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_004} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_005} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_005} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_005} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_005} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_006} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_006} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_006} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_006} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_007} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_007} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_007} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_007} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {calibration_ram_s1_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {52};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ADDR_H} {64};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ADDR_L} {36};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_DATA_H} {31};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {35};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {32};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {79};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {71};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {91};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {89};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {93};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {92};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_ST_DATA_W} {121};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {calibration_ram_s1_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ADDR_H} {64};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ADDR_L} {36};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_DATA_H} {31};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_H} {35};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_L} {32};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {79};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {71};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_WRITE} {67};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {88};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {80};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {91};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {89};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {93};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {92};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_ST_DATA_W} {121};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {52};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {crosser} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser} {DATA_WIDTH} {121};set_instance_parameter_value {crosser} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser} {USE_PACKETS} {1};set_instance_parameter_value {crosser} {USE_CHANNEL} {1};set_instance_parameter_value {crosser} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser} {USE_ERROR} {0};set_instance_parameter_value {crosser} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_001} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_001} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_001} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_001} {USE_PACKETS} {1};set_instance_parameter_value {crosser_001} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_001} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_001} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_001} {USE_ERROR} {0};set_instance_parameter_value {crosser_001} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_001} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_002} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_002} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_002} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_002} {USE_PACKETS} {1};set_instance_parameter_value {crosser_002} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_002} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_002} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_002} {USE_ERROR} {0};set_instance_parameter_value {crosser_002} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_002} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_003} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_003} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_003} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_003} {USE_PACKETS} {1};set_instance_parameter_value {crosser_003} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_003} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_003} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_003} {USE_ERROR} {0};set_instance_parameter_value {crosser_003} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_003} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_004} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_004} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_004} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_004} {USE_PACKETS} {1};set_instance_parameter_value {crosser_004} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_004} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_004} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_004} {USE_ERROR} {0};set_instance_parameter_value {crosser_004} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_004} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_004} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_004} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_005} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_005} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_005} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_005} {USE_PACKETS} {1};set_instance_parameter_value {crosser_005} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_005} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_005} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_005} {USE_ERROR} {0};set_instance_parameter_value {crosser_005} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_005} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_005} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_005} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_006} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_006} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_006} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_006} {USE_PACKETS} {1};set_instance_parameter_value {crosser_006} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_006} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_006} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_006} {USE_ERROR} {0};set_instance_parameter_value {crosser_006} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_006} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_006} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_006} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_007} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_007} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_007} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_007} {USE_PACKETS} {1};set_instance_parameter_value {crosser_007} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_007} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_007} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_007} {USE_ERROR} {0};set_instance_parameter_value {crosser_007} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_007} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_007} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_007} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_008} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_008} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_008} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_008} {USE_PACKETS} {1};set_instance_parameter_value {crosser_008} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_008} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_008} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_008} {USE_ERROR} {0};set_instance_parameter_value {crosser_008} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_008} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_008} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_008} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_009} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_009} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_009} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_009} {USE_PACKETS} {1};set_instance_parameter_value {crosser_009} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_009} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_009} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_009} {USE_ERROR} {0};set_instance_parameter_value {crosser_009} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_009} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_009} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_009} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_010} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_010} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_010} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_010} {USE_PACKETS} {1};set_instance_parameter_value {crosser_010} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_010} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_010} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_010} {USE_ERROR} {0};set_instance_parameter_value {crosser_010} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_010} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_010} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_010} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_011} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_011} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_011} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_011} {USE_PACKETS} {1};set_instance_parameter_value {crosser_011} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_011} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_011} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_011} {USE_ERROR} {0};set_instance_parameter_value {crosser_011} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_011} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_011} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_011} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_012} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_012} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_012} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_012} {USE_PACKETS} {1};set_instance_parameter_value {crosser_012} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_012} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_012} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_012} {USE_ERROR} {0};set_instance_parameter_value {crosser_012} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_012} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_012} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_012} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_013} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_013} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_013} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_013} {USE_PACKETS} {1};set_instance_parameter_value {crosser_013} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_013} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_013} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_013} {USE_ERROR} {0};set_instance_parameter_value {crosser_013} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_013} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_013} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_013} {USE_OUTPUT_PIPELINE} {0};add_instance {cpu_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {cpu_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {cpu_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {cpu_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {cpu_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ddr3_ram_soft_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ext_flash_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ext_flash_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ext_flash_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ext_flash_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ext_flash_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {eth_tse_reset_connection_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ddr3_ram_avl_translator_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {sys_clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {sys_clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {sys_clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_instance {ddr3_ram_afi_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {ddr3_ram_afi_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {150000000};set_instance_parameter_value {ddr3_ram_afi_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_instance {ext_flash_clock_bridge_out_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {ext_flash_clock_bridge_out_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {0};set_instance_parameter_value {ext_flash_clock_bridge_out_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {cpu_data_master_translator.avalon_universal_master_0} {cpu_data_master_agent.av} {avalon};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {defaultConnection} {false};add_connection {cpu_instruction_master_translator.avalon_universal_master_0} {cpu_instruction_master_agent.av} {avalon};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {defaultConnection} {false};add_connection {msgdma_tx_mm_read_translator.avalon_universal_master_0} {msgdma_tx_mm_read_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {defaultConnection} {false};add_connection {rsp_mux_002.src} {msgdma_tx_mm_read_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_002.src/msgdma_tx_mm_read_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_mm_write_translator.avalon_universal_master_0} {msgdma_rx_mm_write_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {defaultConnection} {false};add_connection {rsp_mux_003.src} {msgdma_rx_mm_write_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_003.src/msgdma_rx_mm_write_agent.rp} {qsys_mm.response};add_connection {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0} {msgdma_tx_descriptor_read_master_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_004.src} {msgdma_tx_descriptor_read_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_004.src/msgdma_tx_descriptor_read_master_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0} {msgdma_rx_descriptor_read_master_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_005.src} {msgdma_rx_descriptor_read_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_005.src/msgdma_rx_descriptor_read_master_agent.rp} {qsys_mm.response};add_connection {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0} {msgdma_tx_descriptor_write_master_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_006.src} {msgdma_tx_descriptor_write_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_006.src/msgdma_tx_descriptor_write_master_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0} {msgdma_rx_descriptor_write_master_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_007.src} {msgdma_rx_descriptor_write_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_007.src/msgdma_rx_descriptor_write_master_agent.rp} {qsys_mm.response};add_connection {ddr3_ram_avl_agent.m0} {ddr3_ram_avl_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ddr3_ram_avl_agent.rf_source} {ddr3_ram_avl_agent_rsp_fifo.in} {avalon_streaming};add_connection {ddr3_ram_avl_agent_rsp_fifo.out} {ddr3_ram_avl_agent.rf_sink} {avalon_streaming};add_connection {ddr3_ram_avl_agent.rdata_fifo_src} {ddr3_ram_avl_agent_rdata_fifo.in} {avalon_streaming};add_connection {ddr3_ram_avl_agent_rdata_fifo.out} {ddr3_ram_avl_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {ddr3_ram_avl_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/ddr3_ram_avl_agent.cp} {qsys_mm.command};add_connection {ext_flash_avl_csr_agent.m0} {ext_flash_avl_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ext_flash_avl_csr_agent.rf_source} {ext_flash_avl_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_csr_agent_rsp_fifo.out} {ext_flash_avl_csr_agent.rf_sink} {avalon_streaming};add_connection {ext_flash_avl_csr_agent.rdata_fifo_src} {ext_flash_avl_csr_agent_rdata_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_csr_agent_rdata_fifo.out} {ext_flash_avl_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_001.src} {ext_flash_avl_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/ext_flash_avl_csr_agent.cp} {qsys_mm.command};add_connection {ext_flash_avl_mem_agent.m0} {ext_flash_avl_mem_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ext_flash_avl_mem_agent.rf_source} {ext_flash_avl_mem_agent_rsp_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_mem_agent_rsp_fifo.out} {ext_flash_avl_mem_agent.rf_sink} {avalon_streaming};add_connection {ext_flash_avl_mem_agent.rdata_fifo_src} {ext_flash_avl_mem_agent_rdata_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_mem_agent_rdata_fifo.out} {ext_flash_avl_mem_agent.rdata_fifo_sink} {avalon_streaming};add_connection {eth_tse_control_port_agent.m0} {eth_tse_control_port_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {eth_tse_control_port_agent.rf_source} {eth_tse_control_port_agent_rsp_fifo.in} {avalon_streaming};add_connection {eth_tse_control_port_agent_rsp_fifo.out} {eth_tse_control_port_agent.rf_sink} {avalon_streaming};add_connection {eth_tse_control_port_agent.rdata_fifo_src} {eth_tse_control_port_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_003.src} {eth_tse_control_port_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_003.src/eth_tse_control_port_agent.cp} {qsys_mm.command};add_connection {sysid_control_slave_agent.m0} {sysid_control_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sysid_control_slave_agent.rf_source} {sysid_control_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sysid_control_slave_agent_rsp_fifo.out} {sysid_control_slave_agent.rf_sink} {avalon_streaming};add_connection {sysid_control_slave_agent.rdata_fifo_src} {sysid_control_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_004.src} {sysid_control_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_004.src/sysid_control_slave_agent.cp} {qsys_mm.command};add_connection {msgdma_tx_csr_agent.m0} {msgdma_tx_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_tx_csr_agent.rf_source} {msgdma_tx_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_tx_csr_agent_rsp_fifo.out} {msgdma_tx_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_tx_csr_agent.rdata_fifo_src} {msgdma_tx_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_005.src} {msgdma_tx_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_005.src/msgdma_tx_csr_agent.cp} {qsys_mm.command};add_connection {msgdma_rx_csr_agent.m0} {msgdma_rx_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_rx_csr_agent.rf_source} {msgdma_rx_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_rx_csr_agent_rsp_fifo.out} {msgdma_rx_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_rx_csr_agent.rdata_fifo_src} {msgdma_rx_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_006.src} {msgdma_rx_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_006.src/msgdma_rx_csr_agent.cp} {qsys_mm.command};add_connection {onchip_flash_csr_agent.m0} {onchip_flash_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_flash_csr_agent.rf_source} {onchip_flash_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_flash_csr_agent_rsp_fifo.out} {onchip_flash_csr_agent.rf_sink} {avalon_streaming};add_connection {onchip_flash_csr_agent.rdata_fifo_src} {onchip_flash_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_007.src} {onchip_flash_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_007.src/onchip_flash_csr_agent.cp} {qsys_mm.command};add_connection {udp_generator_csr_agent.m0} {udp_generator_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {udp_generator_csr_agent.rf_source} {udp_generator_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {udp_generator_csr_agent_rsp_fifo.out} {udp_generator_csr_agent.rf_sink} {avalon_streaming};add_connection {udp_generator_csr_agent.rdata_fifo_src} {udp_generator_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_008.src} {udp_generator_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_008.src/udp_generator_csr_agent.cp} {qsys_mm.command};add_connection {sensor_interface_csr_agent.m0} {sensor_interface_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sensor_interface_csr_agent.rf_source} {sensor_interface_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {sensor_interface_csr_agent_rsp_fifo.out} {sensor_interface_csr_agent.rf_sink} {avalon_streaming};add_connection {sensor_interface_csr_agent.rdata_fifo_src} {sensor_interface_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_009.src} {sensor_interface_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_009.src/sensor_interface_csr_agent.cp} {qsys_mm.command};add_connection {onchip_flash_data_agent.m0} {onchip_flash_data_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_flash_data_agent.rf_source} {onchip_flash_data_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_flash_data_agent_rsp_fifo.out} {onchip_flash_data_agent.rf_sink} {avalon_streaming};add_connection {onchip_flash_data_agent.rdata_fifo_src} {onchip_flash_data_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_010.src} {onchip_flash_data_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_010.src/onchip_flash_data_agent.cp} {qsys_mm.command};add_connection {cpu_debug_mem_slave_agent.m0} {cpu_debug_mem_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {cpu_debug_mem_slave_agent.rf_source} {cpu_debug_mem_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent_rsp_fifo.out} {cpu_debug_mem_slave_agent.rf_sink} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent.rdata_fifo_src} {cpu_debug_mem_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_011.src} {cpu_debug_mem_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_011.src/cpu_debug_mem_slave_agent.cp} {qsys_mm.command};add_connection {msgdma_tx_prefetcher_csr_agent.m0} {msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_tx_prefetcher_csr_agent.rf_source} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_tx_prefetcher_csr_agent_rsp_fifo.out} {msgdma_tx_prefetcher_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_tx_prefetcher_csr_agent.rdata_fifo_src} {msgdma_tx_prefetcher_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_012.src} {msgdma_tx_prefetcher_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_012.src/msgdma_tx_prefetcher_csr_agent.cp} {qsys_mm.command};add_connection {msgdma_rx_prefetcher_csr_agent.m0} {msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_rx_prefetcher_csr_agent.rf_source} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_rx_prefetcher_csr_agent_rsp_fifo.out} {msgdma_rx_prefetcher_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_rx_prefetcher_csr_agent.rdata_fifo_src} {msgdma_rx_prefetcher_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_013.src} {msgdma_rx_prefetcher_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_013.src/msgdma_rx_prefetcher_csr_agent.cp} {qsys_mm.command};add_connection {descriptor_memory_s1_agent.m0} {descriptor_memory_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {descriptor_memory_s1_agent.rf_source} {descriptor_memory_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {descriptor_memory_s1_agent_rsp_fifo.out} {descriptor_memory_s1_agent.rf_sink} {avalon_streaming};add_connection {descriptor_memory_s1_agent.rdata_fifo_src} {descriptor_memory_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_014.src} {descriptor_memory_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_014.src/descriptor_memory_s1_agent.cp} {qsys_mm.command};add_connection {sys_clk_timer_s1_agent.m0} {sys_clk_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sys_clk_timer_s1_agent.rf_source} {sys_clk_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {sys_clk_timer_s1_agent_rsp_fifo.out} {sys_clk_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {sys_clk_timer_s1_agent.rdata_fifo_src} {sys_clk_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_015.src} {sys_clk_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_015.src/sys_clk_timer_s1_agent.cp} {qsys_mm.command};add_connection {output_pio_s1_agent.m0} {output_pio_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {output_pio_s1_agent.rf_source} {output_pio_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {output_pio_s1_agent_rsp_fifo.out} {output_pio_s1_agent.rf_sink} {avalon_streaming};add_connection {output_pio_s1_agent.rdata_fifo_src} {output_pio_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_016.src} {output_pio_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_016.src/output_pio_s1_agent.cp} {qsys_mm.command};add_connection {button_pio_s1_agent.m0} {button_pio_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {button_pio_s1_agent.rf_source} {button_pio_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {button_pio_s1_agent_rsp_fifo.out} {button_pio_s1_agent.rf_sink} {avalon_streaming};add_connection {button_pio_s1_agent.rdata_fifo_src} {button_pio_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_017.src} {button_pio_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_017.src/button_pio_s1_agent.cp} {qsys_mm.command};add_connection {debug_uart_s1_agent.m0} {debug_uart_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {debug_uart_s1_agent.rf_source} {debug_uart_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {debug_uart_s1_agent_rsp_fifo.out} {debug_uart_s1_agent.rf_sink} {avalon_streaming};add_connection {debug_uart_s1_agent.rdata_fifo_src} {debug_uart_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_018.src} {debug_uart_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_018.src/debug_uart_s1_agent.cp} {qsys_mm.command};add_connection {frame_timer_s1_agent.m0} {frame_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {frame_timer_s1_agent.rf_source} {frame_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {frame_timer_s1_agent_rsp_fifo.out} {frame_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {frame_timer_s1_agent.rdata_fifo_src} {frame_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_019.src} {frame_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_019.src/frame_timer_s1_agent.cp} {qsys_mm.command};add_connection {calibration_ram_s1_agent.m0} {calibration_ram_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {calibration_ram_s1_agent.rf_source} {calibration_ram_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {calibration_ram_s1_agent_rsp_fifo.out} {calibration_ram_s1_agent.rf_sink} {avalon_streaming};add_connection {calibration_ram_s1_agent.rdata_fifo_src} {calibration_ram_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cpu_data_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_agent.cp/router.sink} {qsys_mm.command};add_connection {cpu_instruction_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {msgdma_tx_mm_read_agent.cp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_mm_read_agent.cp/router_002.sink} {qsys_mm.command};add_connection {router_002.src} {cmd_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/cmd_demux_002.sink} {qsys_mm.command};add_connection {msgdma_rx_mm_write_agent.cp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_mm_write_agent.cp/router_003.sink} {qsys_mm.command};add_connection {router_003.src} {cmd_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/cmd_demux_003.sink} {qsys_mm.command};add_connection {msgdma_tx_descriptor_read_master_agent.cp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_descriptor_read_master_agent.cp/router_004.sink} {qsys_mm.command};add_connection {router_004.src} {cmd_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/cmd_demux_004.sink} {qsys_mm.command};add_connection {msgdma_rx_descriptor_read_master_agent.cp} {router_005.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_descriptor_read_master_agent.cp/router_005.sink} {qsys_mm.command};add_connection {router_005.src} {cmd_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_005.src/cmd_demux_005.sink} {qsys_mm.command};add_connection {msgdma_tx_descriptor_write_master_agent.cp} {router_006.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_descriptor_write_master_agent.cp/router_006.sink} {qsys_mm.command};add_connection {router_006.src} {cmd_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_006.src/cmd_demux_006.sink} {qsys_mm.command};add_connection {msgdma_rx_descriptor_write_master_agent.cp} {router_007.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_descriptor_write_master_agent.cp/router_007.sink} {qsys_mm.command};add_connection {router_007.src} {cmd_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_007.src/cmd_demux_007.sink} {qsys_mm.command};add_connection {ddr3_ram_avl_agent.rp} {router_008.sink} {avalon_streaming};preview_set_connection_tag {ddr3_ram_avl_agent.rp/router_008.sink} {qsys_mm.response};add_connection {router_008.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_008.src/rsp_demux.sink} {qsys_mm.response};add_connection {ext_flash_avl_csr_agent.rp} {router_009.sink} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_csr_agent.rp/router_009.sink} {qsys_mm.response};add_connection {router_009.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_009.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {ext_flash_avl_mem_agent.rp} {router_010.sink} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_mem_agent.rp/router_010.sink} {qsys_mm.response};add_connection {router_010.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_010.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {eth_tse_control_port_agent.rp} {router_011.sink} {avalon_streaming};preview_set_connection_tag {eth_tse_control_port_agent.rp/router_011.sink} {qsys_mm.response};add_connection {router_011.src} {rsp_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_011.src/rsp_demux_003.sink} {qsys_mm.response};add_connection {sysid_control_slave_agent.rp} {router_012.sink} {avalon_streaming};preview_set_connection_tag {sysid_control_slave_agent.rp/router_012.sink} {qsys_mm.response};add_connection {router_012.src} {rsp_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_012.src/rsp_demux_004.sink} {qsys_mm.response};add_connection {msgdma_tx_csr_agent.rp} {router_013.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_csr_agent.rp/router_013.sink} {qsys_mm.response};add_connection {router_013.src} {rsp_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_013.src/rsp_demux_005.sink} {qsys_mm.response};add_connection {msgdma_rx_csr_agent.rp} {router_014.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_csr_agent.rp/router_014.sink} {qsys_mm.response};add_connection {router_014.src} {rsp_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_014.src/rsp_demux_006.sink} {qsys_mm.response};add_connection {onchip_flash_csr_agent.rp} {router_015.sink} {avalon_streaming};preview_set_connection_tag {onchip_flash_csr_agent.rp/router_015.sink} {qsys_mm.response};add_connection {router_015.src} {rsp_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_015.src/rsp_demux_007.sink} {qsys_mm.response};add_connection {udp_generator_csr_agent.rp} {router_016.sink} {avalon_streaming};preview_set_connection_tag {udp_generator_csr_agent.rp/router_016.sink} {qsys_mm.response};add_connection {router_016.src} {rsp_demux_008.sink} {avalon_streaming};preview_set_connection_tag {router_016.src/rsp_demux_008.sink} {qsys_mm.response};add_connection {sensor_interface_csr_agent.rp} {router_017.sink} {avalon_streaming};preview_set_connection_tag {sensor_interface_csr_agent.rp/router_017.sink} {qsys_mm.response};add_connection {router_017.src} {rsp_demux_009.sink} {avalon_streaming};preview_set_connection_tag {router_017.src/rsp_demux_009.sink} {qsys_mm.response};add_connection {onchip_flash_data_agent.rp} {router_018.sink} {avalon_streaming};preview_set_connection_tag {onchip_flash_data_agent.rp/router_018.sink} {qsys_mm.response};add_connection {router_018.src} {rsp_demux_010.sink} {avalon_streaming};preview_set_connection_tag {router_018.src/rsp_demux_010.sink} {qsys_mm.response};add_connection {cpu_debug_mem_slave_agent.rp} {router_019.sink} {avalon_streaming};preview_set_connection_tag {cpu_debug_mem_slave_agent.rp/router_019.sink} {qsys_mm.response};add_connection {router_019.src} {rsp_demux_011.sink} {avalon_streaming};preview_set_connection_tag {router_019.src/rsp_demux_011.sink} {qsys_mm.response};add_connection {msgdma_tx_prefetcher_csr_agent.rp} {router_020.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_prefetcher_csr_agent.rp/router_020.sink} {qsys_mm.response};add_connection {router_020.src} {rsp_demux_012.sink} {avalon_streaming};preview_set_connection_tag {router_020.src/rsp_demux_012.sink} {qsys_mm.response};add_connection {msgdma_rx_prefetcher_csr_agent.rp} {router_021.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_prefetcher_csr_agent.rp/router_021.sink} {qsys_mm.response};add_connection {router_021.src} {rsp_demux_013.sink} {avalon_streaming};preview_set_connection_tag {router_021.src/rsp_demux_013.sink} {qsys_mm.response};add_connection {descriptor_memory_s1_agent.rp} {router_022.sink} {avalon_streaming};preview_set_connection_tag {descriptor_memory_s1_agent.rp/router_022.sink} {qsys_mm.response};add_connection {router_022.src} {rsp_demux_014.sink} {avalon_streaming};preview_set_connection_tag {router_022.src/rsp_demux_014.sink} {qsys_mm.response};add_connection {sys_clk_timer_s1_agent.rp} {router_023.sink} {avalon_streaming};preview_set_connection_tag {sys_clk_timer_s1_agent.rp/router_023.sink} {qsys_mm.response};add_connection {router_023.src} {rsp_demux_015.sink} {avalon_streaming};preview_set_connection_tag {router_023.src/rsp_demux_015.sink} {qsys_mm.response};add_connection {output_pio_s1_agent.rp} {router_024.sink} {avalon_streaming};preview_set_connection_tag {output_pio_s1_agent.rp/router_024.sink} {qsys_mm.response};add_connection {router_024.src} {rsp_demux_016.sink} {avalon_streaming};preview_set_connection_tag {router_024.src/rsp_demux_016.sink} {qsys_mm.response};add_connection {button_pio_s1_agent.rp} {router_025.sink} {avalon_streaming};preview_set_connection_tag {button_pio_s1_agent.rp/router_025.sink} {qsys_mm.response};add_connection {router_025.src} {rsp_demux_017.sink} {avalon_streaming};preview_set_connection_tag {router_025.src/rsp_demux_017.sink} {qsys_mm.response};add_connection {debug_uart_s1_agent.rp} {router_026.sink} {avalon_streaming};preview_set_connection_tag {debug_uart_s1_agent.rp/router_026.sink} {qsys_mm.response};add_connection {router_026.src} {rsp_demux_018.sink} {avalon_streaming};preview_set_connection_tag {router_026.src/rsp_demux_018.sink} {qsys_mm.response};add_connection {frame_timer_s1_agent.rp} {router_027.sink} {avalon_streaming};preview_set_connection_tag {frame_timer_s1_agent.rp/router_027.sink} {qsys_mm.response};add_connection {router_027.src} {rsp_demux_019.sink} {avalon_streaming};preview_set_connection_tag {router_027.src/rsp_demux_019.sink} {qsys_mm.response};add_connection {calibration_ram_s1_agent.rp} {router_028.sink} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_agent.rp/router_028.sink} {qsys_mm.response};add_connection {router.src} {cpu_data_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router.src/cpu_data_master_limiter.cmd_sink} {qsys_mm.command};add_connection {cpu_data_master_limiter.cmd_src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_limiter.cmd_src/cmd_demux.sink} {qsys_mm.command};add_connection {rsp_mux.src} {cpu_data_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/cpu_data_master_limiter.rsp_sink} {qsys_mm.response};add_connection {cpu_data_master_limiter.rsp_src} {cpu_data_master_agent.rp} {avalon_streaming};preview_set_connection_tag {cpu_data_master_limiter.rsp_src/cpu_data_master_agent.rp} {qsys_mm.response};add_connection {router_001.src} {cpu_instruction_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cpu_instruction_master_limiter.cmd_sink} {qsys_mm.command};add_connection {cpu_instruction_master_limiter.cmd_src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_limiter.cmd_src/cmd_demux_001.sink} {qsys_mm.command};add_connection {rsp_mux_001.src} {cpu_instruction_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/cpu_instruction_master_limiter.rsp_sink} {qsys_mm.response};add_connection {cpu_instruction_master_limiter.rsp_src} {cpu_instruction_master_agent.rp} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_limiter.rsp_src/cpu_instruction_master_agent.rp} {qsys_mm.response};add_connection {cmd_mux_002.src} {ext_flash_avl_mem_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/ext_flash_avl_mem_burst_adapter.sink0} {qsys_mm.command};add_connection {ext_flash_avl_mem_burst_adapter.source0} {ext_flash_avl_mem_agent.cp} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_mem_burst_adapter.source0/ext_flash_avl_mem_agent.cp} {qsys_mm.command};add_connection {calibration_ram_s1_burst_adapter.source0} {calibration_ram_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_burst_adapter.source0/calibration_ram_s1_agent.cp} {qsys_mm.command};add_connection {cmd_demux.src3} {cmd_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src3/cmd_mux_003.sink0} {qsys_mm.command};add_connection {cmd_demux.src4} {cmd_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src4/cmd_mux_004.sink0} {qsys_mm.command};add_connection {cmd_demux.src5} {cmd_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src5/cmd_mux_005.sink0} {qsys_mm.command};add_connection {cmd_demux.src6} {cmd_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src6/cmd_mux_006.sink0} {qsys_mm.command};add_connection {cmd_demux.src7} {cmd_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src7/cmd_mux_007.sink0} {qsys_mm.command};add_connection {cmd_demux.src8} {cmd_mux_008.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src8/cmd_mux_008.sink0} {qsys_mm.command};add_connection {cmd_demux.src9} {cmd_mux_009.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src9/cmd_mux_009.sink0} {qsys_mm.command};add_connection {cmd_demux.src10} {cmd_mux_010.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src10/cmd_mux_010.sink0} {qsys_mm.command};add_connection {cmd_demux.src11} {cmd_mux_011.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src11/cmd_mux_011.sink0} {qsys_mm.command};add_connection {cmd_demux.src12} {cmd_mux_012.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src12/cmd_mux_012.sink0} {qsys_mm.command};add_connection {cmd_demux.src13} {cmd_mux_013.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src13/cmd_mux_013.sink0} {qsys_mm.command};add_connection {cmd_demux.src14} {cmd_mux_014.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src14/cmd_mux_014.sink0} {qsys_mm.command};add_connection {cmd_demux.src15} {cmd_mux_015.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src15/cmd_mux_015.sink0} {qsys_mm.command};add_connection {cmd_demux.src16} {cmd_mux_016.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src16/cmd_mux_016.sink0} {qsys_mm.command};add_connection {cmd_demux.src17} {cmd_mux_017.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src17/cmd_mux_017.sink0} {qsys_mm.command};add_connection {cmd_demux.src18} {cmd_mux_018.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src18/cmd_mux_018.sink0} {qsys_mm.command};add_connection {cmd_demux.src19} {cmd_mux_019.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src19/cmd_mux_019.sink0} {qsys_mm.command};add_connection {cmd_demux.src20} {cmd_mux_020.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src20/cmd_mux_020.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src2} {cmd_mux_010.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src2/cmd_mux_010.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src3} {cmd_mux_011.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src3/cmd_mux_011.sink1} {qsys_mm.command};add_connection {cmd_demux_004.src0} {cmd_mux_014.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_004.src0/cmd_mux_014.sink1} {qsys_mm.command};add_connection {cmd_demux_005.src0} {cmd_mux_014.sink2} {avalon_streaming};preview_set_connection_tag {cmd_demux_005.src0/cmd_mux_014.sink2} {qsys_mm.command};add_connection {cmd_demux_006.src0} {cmd_mux_014.sink3} {avalon_streaming};preview_set_connection_tag {cmd_demux_006.src0/cmd_mux_014.sink3} {qsys_mm.command};add_connection {cmd_demux_007.src0} {cmd_mux_014.sink4} {avalon_streaming};preview_set_connection_tag {cmd_demux_007.src0/cmd_mux_014.sink4} {qsys_mm.command};add_connection {rsp_demux_003.src0} {rsp_mux.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src0/rsp_mux.sink3} {qsys_mm.response};add_connection {rsp_demux_004.src0} {rsp_mux.sink4} {avalon_streaming};preview_set_connection_tag {rsp_demux_004.src0/rsp_mux.sink4} {qsys_mm.response};add_connection {rsp_demux_005.src0} {rsp_mux.sink5} {avalon_streaming};preview_set_connection_tag {rsp_demux_005.src0/rsp_mux.sink5} {qsys_mm.response};add_connection {rsp_demux_006.src0} {rsp_mux.sink6} {avalon_streaming};preview_set_connection_tag {rsp_demux_006.src0/rsp_mux.sink6} {qsys_mm.response};add_connection {rsp_demux_007.src0} {rsp_mux.sink7} {avalon_streaming};preview_set_connection_tag {rsp_demux_007.src0/rsp_mux.sink7} {qsys_mm.response};add_connection {rsp_demux_008.src0} {rsp_mux.sink8} {avalon_streaming};preview_set_connection_tag {rsp_demux_008.src0/rsp_mux.sink8} {qsys_mm.response};add_connection {rsp_demux_009.src0} {rsp_mux.sink9} {avalon_streaming};preview_set_connection_tag {rsp_demux_009.src0/rsp_mux.sink9} {qsys_mm.response};add_connection {rsp_demux_010.src0} {rsp_mux.sink10} {avalon_streaming};preview_set_connection_tag {rsp_demux_010.src0/rsp_mux.sink10} {qsys_mm.response};add_connection {rsp_demux_010.src1} {rsp_mux_001.sink2} {avalon_streaming};preview_set_connection_tag {rsp_demux_010.src1/rsp_mux_001.sink2} {qsys_mm.response};add_connection {rsp_demux_011.src0} {rsp_mux.sink11} {avalon_streaming};preview_set_connection_tag {rsp_demux_011.src0/rsp_mux.sink11} {qsys_mm.response};add_connection {rsp_demux_011.src1} {rsp_mux_001.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_011.src1/rsp_mux_001.sink3} {qsys_mm.response};add_connection {rsp_demux_012.src0} {rsp_mux.sink12} {avalon_streaming};preview_set_connection_tag {rsp_demux_012.src0/rsp_mux.sink12} {qsys_mm.response};add_connection {rsp_demux_013.src0} {rsp_mux.sink13} {avalon_streaming};preview_set_connection_tag {rsp_demux_013.src0/rsp_mux.sink13} {qsys_mm.response};add_connection {rsp_demux_014.src0} {rsp_mux.sink14} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src0/rsp_mux.sink14} {qsys_mm.response};add_connection {rsp_demux_014.src1} {rsp_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src1/rsp_mux_004.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src2} {rsp_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src2/rsp_mux_005.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src3} {rsp_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src3/rsp_mux_006.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src4} {rsp_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src4/rsp_mux_007.sink0} {qsys_mm.response};add_connection {rsp_demux_015.src0} {rsp_mux.sink15} {avalon_streaming};preview_set_connection_tag {rsp_demux_015.src0/rsp_mux.sink15} {qsys_mm.response};add_connection {rsp_demux_016.src0} {rsp_mux.sink16} {avalon_streaming};preview_set_connection_tag {rsp_demux_016.src0/rsp_mux.sink16} {qsys_mm.response};add_connection {rsp_demux_017.src0} {rsp_mux.sink17} {avalon_streaming};preview_set_connection_tag {rsp_demux_017.src0/rsp_mux.sink17} {qsys_mm.response};add_connection {rsp_demux_018.src0} {rsp_mux.sink18} {avalon_streaming};preview_set_connection_tag {rsp_demux_018.src0/rsp_mux.sink18} {qsys_mm.response};add_connection {rsp_demux_019.src0} {rsp_mux.sink19} {avalon_streaming};preview_set_connection_tag {rsp_demux_019.src0/rsp_mux.sink19} {qsys_mm.response};add_connection {rsp_demux_020.src0} {rsp_mux.sink20} {avalon_streaming};preview_set_connection_tag {rsp_demux_020.src0/rsp_mux.sink20} {qsys_mm.response};add_connection {router_028.src} {calibration_ram_s1_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {router_028.src/calibration_ram_s1_rsp_width_adapter.sink} {qsys_mm.response};add_connection {calibration_ram_s1_rsp_width_adapter.src} {rsp_demux_020.sink} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_rsp_width_adapter.src/rsp_demux_020.sink} {qsys_mm.response};add_connection {cmd_mux_020.src} {calibration_ram_s1_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_mux_020.src/calibration_ram_s1_cmd_width_adapter.sink} {qsys_mm.command};add_connection {calibration_ram_s1_cmd_width_adapter.src} {calibration_ram_s1_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_cmd_width_adapter.src/calibration_ram_s1_burst_adapter.sink0} {qsys_mm.command};add_connection {cmd_demux.src0} {crosser.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/crosser.in} {qsys_mm.command};add_connection {crosser.out} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {crosser.out/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {crosser_001.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/crosser_001.in} {qsys_mm.command};add_connection {crosser_001.out} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {crosser_001.out/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux.src2} {crosser_002.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src2/crosser_002.in} {qsys_mm.command};add_connection {crosser_002.out} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {crosser_002.out/cmd_mux_002.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {crosser_003.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/crosser_003.in} {qsys_mm.command};add_connection {crosser_003.out} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {crosser_003.out/cmd_mux.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {crosser_004.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/crosser_004.in} {qsys_mm.command};add_connection {crosser_004.out} {cmd_mux_002.sink1} {avalon_streaming};preview_set_connection_tag {crosser_004.out/cmd_mux_002.sink1} {qsys_mm.command};add_connection {cmd_demux_002.src0} {crosser_005.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_002.src0/crosser_005.in} {qsys_mm.command};add_connection {crosser_005.out} {cmd_mux.sink2} {avalon_streaming};preview_set_connection_tag {crosser_005.out/cmd_mux.sink2} {qsys_mm.command};add_connection {cmd_demux_003.src0} {crosser_006.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_003.src0/crosser_006.in} {qsys_mm.command};add_connection {crosser_006.out} {cmd_mux.sink3} {avalon_streaming};preview_set_connection_tag {crosser_006.out/cmd_mux.sink3} {qsys_mm.command};add_connection {rsp_demux.src0} {crosser_007.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/crosser_007.in} {qsys_mm.response};add_connection {crosser_007.out} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {crosser_007.out/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {crosser_008.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/crosser_008.in} {qsys_mm.response};add_connection {crosser_008.out} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {crosser_008.out/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux.src2} {crosser_009.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src2/crosser_009.in} {qsys_mm.response};add_connection {crosser_009.out} {rsp_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {crosser_009.out/rsp_mux_002.sink0} {qsys_mm.response};add_connection {rsp_demux.src3} {crosser_010.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src3/crosser_010.in} {qsys_mm.response};add_connection {crosser_010.out} {rsp_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {crosser_010.out/rsp_mux_003.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {crosser_011.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/crosser_011.in} {qsys_mm.response};add_connection {crosser_011.out} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {crosser_011.out/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {crosser_012.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/crosser_012.in} {qsys_mm.response};add_connection {crosser_012.out} {rsp_mux.sink2} {avalon_streaming};preview_set_connection_tag {crosser_012.out/rsp_mux.sink2} {qsys_mm.response};add_connection {rsp_demux_002.src1} {crosser_013.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src1/crosser_013.in} {qsys_mm.response};add_connection {crosser_013.out} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {crosser_013.out/rsp_mux_001.sink1} {qsys_mm.response};add_connection {cpu_data_master_limiter.cmd_valid} {cmd_demux.sink_valid} {avalon_streaming};add_connection {cpu_instruction_master_limiter.cmd_valid} {cmd_demux_001.sink_valid} {avalon_streaming};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_mm_read_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_mm_write_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_read_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_read_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_write_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_write_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_mm_read_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_mm_write_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_read_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_read_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_write_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_write_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_014.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_015.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_016.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_021.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_025.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_026.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_027.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_028.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_limiter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_limiter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_burst_adapter.cr0_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_010.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_011.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_012.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_010.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_011.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_012.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_rsp_width_adapter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_cmd_width_adapter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_001.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_002.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_003.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_004.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_005.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_006.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_007.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_008.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_009.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_010.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_011.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_012.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_013.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_translator.reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_translator.reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent_rdata_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent_rsp_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent_rdata_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {router_009.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {router_010.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_burst_adapter.cr0_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_001.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_002.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_004.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_011.in_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_012.in_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_013.in_clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_011.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_012.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_022.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_023.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_024.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_003.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_004.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_014.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_015.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_016.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_003.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_004.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_014.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_015.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_016.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_translator.reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent_rsp_fifo.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent_rdata_fifo.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {router_008.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_003.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_005.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_006.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_007.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_008.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_009.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_010.in_clk_reset} {reset};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_mm_read_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_mm_write_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_read_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_read_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_write_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_write_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_mm_read_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_mm_write_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_read_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_read_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_write_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_write_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_021.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_022.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_023.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_024.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_025.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_026.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_027.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_028.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_limiter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_limiter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_burst_adapter.cr0} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_008.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_008.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_009.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_009.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_010.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_010.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_rsp_width_adapter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_cmd_width_adapter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_001.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_002.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_003.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_004.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_005.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_006.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_007.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_008.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_009.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_010.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_011.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_012.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_013.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_reset_reset_bridge.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_reset_connection_reset_bridge.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_translator.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent_rsp_fifo.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent_rdata_fifo.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {router_008.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_003.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_005.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_006.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_007.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_008.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_009.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_010.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_soft_reset_reset_bridge.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_translator_reset_reset_bridge.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_translator.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_translator.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent_rsp_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent_rdata_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent_rsp_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent_rdata_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {router_009.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {router_010.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_burst_adapter.cr0} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_001.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_002.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_004.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_011.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_012.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_013.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_reset_reset_bridge.clk} {clock};add_interface {ddr3_ram_afi_clk} {clock} {slave};set_interface_property {ddr3_ram_afi_clk} {EXPORT_OF} {ddr3_ram_afi_clk_clock_bridge.in_clk};add_interface {ext_flash_clock_bridge_out_clk} {clock} {slave};set_interface_property {ext_flash_clock_bridge_out_clk} {EXPORT_OF} {ext_flash_clock_bridge_out_clk_clock_bridge.in_clk};add_interface {sys_clk_clk} {clock} {slave};set_interface_property {sys_clk_clk} {EXPORT_OF} {sys_clk_clk_clock_bridge.in_clk};add_interface {cpu_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {cpu_reset_reset_bridge_in_reset} {EXPORT_OF} {cpu_reset_reset_bridge.in_reset};add_interface {ddr3_ram_avl_translator_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ddr3_ram_avl_translator_reset_reset_bridge_in_reset} {EXPORT_OF} {ddr3_ram_avl_translator_reset_reset_bridge.in_reset};add_interface {ddr3_ram_soft_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ddr3_ram_soft_reset_reset_bridge_in_reset} {EXPORT_OF} {ddr3_ram_soft_reset_reset_bridge.in_reset};add_interface {eth_tse_reset_connection_reset_bridge_in_reset} {reset} {slave};set_interface_property {eth_tse_reset_connection_reset_bridge_in_reset} {EXPORT_OF} {eth_tse_reset_connection_reset_bridge.in_reset};add_interface {ext_flash_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ext_flash_reset_reset_bridge_in_reset} {EXPORT_OF} {ext_flash_reset_reset_bridge.in_reset};add_interface {cpu_data_master} {avalon} {slave};set_interface_property {cpu_data_master} {EXPORT_OF} {cpu_data_master_translator.avalon_anti_master_0};add_interface {cpu_instruction_master} {avalon} {slave};set_interface_property {cpu_instruction_master} {EXPORT_OF} {cpu_instruction_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_descriptor_read_master} {avalon} {slave};set_interface_property {msgdma_rx_descriptor_read_master} {EXPORT_OF} {msgdma_rx_descriptor_read_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_descriptor_write_master} {avalon} {slave};set_interface_property {msgdma_rx_descriptor_write_master} {EXPORT_OF} {msgdma_rx_descriptor_write_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_mm_write} {avalon} {slave};set_interface_property {msgdma_rx_mm_write} {EXPORT_OF} {msgdma_rx_mm_write_translator.avalon_anti_master_0};add_interface {msgdma_tx_descriptor_read_master} {avalon} {slave};set_interface_property {msgdma_tx_descriptor_read_master} {EXPORT_OF} {msgdma_tx_descriptor_read_master_translator.avalon_anti_master_0};add_interface {msgdma_tx_descriptor_write_master} {avalon} {slave};set_interface_property {msgdma_tx_descriptor_write_master} {EXPORT_OF} {msgdma_tx_descriptor_write_master_translator.avalon_anti_master_0};add_interface {msgdma_tx_mm_read} {avalon} {slave};set_interface_property {msgdma_tx_mm_read} {EXPORT_OF} {msgdma_tx_mm_read_translator.avalon_anti_master_0};add_interface {button_pio_s1} {avalon} {master};set_interface_property {button_pio_s1} {EXPORT_OF} {button_pio_s1_translator.avalon_anti_slave_0};add_interface {calibration_ram_s1} {avalon} {master};set_interface_property {calibration_ram_s1} {EXPORT_OF} {calibration_ram_s1_translator.avalon_anti_slave_0};add_interface {cpu_debug_mem_slave} {avalon} {master};set_interface_property {cpu_debug_mem_slave} {EXPORT_OF} {cpu_debug_mem_slave_translator.avalon_anti_slave_0};add_interface {ddr3_ram_avl} {avalon} {master};set_interface_property {ddr3_ram_avl} {EXPORT_OF} {ddr3_ram_avl_translator.avalon_anti_slave_0};add_interface {debug_uart_s1} {avalon} {master};set_interface_property {debug_uart_s1} {EXPORT_OF} {debug_uart_s1_translator.avalon_anti_slave_0};add_interface {descriptor_memory_s1} {avalon} {master};set_interface_property {descriptor_memory_s1} {EXPORT_OF} {descriptor_memory_s1_translator.avalon_anti_slave_0};add_interface {eth_tse_control_port} {avalon} {master};set_interface_property {eth_tse_control_port} {EXPORT_OF} {eth_tse_control_port_translator.avalon_anti_slave_0};add_interface {ext_flash_avl_csr} {avalon} {master};set_interface_property {ext_flash_avl_csr} {EXPORT_OF} {ext_flash_avl_csr_translator.avalon_anti_slave_0};add_interface {ext_flash_avl_mem} {avalon} {master};set_interface_property {ext_flash_avl_mem} {EXPORT_OF} {ext_flash_avl_mem_translator.avalon_anti_slave_0};add_interface {frame_timer_s1} {avalon} {master};set_interface_property {frame_timer_s1} {EXPORT_OF} {frame_timer_s1_translator.avalon_anti_slave_0};add_interface {msgdma_rx_csr} {avalon} {master};set_interface_property {msgdma_rx_csr} {EXPORT_OF} {msgdma_rx_csr_translator.avalon_anti_slave_0};add_interface {msgdma_rx_prefetcher_csr} {avalon} {master};set_interface_property {msgdma_rx_prefetcher_csr} {EXPORT_OF} {msgdma_rx_prefetcher_csr_translator.avalon_anti_slave_0};add_interface {msgdma_tx_csr} {avalon} {master};set_interface_property {msgdma_tx_csr} {EXPORT_OF} {msgdma_tx_csr_translator.avalon_anti_slave_0};add_interface {msgdma_tx_prefetcher_csr} {avalon} {master};set_interface_property {msgdma_tx_prefetcher_csr} {EXPORT_OF} {msgdma_tx_prefetcher_csr_translator.avalon_anti_slave_0};add_interface {onchip_flash_csr} {avalon} {master};set_interface_property {onchip_flash_csr} {EXPORT_OF} {onchip_flash_csr_translator.avalon_anti_slave_0};add_interface {onchip_flash_data} {avalon} {master};set_interface_property {onchip_flash_data} {EXPORT_OF} {onchip_flash_data_translator.avalon_anti_slave_0};add_interface {output_pio_s1} {avalon} {master};set_interface_property {output_pio_s1} {EXPORT_OF} {output_pio_s1_translator.avalon_anti_slave_0};add_interface {sensor_interface_csr} {avalon} {master};set_interface_property {sensor_interface_csr} {EXPORT_OF} {sensor_interface_csr_translator.avalon_anti_slave_0};add_interface {sys_clk_timer_s1} {avalon} {master};set_interface_property {sys_clk_timer_s1} {EXPORT_OF} {sys_clk_timer_s1_translator.avalon_anti_slave_0};add_interface {sysid_control_slave} {avalon} {master};set_interface_property {sysid_control_slave} {EXPORT_OF} {sysid_control_slave_translator.avalon_anti_slave_0};add_interface {udp_generator_csr} {avalon} {master};set_interface_property {udp_generator_csr} {EXPORT_OF} {udp_generator_csr_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.button_pio.s1} {0};set_module_assignment {interconnect_id.calibration_ram.s1} {1};set_module_assignment {interconnect_id.cpu.data_master} {0};set_module_assignment {interconnect_id.cpu.debug_mem_slave} {2};set_module_assignment {interconnect_id.cpu.instruction_master} {1};set_module_assignment {interconnect_id.ddr3_ram.avl} {3};set_module_assignment {interconnect_id.debug_uart.s1} {4};set_module_assignment {interconnect_id.descriptor_memory.s1} {5};set_module_assignment {interconnect_id.eth_tse.control_port} {6};set_module_assignment {interconnect_id.ext_flash.avl_csr} {7};set_module_assignment {interconnect_id.ext_flash.avl_mem} {8};set_module_assignment {interconnect_id.frame_timer.s1} {9};set_module_assignment {interconnect_id.msgdma_rx.csr} {10};set_module_assignment {interconnect_id.msgdma_rx.descriptor_read_master} {2};set_module_assignment {interconnect_id.msgdma_rx.descriptor_write_master} {3};set_module_assignment {interconnect_id.msgdma_rx.mm_write} {4};set_module_assignment {interconnect_id.msgdma_rx.prefetcher_csr} {11};set_module_assignment {interconnect_id.msgdma_tx.csr} {12};set_module_assignment {interconnect_id.msgdma_tx.descriptor_read_master} {5};set_module_assignment {interconnect_id.msgdma_tx.descriptor_write_master} {6};set_module_assignment {interconnect_id.msgdma_tx.mm_read} {7};set_module_assignment {interconnect_id.msgdma_tx.prefetcher_csr} {13};set_module_assignment {interconnect_id.onchip_flash.csr} {14};set_module_assignment {interconnect_id.onchip_flash.data} {15};set_module_assignment {interconnect_id.output_pio.s1} {16};set_module_assignment {interconnect_id.sensor_interface.csr} {17};set_module_assignment {interconnect_id.sys_clk_timer.s1} {18};set_module_assignment {interconnect_id.sysid.control_slave} {19};set_module_assignment {interconnect_id.udp_generator.csr} {20};(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=1,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=1,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=1,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=28,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=28,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=0,USE_READDATA=0,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=0,USE_READDATA=0,USE_READDATAVALID=0,USE_READRESPONSE=1,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=1)(altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=1,AV_ADDRESS_W=29,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=4,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=0,USE_READDATA=0,USE_READDATAVALID=0,USE_READRESPONSE=1,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEDATA=1,USE_WRITERESPONSE=1)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=25,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=3,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=32,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=150000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=5,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=1,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=1,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=24,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=7,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=1,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=1,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=9,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=1,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=8,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=1,AV_WRITE_WAIT_CYCLES=1,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=1,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=0,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=1,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=2,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=19,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=4,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=6,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=1,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=1,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=1,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=0,USE_DEBUGACCESS=1,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=1,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=11,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=1,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=1,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=2,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=1,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=0,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=1,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=1,AV_WRITE_WAIT_CYCLES=1,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=1,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=3,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=1,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=2,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=2,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=29,UAV_BURSTCOUNT_W=2,UAV_BYTEENABLE_W=2,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=16,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="7"
|
|
name="ext_flash_avl_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d20"
|
|
end="0x00000000018403d40"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="8"
|
|
name="ext_flash_avl_mem_translator.avalon_universal_slave_0"
|
|
start="0x0000000014000000"
|
|
end="0x00000000018000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="6"
|
|
name="eth_tse_control_port_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403000"
|
|
end="0x00000000018403400"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="19"
|
|
name="sysid_control_slave_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d68"
|
|
end="0x00000000018403d70"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="12"
|
|
name="msgdma_tx_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d00"
|
|
end="0x00000000018403d20"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="10"
|
|
name="msgdma_rx_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403ce0"
|
|
end="0x00000000018403d00"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="14"
|
|
name="onchip_flash_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d60"
|
|
end="0x00000000018403d68"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="20"
|
|
name="udp_generator_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403cc0"
|
|
end="0x00000000018403ce0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="17"
|
|
name="sensor_interface_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d50"
|
|
end="0x00000000018403d60"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="15"
|
|
name="onchip_flash_data_translator.avalon_universal_slave_0"
|
|
start="0x0000000018200000"
|
|
end="0x00000000018400000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="2"
|
|
name="cpu_debug_mem_slave_translator.avalon_universal_slave_0"
|
|
start="0x0000000018402800"
|
|
end="0x00000000018403000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="13"
|
|
name="msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403ca0"
|
|
end="0x00000000018403cc0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="11"
|
|
name="msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c80"
|
|
end="0x00000000018403ca0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="18"
|
|
name="sys_clk_timer_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c60"
|
|
end="0x00000000018403c80"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="16"
|
|
name="output_pio_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c40"
|
|
end="0x00000000018403c60"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="0"
|
|
name="button_pio_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d40"
|
|
end="0x00000000018403d50"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="4"
|
|
name="debug_uart_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c20"
|
|
end="0x00000000018403c40"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="9"
|
|
name="frame_timer_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c00"
|
|
end="0x00000000018403c20"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="1"
|
|
name="calibration_ram_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403400"
|
|
end="0x00000000018403800"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
,AV_BURSTBOUNDARIES=1,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="8"
|
|
name="ext_flash_avl_mem_translator.avalon_universal_slave_0"
|
|
start="0x0000000014000000"
|
|
end="0x00000000018000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="15"
|
|
name="onchip_flash_data_translator.avalon_universal_slave_0"
|
|
start="0x0000000018200000"
|
|
end="0x00000000018400000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="2"
|
|
name="cpu_debug_mem_slave_translator.avalon_universal_slave_0"
|
|
start="0x0000000018402800"
|
|
end="0x00000000018403000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=1,BURSTWRAP_VALUE=3,CACHE_VALUE=0,ID=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=7,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=5,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=2,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_merlin_master_agent:19.1:ADDR_MAP=<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=6,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=1,USE_WRITERESPONSE=1)(altera_merlin_master_agent:19.1:ADDR_MAP=<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=3,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=1,USE_WRITERESPONSE=1)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=5,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=3,MAX_BURSTWRAP=511,MAX_BYTE_CNT=16,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=33,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=34,CHANNEL_WIDTH=0,EMPTY_LATENCY=3,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=64,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=1,USE_PACKETS=0,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=7,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=34,CHANNEL_WIDTH=0,EMPTY_LATENCY=0,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=0,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=9,AV_LINEWRAPBURSTS=1,ECC_ENABLE=0,ID=8,MAX_BURSTWRAP=255,MAX_BYTE_CNT=256,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=34,CHANNEL_WIDTH=0,EMPTY_LATENCY=0,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=0,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=6,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=19,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=12,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=10,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=14,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=20,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=17,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=6,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=15,MAX_BURSTWRAP=511,MAX_BYTE_CNT=32,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=2,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=13,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=11,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=5,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=18,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=16,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=0,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=4,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=9,MAX_BURSTWRAP=511,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=2,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=1,MAX_BURSTWRAP=511,MAX_BYTE_CNT=2,MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),PKT_ADDR_H=46,PKT_ADDR_L=18,PKT_BEGIN_BURST=78,PKT_BURSTWRAP_H=70,PKT_BURSTWRAP_L=62,PKT_BURST_SIZE_H=73,PKT_BURST_SIZE_L=71,PKT_BYTEEN_H=17,PKT_BYTEEN_L=16,PKT_BYTE_CNT_H=61,PKT_BYTE_CNT_L=53,PKT_DATA_H=15,PKT_DATA_L=0,PKT_DEST_ID_H=89,PKT_DEST_ID_L=85,PKT_ORI_BURST_SIZE_H=102,PKT_ORI_BURST_SIZE_L=100,PKT_PROTECTION_H=93,PKT_PROTECTION_L=91,PKT_RESPONSE_STATUS_H=99,PKT_RESPONSE_STATUS_L=98,PKT_SRC_ID_H=84,PKT_SRC_ID_L=80,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=47,PKT_TRANS_LOCK=51,PKT_TRANS_POSTED=48,PKT_TRANS_READ=50,PKT_TRANS_WRITE=49,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=103,SUPPRESS_0_BYTEEN_CMD=1,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=104,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_merlin_router:19.1:CHANNEL_ID=000000000000000000001,000000000000000000100,000000000010000000000,000000100000000000000,000000000100000000000,000000000000000001000,100000000000000000000,010000000000000000000,001000000000000000000,000010000000000000000,000001000000000000000,000000010000000000000,000000001000000000000,000000000000100000000,000000000000001000000,000000000000000100000,000000000000000000010,000100000000000000000,000000000001000000000,000000000000010000000,000000000000000010000,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,8,15,5,2,6,1,9,4,16,18,11,13,20,10,12,7,0,17,14,19,END_ADDRESS=0x10000000,0x18000000,0x18400000,0x18402000,0x18403000,0x18403400,0x18403800,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68,0x18403d70,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,SLAVES_INFO=3:000000000000000000001:0x8000000:0x10000000:both:1:0:0:1,8:000000000000000000100:0x14000000:0x18000000:both:1:0:0:1,15:000000000010000000000:0x18200000:0x18400000:both:1:0:0:1,5:000000100000000000000:0x18400000:0x18402000:both:1:0:0:1,2:000000000100000000000:0x18402800:0x18403000:both:1:0:0:1,6:000000000000000001000:0x18403000:0x18403400:both:1:0:0:1,1:100000000000000000000:0x18403400:0x18403800:both:1:0:0:1,9:010000000000000000000:0x18403c00:0x18403c20:both:1:0:0:1,4:001000000000000000000:0x18403c20:0x18403c40:both:1:0:0:1,16:000010000000000000000:0x18403c40:0x18403c60:both:1:0:0:1,18:000001000000000000000:0x18403c60:0x18403c80:both:1:0:0:1,11:000000010000000000000:0x18403c80:0x18403ca0:both:1:0:0:1,13:000000001000000000000:0x18403ca0:0x18403cc0:both:1:0:0:1,20:000000000000100000000:0x18403cc0:0x18403ce0:both:1:0:0:1,10:000000000000001000000:0x18403ce0:0x18403d00:both:1:0:0:1,12:000000000000000100000:0x18403d00:0x18403d20:both:1:0:0:1,7:000000000000000000010:0x18403d20:0x18403d40:both:1:0:0:1,0:000100000000000000000:0x18403d40:0x18403d50:read:1:0:0:1,17:000000000001000000000:0x18403d50:0x18403d60:both:1:0:0:1,14:000000000000010000000:0x18403d60:0x18403d68:both:1:0:0:1,19:000000000000000010000:0x18403d68:0x18403d70:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,0x14000000,0x18200000,0x18400000,0x18402800,0x18403000,0x18403400,0x18403c00,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,read,both,both,read)(altera_merlin_router:19.1:CHANNEL_ID=0001,0010,0100,1000,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,8,15,2,END_ADDRESS=0x10000000,0x18000000,0x18400000,0x18403000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,SLAVES_INFO=3:0001:0x8000000:0x10000000:both:1:0:0:1,8:0010:0x14000000:0x18000000:both:1:0:0:1,15:0100:0x18200000:0x18400000:both:1:0:0:1,2:1000:0x18402800:0x18403000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,0x14000000,0x18200000,0x18402800,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,both,both,both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,END_ADDRESS=0x10000000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=3:1:0x8000000:0x10000000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,END_ADDRESS=0x10000000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=3:1:0x8000000:0x10000000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=5,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=5,END_ADDRESS=0x18402000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=5:1:0x18400000:0x18402000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x18400000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=5,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=5,END_ADDRESS=0x18402000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=5:1:0x18400000:0x18402000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x18400000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=5,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=5,END_ADDRESS=0x18402000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=5:1:0x18400000:0x18402000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x18400000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=5,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=5,END_ADDRESS=0x18402000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=5:1:0x18400000:0x18402000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x18400000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=0001,0010,0100,1000,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,7,4,END_ADDRESS=0x0,0x0,0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,SLAVES_INFO=0:0001:0x0:0x0:both:1:0:0:1,1:0010:0x0:0x0:read:1:0:0:1,7:0100:0x0:0x0:read:1:0:0:1,4:1000:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read,read,write)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read)(altera_merlin_router:19.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=00001,00010,00100,01000,10000,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,5,2,6,3,END_ADDRESS=0x0,0x0,0x0,0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,0,SLAVES_INFO=0:00001:0x0:0x0:both:1:0:0:1,5:00010:0x0:0x0:read:1:0:0:1,2:00100:0x0:0x0:read:1:0:0:1,6:01000:0x0:0x0:write:1:0:0:1,3:10000:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,0x0,0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read,read,write,write)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both)(altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),NON_SECURED_TAG=1,PKT_ADDR_H=46,PKT_ADDR_L=18,PKT_DEST_ID_H=89,PKT_DEST_ID_L=85,PKT_PROTECTION_H=93,PKT_PROTECTION_L=91,PKT_TRANS_READ=50,PKT_TRANS_WRITE=49,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=103,TYPE_OF_TRANSACTION=both)(altera_merlin_traffic_limiter:19.1:ENFORCE_ORDER=1,MAX_BURST_LENGTH=1,MAX_OUTSTANDING_RESPONSES=36,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PIPELINED=0,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_POSTED=66,PKT_TRANS_WRITE=67,PREVENT_HAZARDS=0,REORDER=0,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPORTS_NONPOSTED_WRITES=0,SUPPORTS_POSTED_WRITES=1,VALID_WIDTH=21)(altera_merlin_traffic_limiter:19.1:ENFORCE_ORDER=1,MAX_BURST_LENGTH=1,MAX_OUTSTANDING_RESPONSES=36,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PIPELINED=0,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_POSTED=66,PKT_TRANS_WRITE=67,PREVENT_HAZARDS=0,REORDER=0,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPORTS_NONPOSTED_WRITES=0,SUPPORTS_POSTED_WRITES=1,VALID_WIDTH=21)(altera_merlin_burst_adapter:19.1:ADAPTER_VERSION=13.1,BURSTWRAP_CONST_MASK=3,BURSTWRAP_CONST_VALUE=3,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=0,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=87,OUT_BYTE_CNT_H=79,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,ST_CHANNEL_W=21,ST_DATA_W=121)(altera_merlin_burst_adapter:19.1:ADAPTER_VERSION=13.1,BURSTWRAP_CONST_MASK=511,BURSTWRAP_CONST_VALUE=511,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=0,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=0,MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=70,OUT_BYTE_CNT_H=54,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=46,PKT_ADDR_L=18,PKT_BEGIN_BURST=78,PKT_BURSTWRAP_H=70,PKT_BURSTWRAP_L=62,PKT_BURST_SIZE_H=73,PKT_BURST_SIZE_L=71,PKT_BURST_TYPE_H=75,PKT_BURST_TYPE_L=74,PKT_BYTEEN_H=17,PKT_BYTEEN_L=16,PKT_BYTE_CNT_H=61,PKT_BYTE_CNT_L=53,PKT_TRANS_COMPRESSED_READ=47,PKT_TRANS_READ=50,PKT_TRANS_WRITE=49,ST_CHANNEL_W=21,ST_DATA_W=103)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=21,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=21)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=4,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=21)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=4,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=5,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=150000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=4,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=5,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=21,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=4,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0)(altera_merlin_width_adapter:19.1:COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),IN_PKT_ADDR_H=46,IN_PKT_ADDR_L=18,IN_PKT_BURSTWRAP_H=70,IN_PKT_BURSTWRAP_L=62,IN_PKT_BURST_SIZE_H=73,IN_PKT_BURST_SIZE_L=71,IN_PKT_BURST_TYPE_H=75,IN_PKT_BURST_TYPE_L=74,IN_PKT_BYTEEN_H=17,IN_PKT_BYTEEN_L=16,IN_PKT_BYTE_CNT_H=61,IN_PKT_BYTE_CNT_L=53,IN_PKT_DATA_H=15,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=102,IN_PKT_ORI_BURST_SIZE_L=100,IN_PKT_RESPONSE_STATUS_H=99,IN_PKT_RESPONSE_STATUS_L=98,IN_PKT_TRANS_COMPRESSED_READ=47,IN_PKT_TRANS_EXCLUSIVE=52,IN_PKT_TRANS_WRITE=49,IN_ST_DATA_W=103,OPTIMIZE_FOR_RSP=1,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),OUT_PKT_ADDR_H=64,OUT_PKT_ADDR_L=36,OUT_PKT_BURST_SIZE_H=91,OUT_PKT_BURST_SIZE_L=89,OUT_PKT_BURST_TYPE_H=93,OUT_PKT_BURST_TYPE_L=92,OUT_PKT_BYTEEN_H=35,OUT_PKT_BYTEEN_L=32,OUT_PKT_BYTE_CNT_H=79,OUT_PKT_BYTE_CNT_L=71,OUT_PKT_DATA_H=31,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=120,OUT_PKT_ORI_BURST_SIZE_L=118,OUT_PKT_RESPONSE_STATUS_H=117,OUT_PKT_RESPONSE_STATUS_L=116,OUT_PKT_TRANS_COMPRESSED_READ=65,OUT_PKT_TRANS_EXCLUSIVE=70,OUT_ST_DATA_W=121,PACKING=1,RESPONSE_PATH=1,ST_CHANNEL_W=21)(altera_merlin_width_adapter:19.1:COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),IN_PKT_ADDR_H=64,IN_PKT_ADDR_L=36,IN_PKT_BURSTWRAP_H=88,IN_PKT_BURSTWRAP_L=80,IN_PKT_BURST_SIZE_H=91,IN_PKT_BURST_SIZE_L=89,IN_PKT_BURST_TYPE_H=93,IN_PKT_BURST_TYPE_L=92,IN_PKT_BYTEEN_H=35,IN_PKT_BYTEEN_L=32,IN_PKT_BYTE_CNT_H=79,IN_PKT_BYTE_CNT_L=71,IN_PKT_DATA_H=31,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=120,IN_PKT_ORI_BURST_SIZE_L=118,IN_PKT_RESPONSE_STATUS_H=117,IN_PKT_RESPONSE_STATUS_L=116,IN_PKT_TRANS_COMPRESSED_READ=65,IN_PKT_TRANS_EXCLUSIVE=70,IN_PKT_TRANS_WRITE=67,IN_ST_DATA_W=121,OPTIMIZE_FOR_RSP=0,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),OUT_PKT_ADDR_H=46,OUT_PKT_ADDR_L=18,OUT_PKT_BURST_SIZE_H=73,OUT_PKT_BURST_SIZE_L=71,OUT_PKT_BURST_TYPE_H=75,OUT_PKT_BURST_TYPE_L=74,OUT_PKT_BYTEEN_H=17,OUT_PKT_BYTEEN_L=16,OUT_PKT_BYTE_CNT_H=61,OUT_PKT_BYTE_CNT_L=53,OUT_PKT_DATA_H=15,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=102,OUT_PKT_ORI_BURST_SIZE_L=100,OUT_PKT_RESPONSE_STATUS_H=99,OUT_PKT_RESPONSE_STATUS_L=98,OUT_PKT_TRANS_COMPRESSED_READ=47,OUT_PKT_TRANS_EXCLUSIVE=52,OUT_ST_DATA_W=103,PACKING=1,RESPONSE_PATH=0,ST_CHANNEL_W=21)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=150000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=0,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=0,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=150000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=0,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=150000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=150000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=150000000,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=150000000,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=150000000,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=150000000,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=0,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=0,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=0,AUTO_OUT_CLK_CLOCK_RATE=50000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=150000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=150000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=50000000,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=150000000,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon:19.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19.1:)(avalon_streaming:19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instancePathKey="q_sys:.:mm_interconnect_1"
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kind="altera_mm_interconnect"
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version="19.1"
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name="q_sys_mm_interconnect_1">
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<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
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<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
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<parameter
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name="COMPOSE_CONTENTS"
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value="add_instance {cpu_data_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_data_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_data_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_data_master_translator} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_data_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {cpu_data_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_data_master_translator} {SYNC_RESET} {0};add_instance {cpu_instruction_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {cpu_instruction_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READ} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_instruction_master_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_instruction_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {cpu_instruction_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_instruction_master_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_mm_read_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESS_W} {28};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_mm_read_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_mm_write_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESS_W} {28};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_mm_write_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_descriptor_read_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_descriptor_read_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_translator} {SYNC_RESET} {0};add_instance {msgdma_tx_descriptor_write_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {USE_WRITERESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_translator} {SYNC_RESET} {0};add_instance {msgdma_rx_descriptor_write_master_translator} {altera_merlin_master_translator};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_READLATENCY} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READDATA} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READ} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_CLKEN} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {USE_WRITERESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {64};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_translator} {SYNC_RESET} {0};add_instance {ddr3_ram_avl_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESS_W} {25};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_DATA_W} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_BURSTCOUNT_W} {5};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READDATA} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READ} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITE} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BEGINBURSTTRANSFER} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_LOCK} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {32};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ddr3_ram_avl_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {ext_flash_avl_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READ} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ext_flash_avl_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {ext_flash_avl_mem_translator} {altera_merlin_slave_translator};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESS_W} {24};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_DATA_W} {32};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTCOUNT_W} {7};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_BURSTCOUNT_W} {9};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_READLATENCY} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READDATA} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READ} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITE} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_ADDRESS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_LOCK} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_CONSTANT_BURST_BEHAVIOR} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {ext_flash_avl_mem_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {eth_tse_control_port_translator} {altera_merlin_slave_translator};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESS_W} {8};set_instance_parameter_value {eth_tse_control_port_translator} {AV_DATA_W} {32};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_DATA_W} {32};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {eth_tse_control_port_translator} {AV_READLATENCY} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READDATA} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READ} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITE} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_ADDRESS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_LOCK} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {eth_tse_control_port_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {eth_tse_control_port_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {eth_tse_control_port_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {eth_tse_control_port_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sysid_control_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESS_W} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_DATA_W} {32};set_instance_parameter_value {sysid_control_slave_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {sysid_control_slave_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sysid_control_slave_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sysid_control_slave_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sysid_control_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_READDATA} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READ} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sysid_control_slave_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sysid_control_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sysid_control_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sysid_control_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sysid_control_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sysid_control_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sysid_control_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sysid_control_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_tx_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_rx_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {onchip_flash_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESS_W} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {onchip_flash_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READ} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_flash_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_flash_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {udp_generator_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {udp_generator_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {udp_generator_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {udp_generator_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {udp_generator_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {udp_generator_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {udp_generator_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_READ} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {udp_generator_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {udp_generator_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {udp_generator_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {udp_generator_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {udp_generator_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {udp_generator_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {udp_generator_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {udp_generator_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sensor_interface_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESS_W} {2};set_instance_parameter_value {sensor_interface_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sensor_interface_csr_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READ} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sensor_interface_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sensor_interface_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sensor_interface_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {onchip_flash_data_translator} {altera_merlin_slave_translator};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESS_W} {19};set_instance_parameter_value {onchip_flash_data_translator} {AV_DATA_W} {32};set_instance_parameter_value {onchip_flash_data_translator} {UAV_DATA_W} {32};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTCOUNT_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {onchip_flash_data_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {onchip_flash_data_translator} {UAV_BURSTCOUNT_W} {6};set_instance_parameter_value {onchip_flash_data_translator} {AV_READLATENCY} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READDATA} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READ} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITE} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_ADDRESS} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_LOCK} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_data_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_data_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {onchip_flash_data_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {onchip_flash_data_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_data_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {onchip_flash_data_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {onchip_flash_data_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {cpu_debug_mem_slave_translator} {altera_merlin_slave_translator};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_DATA_W} {32};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_DATA_W} {32};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_READLATENCY} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READDATA} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READ} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITE} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_ADDRESS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_LOCK} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_REGISTERINCOMINGSIGNALS} {1};set_instance_parameter_value {cpu_debug_mem_slave_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {cpu_debug_mem_slave_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_tx_prefetcher_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {msgdma_rx_prefetcher_csr_translator} {altera_merlin_slave_translator};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_DATA_W} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_READLATENCY} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READDATA} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READ} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITE} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_ADDRESS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_LOCK} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {descriptor_memory_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESS_W} {11};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READ} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {descriptor_memory_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {sys_clk_timer_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READ} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {sys_clk_timer_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {output_pio_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {output_pio_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {output_pio_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {output_pio_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {output_pio_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {output_pio_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {output_pio_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_READ} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {output_pio_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {output_pio_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {output_pio_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {output_pio_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {output_pio_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {output_pio_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {output_pio_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {output_pio_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {button_pio_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESS_W} {2};set_instance_parameter_value {button_pio_s1_translator} {AV_DATA_W} {32};set_instance_parameter_value {button_pio_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {button_pio_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {button_pio_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {button_pio_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {button_pio_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITEDATA} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READ} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {button_pio_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {button_pio_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {button_pio_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {button_pio_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {button_pio_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {button_pio_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {button_pio_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {button_pio_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {debug_uart_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {debug_uart_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {debug_uart_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {debug_uart_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {debug_uart_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {debug_uart_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {debug_uart_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_WRITE_WAIT} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_READ} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_BEGINTRANSFER} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {debug_uart_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {debug_uart_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {debug_uart_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {debug_uart_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {debug_uart_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {debug_uart_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {debug_uart_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {debug_uart_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {frame_timer_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESS_W} {3};set_instance_parameter_value {frame_timer_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {frame_timer_s1_translator} {UAV_DATA_W} {32};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_BYTEENABLE_W} {1};set_instance_parameter_value {frame_timer_s1_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {frame_timer_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {frame_timer_s1_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {frame_timer_s1_translator} {AV_READLATENCY} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_READ} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {frame_timer_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {frame_timer_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {frame_timer_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {frame_timer_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {frame_timer_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {frame_timer_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {frame_timer_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {frame_timer_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {calibration_ram_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESS_W} {9};set_instance_parameter_value {calibration_ram_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_DATA_W} {16};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READ} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {calibration_ram_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {calibration_ram_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {calibration_ram_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {calibration_ram_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {cpu_data_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_data_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_data_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_data_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_data_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_data_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {cpu_data_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {cpu_data_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {cpu_data_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {cpu_data_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_data_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_data_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_data_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_data_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_data_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_data_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_data_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_data_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_data_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_data_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_data_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_data_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_data_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_data_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_data_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_data_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_data_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_data_master_agent} {AV_BURSTBOUNDARIES} {1};set_instance_parameter_value {cpu_data_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_data_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="7"
|
|
name="ext_flash_avl_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d20"
|
|
end="0x00000000018403d40"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="8"
|
|
name="ext_flash_avl_mem_translator.avalon_universal_slave_0"
|
|
start="0x0000000014000000"
|
|
end="0x00000000018000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="6"
|
|
name="eth_tse_control_port_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403000"
|
|
end="0x00000000018403400"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="19"
|
|
name="sysid_control_slave_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d68"
|
|
end="0x00000000018403d70"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="12"
|
|
name="msgdma_tx_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d00"
|
|
end="0x00000000018403d20"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="10"
|
|
name="msgdma_rx_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403ce0"
|
|
end="0x00000000018403d00"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="14"
|
|
name="onchip_flash_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d60"
|
|
end="0x00000000018403d68"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="20"
|
|
name="udp_generator_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403cc0"
|
|
end="0x00000000018403ce0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="17"
|
|
name="sensor_interface_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d50"
|
|
end="0x00000000018403d60"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="15"
|
|
name="onchip_flash_data_translator.avalon_universal_slave_0"
|
|
start="0x0000000018200000"
|
|
end="0x00000000018400000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="2"
|
|
name="cpu_debug_mem_slave_translator.avalon_universal_slave_0"
|
|
start="0x0000000018402800"
|
|
end="0x00000000018403000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="13"
|
|
name="msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403ca0"
|
|
end="0x00000000018403cc0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="11"
|
|
name="msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c80"
|
|
end="0x00000000018403ca0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="18"
|
|
name="sys_clk_timer_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c60"
|
|
end="0x00000000018403c80"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="16"
|
|
name="output_pio_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c40"
|
|
end="0x00000000018403c60"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="0"
|
|
name="button_pio_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d40"
|
|
end="0x00000000018403d50"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="4"
|
|
name="debug_uart_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c20"
|
|
end="0x00000000018403c40"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="9"
|
|
name="frame_timer_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c00"
|
|
end="0x00000000018403c20"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="1"
|
|
name="calibration_ram_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403400"
|
|
end="0x00000000018403800"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {cpu_data_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_data_master_agent} {ID} {0};set_instance_parameter_value {cpu_data_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {cpu_data_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_data_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_data_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_data_master_agent} {USE_WRITERESPONSE} {0};add_instance {cpu_instruction_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_instruction_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_instruction_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_instruction_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_instruction_master_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {cpu_instruction_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {cpu_instruction_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="8"
|
|
name="ext_flash_avl_mem_translator.avalon_universal_slave_0"
|
|
start="0x0000000014000000"
|
|
end="0x00000000018000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="15"
|
|
name="onchip_flash_data_translator.avalon_universal_slave_0"
|
|
start="0x0000000018200000"
|
|
end="0x00000000018400000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="2"
|
|
name="cpu_debug_mem_slave_translator.avalon_universal_slave_0"
|
|
start="0x0000000018402800"
|
|
end="0x00000000018403000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {cpu_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {cpu_instruction_master_agent} {ID} {1};set_instance_parameter_value {cpu_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {cpu_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {cpu_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_mm_read_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_mm_read_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_tx_mm_read_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {ID} {7};set_instance_parameter_value {msgdma_tx_mm_read_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_mm_read_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_mm_read_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_mm_read_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_rx_mm_write_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_mm_write_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_rx_mm_write_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {ID} {4};set_instance_parameter_value {msgdma_rx_mm_write_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_mm_write_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_mm_write_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_mm_write_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_descriptor_read_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {ID} {5};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_descriptor_read_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_rx_descriptor_read_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {ID} {2};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_descriptor_read_master_agent} {USE_WRITERESPONSE} {0};add_instance {msgdma_tx_descriptor_write_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {ID} {6};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_tx_descriptor_write_master_agent} {USE_WRITERESPONSE} {1};add_instance {msgdma_rx_descriptor_write_master_agent} {altera_merlin_master_agent};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_QOS_H} {97};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_QOS_L} {97};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_CACHE_H} {115};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_CACHE_L} {112};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ADDR_MAP} {<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {ID} {3};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {BURSTWRAP_VALUE} {511};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {USE_READRESPONSE} {1};set_instance_parameter_value {msgdma_rx_descriptor_write_master_agent} {USE_WRITERESPONSE} {1};add_instance {ddr3_ram_avl_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ddr3_ram_avl_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ddr3_ram_avl_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ddr3_ram_avl_agent} {ST_DATA_W} {121};set_instance_parameter_value {ddr3_ram_avl_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {AVS_BURSTCOUNT_W} {5};set_instance_parameter_value {ddr3_ram_avl_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ddr3_ram_avl_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ddr3_ram_avl_agent} {MAX_BYTE_CNT} {16};set_instance_parameter_value {ddr3_ram_avl_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {ddr3_ram_avl_agent} {ID} {3};set_instance_parameter_value {ddr3_ram_avl_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ddr3_ram_avl_agent} {ECC_ENABLE} {0};add_instance {ddr3_ram_avl_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {FIFO_DEPTH} {33};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ddr3_ram_avl_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ddr3_ram_avl_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {FIFO_DEPTH} {64};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {EMPTY_LATENCY} {3};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {1};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ddr3_ram_avl_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ext_flash_avl_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ext_flash_avl_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {ext_flash_avl_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ext_flash_avl_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {ext_flash_avl_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {ext_flash_avl_csr_agent} {ID} {7};set_instance_parameter_value {ext_flash_avl_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_csr_agent} {ECC_ENABLE} {0};add_instance {ext_flash_avl_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_csr_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_csr_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_mem_agent} {altera_merlin_slave_agent};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DATA_H} {31};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DATA_L} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {ext_flash_avl_mem_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {ext_flash_avl_mem_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_mem_agent} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_mem_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {AVS_BURSTCOUNT_W} {9};set_instance_parameter_value {ext_flash_avl_mem_agent} {AV_LINEWRAPBURSTS} {1};set_instance_parameter_value {ext_flash_avl_mem_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_mem_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {ext_flash_avl_mem_agent} {MAX_BYTE_CNT} {256};set_instance_parameter_value {ext_flash_avl_mem_agent} {MAX_BURSTWRAP} {255};set_instance_parameter_value {ext_flash_avl_mem_agent} {ID} {8};set_instance_parameter_value {ext_flash_avl_mem_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {ext_flash_avl_mem_agent} {ECC_ENABLE} {0};add_instance {ext_flash_avl_mem_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_mem_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {ext_flash_avl_mem_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {ext_flash_avl_mem_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {eth_tse_control_port_agent} {altera_merlin_slave_agent};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DATA_H} {31};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DATA_L} {0};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {eth_tse_control_port_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {eth_tse_control_port_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {eth_tse_control_port_agent} {ST_DATA_W} {121};set_instance_parameter_value {eth_tse_control_port_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {eth_tse_control_port_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {eth_tse_control_port_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {eth_tse_control_port_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {eth_tse_control_port_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {eth_tse_control_port_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {eth_tse_control_port_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {eth_tse_control_port_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {eth_tse_control_port_agent} {ID} {6};set_instance_parameter_value {eth_tse_control_port_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {eth_tse_control_port_agent} {ECC_ENABLE} {0};add_instance {eth_tse_control_port_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {eth_tse_control_port_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sysid_control_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sysid_control_slave_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sysid_control_slave_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sysid_control_slave_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sysid_control_slave_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sysid_control_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sysid_control_slave_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sysid_control_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sysid_control_slave_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sysid_control_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sysid_control_slave_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sysid_control_slave_agent} {ST_DATA_W} {121};set_instance_parameter_value {sysid_control_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sysid_control_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sysid_control_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sysid_control_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sysid_control_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sysid_control_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sysid_control_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sysid_control_slave_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sysid_control_slave_agent} {ID} {19};set_instance_parameter_value {sysid_control_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sysid_control_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sysid_control_slave_agent} {ECC_ENABLE} {0};add_instance {sysid_control_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sysid_control_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_tx_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_tx_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_tx_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_tx_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_tx_csr_agent} {ID} {12};set_instance_parameter_value {msgdma_tx_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_tx_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_tx_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_rx_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_rx_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_rx_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_rx_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_rx_csr_agent} {ID} {10};set_instance_parameter_value {msgdma_rx_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_rx_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_rx_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {onchip_flash_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {onchip_flash_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_flash_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {onchip_flash_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {onchip_flash_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {onchip_flash_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_flash_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_flash_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_flash_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {onchip_flash_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {onchip_flash_csr_agent} {ID} {14};set_instance_parameter_value {onchip_flash_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_csr_agent} {ECC_ENABLE} {0};add_instance {onchip_flash_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_flash_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {udp_generator_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {udp_generator_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {udp_generator_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {udp_generator_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {udp_generator_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {udp_generator_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {udp_generator_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {udp_generator_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {udp_generator_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {udp_generator_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {udp_generator_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {udp_generator_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {udp_generator_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {udp_generator_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {udp_generator_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {udp_generator_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {udp_generator_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {udp_generator_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {udp_generator_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {udp_generator_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {udp_generator_csr_agent} {ID} {20};set_instance_parameter_value {udp_generator_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {udp_generator_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {udp_generator_csr_agent} {ECC_ENABLE} {0};add_instance {udp_generator_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {udp_generator_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sensor_interface_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sensor_interface_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sensor_interface_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sensor_interface_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {sensor_interface_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sensor_interface_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sensor_interface_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sensor_interface_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sensor_interface_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sensor_interface_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sensor_interface_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sensor_interface_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sensor_interface_csr_agent} {ID} {17};set_instance_parameter_value {sensor_interface_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sensor_interface_csr_agent} {ECC_ENABLE} {0};add_instance {sensor_interface_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sensor_interface_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {onchip_flash_data_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {onchip_flash_data_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {onchip_flash_data_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {onchip_flash_data_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {onchip_flash_data_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {onchip_flash_data_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {onchip_flash_data_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DATA_H} {31};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_flash_data_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {onchip_flash_data_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {onchip_flash_data_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_flash_data_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {onchip_flash_data_agent} {ST_DATA_W} {121};set_instance_parameter_value {onchip_flash_data_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_flash_data_agent} {AVS_BURSTCOUNT_W} {6};set_instance_parameter_value {onchip_flash_data_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_flash_data_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_flash_data_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_flash_data_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_flash_data_agent} {MAX_BYTE_CNT} {32};set_instance_parameter_value {onchip_flash_data_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {onchip_flash_data_agent} {ID} {15};set_instance_parameter_value {onchip_flash_data_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_flash_data_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_flash_data_agent} {ECC_ENABLE} {0};add_instance {onchip_flash_data_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_flash_data_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {cpu_debug_mem_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ST_DATA_W} {121};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {cpu_debug_mem_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_debug_mem_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {cpu_debug_mem_slave_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ID} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent} {ECC_ENABLE} {0};add_instance {cpu_debug_mem_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {cpu_debug_mem_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_tx_prefetcher_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ID} {13};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_tx_prefetcher_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {msgdma_rx_prefetcher_csr_agent} {altera_merlin_slave_agent};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DATA_H} {31};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DATA_L} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ST_DATA_W} {121};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ID} {11};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent} {ECC_ENABLE} {0};add_instance {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {msgdma_rx_prefetcher_csr_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {descriptor_memory_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {descriptor_memory_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {descriptor_memory_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {descriptor_memory_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {descriptor_memory_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {descriptor_memory_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {descriptor_memory_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {descriptor_memory_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {descriptor_memory_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {descriptor_memory_s1_agent} {ID} {5};set_instance_parameter_value {descriptor_memory_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {descriptor_memory_s1_agent} {ECC_ENABLE} {0};add_instance {descriptor_memory_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {descriptor_memory_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sys_clk_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {sys_clk_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {sys_clk_timer_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sys_clk_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sys_clk_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sys_clk_timer_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {sys_clk_timer_s1_agent} {ID} {18};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sys_clk_timer_s1_agent} {ECC_ENABLE} {0};add_instance {sys_clk_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sys_clk_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {output_pio_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {output_pio_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {output_pio_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {output_pio_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {output_pio_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {output_pio_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {output_pio_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {output_pio_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {output_pio_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {output_pio_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {output_pio_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {output_pio_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {output_pio_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {output_pio_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {output_pio_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {output_pio_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {output_pio_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {output_pio_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {output_pio_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {output_pio_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {output_pio_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {output_pio_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {output_pio_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {output_pio_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {output_pio_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {output_pio_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {output_pio_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {output_pio_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {output_pio_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {output_pio_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {output_pio_s1_agent} {ID} {16};set_instance_parameter_value {output_pio_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {output_pio_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {output_pio_s1_agent} {ECC_ENABLE} {0};add_instance {output_pio_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {output_pio_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {button_pio_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {button_pio_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {button_pio_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {button_pio_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {button_pio_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {button_pio_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {button_pio_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {button_pio_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {button_pio_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {button_pio_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {button_pio_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {button_pio_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {button_pio_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {button_pio_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {button_pio_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {button_pio_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {button_pio_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {button_pio_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {button_pio_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {button_pio_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {button_pio_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {button_pio_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {button_pio_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {button_pio_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {button_pio_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {button_pio_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {button_pio_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {button_pio_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {button_pio_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {button_pio_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {button_pio_s1_agent} {ID} {0};set_instance_parameter_value {button_pio_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {button_pio_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {button_pio_s1_agent} {ECC_ENABLE} {0};add_instance {button_pio_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {button_pio_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {debug_uart_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {debug_uart_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {debug_uart_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {debug_uart_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {debug_uart_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {debug_uart_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {debug_uart_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {debug_uart_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {debug_uart_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {debug_uart_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {debug_uart_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {debug_uart_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {debug_uart_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {debug_uart_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {debug_uart_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {debug_uart_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {debug_uart_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {debug_uart_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {debug_uart_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {debug_uart_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {debug_uart_s1_agent} {ID} {4};set_instance_parameter_value {debug_uart_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {debug_uart_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {debug_uart_s1_agent} {ECC_ENABLE} {0};add_instance {debug_uart_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {debug_uart_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {frame_timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {frame_timer_s1_agent} {PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {frame_timer_s1_agent} {PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {frame_timer_s1_agent} {PKT_PROTECTION_H} {111};set_instance_parameter_value {frame_timer_s1_agent} {PKT_PROTECTION_L} {109};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {frame_timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {frame_timer_s1_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {frame_timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SRC_ID_H} {102};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SRC_ID_L} {98};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DEST_ID_H} {107};set_instance_parameter_value {frame_timer_s1_agent} {PKT_DEST_ID_L} {103};set_instance_parameter_value {frame_timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {frame_timer_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {frame_timer_s1_agent} {ST_DATA_W} {121};set_instance_parameter_value {frame_timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {frame_timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {frame_timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {frame_timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {frame_timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {frame_timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {frame_timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {frame_timer_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {frame_timer_s1_agent} {ID} {9};set_instance_parameter_value {frame_timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {frame_timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {frame_timer_s1_agent} {ECC_ENABLE} {0};add_instance {frame_timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {122};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {frame_timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {calibration_ram_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_LOCK} {51};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BEGIN_BURST} {78};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_PROTECTION_H} {93};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_PROTECTION_L} {91};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_POSTED} {48};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_TRANS_READ} {50};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SRC_ID_H} {84};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SRC_ID_L} {80};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DEST_ID_H} {89};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_DEST_ID_L} {85};set_instance_parameter_value {calibration_ram_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {calibration_ram_s1_agent} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_agent} {ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {calibration_ram_s1_agent} {AVS_BURSTCOUNT_W} {2};set_instance_parameter_value {calibration_ram_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {calibration_ram_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {calibration_ram_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {calibration_ram_s1_agent} {MAX_BYTE_CNT} {2};set_instance_parameter_value {calibration_ram_s1_agent} {MAX_BURSTWRAP} {511};set_instance_parameter_value {calibration_ram_s1_agent} {ID} {1};set_instance_parameter_value {calibration_ram_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {calibration_ram_s1_agent} {ECC_ENABLE} {0};add_instance {calibration_ram_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {104};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {calibration_ram_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {3 8 15 5 2 6 1 9 4 16 18 11 13 20 10 12 7 0 17 14 19 };set_instance_parameter_value {router} {CHANNEL_ID} {000000000000000000001 000000000000000000100 000000000010000000000 000000100000000000000 000000000100000000000 000000000000000001000 100000000000000000000 010000000000000000000 001000000000000000000 000010000000000000000 000001000000000000000 000000010000000000000 000000001000000000000 000000000000100000000 000000000000001000000 000000000000000100000 000000000000000000010 000100000000000000000 000000000001000000000 000000000000010000000 000000000000000010000 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both both both both both both both both both both both both both both both both both read both both read };set_instance_parameter_value {router} {START_ADDRESS} {0x8000000 0x14000000 0x18200000 0x18400000 0x18402800 0x18403000 0x18403400 0x18403c00 0x18403c20 0x18403c40 0x18403c60 0x18403c80 0x18403ca0 0x18403cc0 0x18403ce0 0x18403d00 0x18403d20 0x18403d40 0x18403d50 0x18403d60 0x18403d68 };set_instance_parameter_value {router} {END_ADDRESS} {0x10000000 0x18000000 0x18400000 0x18402000 0x18403000 0x18403400 0x18403800 0x18403c20 0x18403c40 0x18403c60 0x18403c80 0x18403ca0 0x18403cc0 0x18403ce0 0x18403d00 0x18403d20 0x18403d40 0x18403d50 0x18403d60 0x18403d68 0x18403d70 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {64};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router} {PKT_TRANS_READ} {68};set_instance_parameter_value {router} {ST_DATA_W} {121};set_instance_parameter_value {router} {ST_CHANNEL_W} {21};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {3};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {3 8 15 2 };set_instance_parameter_value {router_001} {CHANNEL_ID} {0001 0010 0100 1000 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both both both both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x8000000 0x14000000 0x18200000 0x18402800 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x10000000 0x18000000 0x18400000 0x18403000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {64};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_001} {ST_DATA_W} {121};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {3 };set_instance_parameter_value {router_002} {CHANNEL_ID} {1 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x8000000 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x10000000 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {64};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_002} {ST_DATA_W} {121};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_002} {DECODER_TYPE} {0};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {3 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_003} {START_ADDRESS} {0x8000000 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x10000000 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {64};set_instance_parameter_value {router_003} {PKT_ADDR_L} {36};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_003} {ST_DATA_W} {121};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_003} {DECODER_TYPE} {0};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {3};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {5 };set_instance_parameter_value {router_004} {CHANNEL_ID} {1 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_004} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {64};set_instance_parameter_value {router_004} {PKT_ADDR_L} {36};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_004} {ST_DATA_W} {121};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_004} {DECODER_TYPE} {0};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {router_005} {altera_merlin_router};set_instance_parameter_value {router_005} {DESTINATION_ID} {5 };set_instance_parameter_value {router_005} {CHANNEL_ID} {1 };set_instance_parameter_value {router_005} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_005} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_005} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_005} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_005} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_005} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_005} {SPAN_OFFSET} {};set_instance_parameter_value {router_005} {PKT_ADDR_H} {64};set_instance_parameter_value {router_005} {PKT_ADDR_L} {36};set_instance_parameter_value {router_005} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_005} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_005} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_005} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_005} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_005} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_005} {ST_DATA_W} {121};set_instance_parameter_value {router_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_005} {DECODER_TYPE} {0};set_instance_parameter_value {router_005} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_005} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_005} {MEMORY_ALIASING_DECODE} {0};add_instance {router_006} {altera_merlin_router};set_instance_parameter_value {router_006} {DESTINATION_ID} {5 };set_instance_parameter_value {router_006} {CHANNEL_ID} {1 };set_instance_parameter_value {router_006} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_006} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_006} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_006} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_006} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_006} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_006} {SPAN_OFFSET} {};set_instance_parameter_value {router_006} {PKT_ADDR_H} {64};set_instance_parameter_value {router_006} {PKT_ADDR_L} {36};set_instance_parameter_value {router_006} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_006} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_006} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_006} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_006} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_006} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_006} {ST_DATA_W} {121};set_instance_parameter_value {router_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_006} {DECODER_TYPE} {0};set_instance_parameter_value {router_006} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_006} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_006} {MEMORY_ALIASING_DECODE} {0};add_instance {router_007} {altera_merlin_router};set_instance_parameter_value {router_007} {DESTINATION_ID} {5 };set_instance_parameter_value {router_007} {CHANNEL_ID} {1 };set_instance_parameter_value {router_007} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_007} {START_ADDRESS} {0x18400000 };set_instance_parameter_value {router_007} {END_ADDRESS} {0x18402000 };set_instance_parameter_value {router_007} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_007} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_007} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_007} {SPAN_OFFSET} {};set_instance_parameter_value {router_007} {PKT_ADDR_H} {64};set_instance_parameter_value {router_007} {PKT_ADDR_L} {36};set_instance_parameter_value {router_007} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_007} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_007} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_007} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_007} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_007} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_007} {ST_DATA_W} {121};set_instance_parameter_value {router_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_007} {DECODER_TYPE} {0};set_instance_parameter_value {router_007} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_007} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_DESTID} {5};set_instance_parameter_value {router_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_007} {MEMORY_ALIASING_DECODE} {0};add_instance {router_008} {altera_merlin_router};set_instance_parameter_value {router_008} {DESTINATION_ID} {0 1 7 4 };set_instance_parameter_value {router_008} {CHANNEL_ID} {0001 0010 0100 1000 };set_instance_parameter_value {router_008} {TYPE_OF_TRANSACTION} {both read read write };set_instance_parameter_value {router_008} {START_ADDRESS} {0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_008} {END_ADDRESS} {0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_008} {NON_SECURED_TAG} {1 1 1 1 };set_instance_parameter_value {router_008} {SECURED_RANGE_PAIRS} {0 0 0 0 };set_instance_parameter_value {router_008} {SECURED_RANGE_LIST} {0 0 0 0 };set_instance_parameter_value {router_008} {SPAN_OFFSET} {};set_instance_parameter_value {router_008} {PKT_ADDR_H} {64};set_instance_parameter_value {router_008} {PKT_ADDR_L} {36};set_instance_parameter_value {router_008} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_008} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_008} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_008} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_008} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_008} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_008} {ST_DATA_W} {121};set_instance_parameter_value {router_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_008} {DECODER_TYPE} {1};set_instance_parameter_value {router_008} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_008} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_008} {MEMORY_ALIASING_DECODE} {0};add_instance {router_009} {altera_merlin_router};set_instance_parameter_value {router_009} {DESTINATION_ID} {0 };set_instance_parameter_value {router_009} {CHANNEL_ID} {1 };set_instance_parameter_value {router_009} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_009} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_009} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_009} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_009} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_009} {SPAN_OFFSET} {};set_instance_parameter_value {router_009} {PKT_ADDR_H} {64};set_instance_parameter_value {router_009} {PKT_ADDR_L} {36};set_instance_parameter_value {router_009} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_009} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_009} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_009} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_009} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_009} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_009} {ST_DATA_W} {121};set_instance_parameter_value {router_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_009} {DECODER_TYPE} {1};set_instance_parameter_value {router_009} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_009} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_009} {MEMORY_ALIASING_DECODE} {0};add_instance {router_010} {altera_merlin_router};set_instance_parameter_value {router_010} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_010} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_010} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_010} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_010} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_010} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_010} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_010} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_010} {SPAN_OFFSET} {};set_instance_parameter_value {router_010} {PKT_ADDR_H} {64};set_instance_parameter_value {router_010} {PKT_ADDR_L} {36};set_instance_parameter_value {router_010} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_010} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_010} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_010} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_010} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_010} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_010} {ST_DATA_W} {121};set_instance_parameter_value {router_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_010} {DECODER_TYPE} {1};set_instance_parameter_value {router_010} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_010} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_010} {MEMORY_ALIASING_DECODE} {0};add_instance {router_011} {altera_merlin_router};set_instance_parameter_value {router_011} {DESTINATION_ID} {0 };set_instance_parameter_value {router_011} {CHANNEL_ID} {1 };set_instance_parameter_value {router_011} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_011} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_011} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_011} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_011} {SPAN_OFFSET} {};set_instance_parameter_value {router_011} {PKT_ADDR_H} {64};set_instance_parameter_value {router_011} {PKT_ADDR_L} {36};set_instance_parameter_value {router_011} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_011} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_011} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_011} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_011} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_011} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_011} {ST_DATA_W} {121};set_instance_parameter_value {router_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_011} {DECODER_TYPE} {1};set_instance_parameter_value {router_011} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_011} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_011} {MEMORY_ALIASING_DECODE} {0};add_instance {router_012} {altera_merlin_router};set_instance_parameter_value {router_012} {DESTINATION_ID} {0 };set_instance_parameter_value {router_012} {CHANNEL_ID} {1 };set_instance_parameter_value {router_012} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_012} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_012} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_012} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_012} {SPAN_OFFSET} {};set_instance_parameter_value {router_012} {PKT_ADDR_H} {64};set_instance_parameter_value {router_012} {PKT_ADDR_L} {36};set_instance_parameter_value {router_012} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_012} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_012} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_012} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_012} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_012} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_012} {ST_DATA_W} {121};set_instance_parameter_value {router_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_012} {DECODER_TYPE} {1};set_instance_parameter_value {router_012} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_012} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_012} {MEMORY_ALIASING_DECODE} {0};add_instance {router_013} {altera_merlin_router};set_instance_parameter_value {router_013} {DESTINATION_ID} {0 };set_instance_parameter_value {router_013} {CHANNEL_ID} {1 };set_instance_parameter_value {router_013} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_013} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_013} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_013} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_013} {SPAN_OFFSET} {};set_instance_parameter_value {router_013} {PKT_ADDR_H} {64};set_instance_parameter_value {router_013} {PKT_ADDR_L} {36};set_instance_parameter_value {router_013} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_013} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_013} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_013} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_013} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_013} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_013} {ST_DATA_W} {121};set_instance_parameter_value {router_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_013} {DECODER_TYPE} {1};set_instance_parameter_value {router_013} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_013} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_013} {MEMORY_ALIASING_DECODE} {0};add_instance {router_014} {altera_merlin_router};set_instance_parameter_value {router_014} {DESTINATION_ID} {0 };set_instance_parameter_value {router_014} {CHANNEL_ID} {1 };set_instance_parameter_value {router_014} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_014} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_014} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_014} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_014} {SPAN_OFFSET} {};set_instance_parameter_value {router_014} {PKT_ADDR_H} {64};set_instance_parameter_value {router_014} {PKT_ADDR_L} {36};set_instance_parameter_value {router_014} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_014} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_014} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_014} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_014} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_014} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_014} {ST_DATA_W} {121};set_instance_parameter_value {router_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_014} {DECODER_TYPE} {1};set_instance_parameter_value {router_014} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_014} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_014} {MEMORY_ALIASING_DECODE} {0};add_instance {router_015} {altera_merlin_router};set_instance_parameter_value {router_015} {DESTINATION_ID} {0 };set_instance_parameter_value {router_015} {CHANNEL_ID} {1 };set_instance_parameter_value {router_015} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_015} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_015} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_015} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_015} {SPAN_OFFSET} {};set_instance_parameter_value {router_015} {PKT_ADDR_H} {64};set_instance_parameter_value {router_015} {PKT_ADDR_L} {36};set_instance_parameter_value {router_015} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_015} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_015} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_015} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_015} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_015} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_015} {ST_DATA_W} {121};set_instance_parameter_value {router_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_015} {DECODER_TYPE} {1};set_instance_parameter_value {router_015} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_015} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_015} {MEMORY_ALIASING_DECODE} {0};add_instance {router_016} {altera_merlin_router};set_instance_parameter_value {router_016} {DESTINATION_ID} {0 };set_instance_parameter_value {router_016} {CHANNEL_ID} {1 };set_instance_parameter_value {router_016} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_016} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_016} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_016} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_016} {SPAN_OFFSET} {};set_instance_parameter_value {router_016} {PKT_ADDR_H} {64};set_instance_parameter_value {router_016} {PKT_ADDR_L} {36};set_instance_parameter_value {router_016} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_016} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_016} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_016} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_016} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_016} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_016} {ST_DATA_W} {121};set_instance_parameter_value {router_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_016} {DECODER_TYPE} {1};set_instance_parameter_value {router_016} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_016} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_016} {MEMORY_ALIASING_DECODE} {0};add_instance {router_017} {altera_merlin_router};set_instance_parameter_value {router_017} {DESTINATION_ID} {0 };set_instance_parameter_value {router_017} {CHANNEL_ID} {1 };set_instance_parameter_value {router_017} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_017} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_017} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_017} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_017} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_017} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_017} {SPAN_OFFSET} {};set_instance_parameter_value {router_017} {PKT_ADDR_H} {64};set_instance_parameter_value {router_017} {PKT_ADDR_L} {36};set_instance_parameter_value {router_017} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_017} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_017} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_017} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_017} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_017} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_017} {ST_DATA_W} {121};set_instance_parameter_value {router_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_017} {DECODER_TYPE} {1};set_instance_parameter_value {router_017} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_017} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_017} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_017} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_017} {MEMORY_ALIASING_DECODE} {0};add_instance {router_018} {altera_merlin_router};set_instance_parameter_value {router_018} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_018} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_018} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_018} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_018} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_018} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_018} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_018} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_018} {SPAN_OFFSET} {};set_instance_parameter_value {router_018} {PKT_ADDR_H} {64};set_instance_parameter_value {router_018} {PKT_ADDR_L} {36};set_instance_parameter_value {router_018} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_018} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_018} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_018} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_018} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_018} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_018} {ST_DATA_W} {121};set_instance_parameter_value {router_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_018} {DECODER_TYPE} {1};set_instance_parameter_value {router_018} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_018} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_018} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_018} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_018} {MEMORY_ALIASING_DECODE} {0};add_instance {router_019} {altera_merlin_router};set_instance_parameter_value {router_019} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_019} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_019} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_019} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_019} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_019} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_019} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_019} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_019} {SPAN_OFFSET} {};set_instance_parameter_value {router_019} {PKT_ADDR_H} {64};set_instance_parameter_value {router_019} {PKT_ADDR_L} {36};set_instance_parameter_value {router_019} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_019} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_019} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_019} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_019} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_019} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_019} {ST_DATA_W} {121};set_instance_parameter_value {router_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_019} {DECODER_TYPE} {1};set_instance_parameter_value {router_019} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_019} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_019} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_019} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_019} {MEMORY_ALIASING_DECODE} {0};add_instance {router_020} {altera_merlin_router};set_instance_parameter_value {router_020} {DESTINATION_ID} {0 };set_instance_parameter_value {router_020} {CHANNEL_ID} {1 };set_instance_parameter_value {router_020} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_020} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_020} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_020} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_020} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_020} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_020} {SPAN_OFFSET} {};set_instance_parameter_value {router_020} {PKT_ADDR_H} {64};set_instance_parameter_value {router_020} {PKT_ADDR_L} {36};set_instance_parameter_value {router_020} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_020} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_020} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_020} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_020} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_020} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_020} {ST_DATA_W} {121};set_instance_parameter_value {router_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_020} {DECODER_TYPE} {1};set_instance_parameter_value {router_020} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_020} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_020} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_020} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_020} {MEMORY_ALIASING_DECODE} {0};add_instance {router_021} {altera_merlin_router};set_instance_parameter_value {router_021} {DESTINATION_ID} {0 };set_instance_parameter_value {router_021} {CHANNEL_ID} {1 };set_instance_parameter_value {router_021} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_021} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_021} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_021} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_021} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_021} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_021} {SPAN_OFFSET} {};set_instance_parameter_value {router_021} {PKT_ADDR_H} {64};set_instance_parameter_value {router_021} {PKT_ADDR_L} {36};set_instance_parameter_value {router_021} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_021} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_021} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_021} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_021} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_021} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_021} {ST_DATA_W} {121};set_instance_parameter_value {router_021} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_021} {DECODER_TYPE} {1};set_instance_parameter_value {router_021} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_021} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_021} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_021} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_021} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_021} {MEMORY_ALIASING_DECODE} {0};add_instance {router_022} {altera_merlin_router};set_instance_parameter_value {router_022} {DESTINATION_ID} {0 5 2 6 3 };set_instance_parameter_value {router_022} {CHANNEL_ID} {00001 00010 00100 01000 10000 };set_instance_parameter_value {router_022} {TYPE_OF_TRANSACTION} {both read read write write };set_instance_parameter_value {router_022} {START_ADDRESS} {0x0 0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_022} {END_ADDRESS} {0x0 0x0 0x0 0x0 0x0 };set_instance_parameter_value {router_022} {NON_SECURED_TAG} {1 1 1 1 1 };set_instance_parameter_value {router_022} {SECURED_RANGE_PAIRS} {0 0 0 0 0 };set_instance_parameter_value {router_022} {SECURED_RANGE_LIST} {0 0 0 0 0 };set_instance_parameter_value {router_022} {SPAN_OFFSET} {};set_instance_parameter_value {router_022} {PKT_ADDR_H} {64};set_instance_parameter_value {router_022} {PKT_ADDR_L} {36};set_instance_parameter_value {router_022} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_022} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_022} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_022} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_022} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_022} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_022} {ST_DATA_W} {121};set_instance_parameter_value {router_022} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_022} {DECODER_TYPE} {1};set_instance_parameter_value {router_022} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_022} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_022} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_022} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_022} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_022} {MEMORY_ALIASING_DECODE} {0};add_instance {router_023} {altera_merlin_router};set_instance_parameter_value {router_023} {DESTINATION_ID} {0 };set_instance_parameter_value {router_023} {CHANNEL_ID} {1 };set_instance_parameter_value {router_023} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_023} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_023} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_023} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_023} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_023} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_023} {SPAN_OFFSET} {};set_instance_parameter_value {router_023} {PKT_ADDR_H} {64};set_instance_parameter_value {router_023} {PKT_ADDR_L} {36};set_instance_parameter_value {router_023} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_023} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_023} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_023} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_023} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_023} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_023} {ST_DATA_W} {121};set_instance_parameter_value {router_023} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_023} {DECODER_TYPE} {1};set_instance_parameter_value {router_023} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_023} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_023} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_023} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_023} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_023} {MEMORY_ALIASING_DECODE} {0};add_instance {router_024} {altera_merlin_router};set_instance_parameter_value {router_024} {DESTINATION_ID} {0 };set_instance_parameter_value {router_024} {CHANNEL_ID} {1 };set_instance_parameter_value {router_024} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_024} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_024} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_024} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_024} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_024} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_024} {SPAN_OFFSET} {};set_instance_parameter_value {router_024} {PKT_ADDR_H} {64};set_instance_parameter_value {router_024} {PKT_ADDR_L} {36};set_instance_parameter_value {router_024} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_024} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_024} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_024} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_024} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_024} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_024} {ST_DATA_W} {121};set_instance_parameter_value {router_024} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_024} {DECODER_TYPE} {1};set_instance_parameter_value {router_024} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_024} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_024} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_024} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_024} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_024} {MEMORY_ALIASING_DECODE} {0};add_instance {router_025} {altera_merlin_router};set_instance_parameter_value {router_025} {DESTINATION_ID} {0 };set_instance_parameter_value {router_025} {CHANNEL_ID} {1 };set_instance_parameter_value {router_025} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_025} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_025} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_025} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_025} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_025} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_025} {SPAN_OFFSET} {};set_instance_parameter_value {router_025} {PKT_ADDR_H} {64};set_instance_parameter_value {router_025} {PKT_ADDR_L} {36};set_instance_parameter_value {router_025} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_025} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_025} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_025} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_025} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_025} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_025} {ST_DATA_W} {121};set_instance_parameter_value {router_025} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_025} {DECODER_TYPE} {1};set_instance_parameter_value {router_025} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_025} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_025} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_025} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_025} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_025} {MEMORY_ALIASING_DECODE} {0};add_instance {router_026} {altera_merlin_router};set_instance_parameter_value {router_026} {DESTINATION_ID} {0 };set_instance_parameter_value {router_026} {CHANNEL_ID} {1 };set_instance_parameter_value {router_026} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_026} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_026} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_026} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_026} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_026} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_026} {SPAN_OFFSET} {};set_instance_parameter_value {router_026} {PKT_ADDR_H} {64};set_instance_parameter_value {router_026} {PKT_ADDR_L} {36};set_instance_parameter_value {router_026} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_026} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_026} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_026} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_026} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_026} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_026} {ST_DATA_W} {121};set_instance_parameter_value {router_026} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_026} {DECODER_TYPE} {1};set_instance_parameter_value {router_026} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_026} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_026} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_026} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_026} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_026} {MEMORY_ALIASING_DECODE} {0};add_instance {router_027} {altera_merlin_router};set_instance_parameter_value {router_027} {DESTINATION_ID} {0 };set_instance_parameter_value {router_027} {CHANNEL_ID} {1 };set_instance_parameter_value {router_027} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_027} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_027} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_027} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_027} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_027} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_027} {SPAN_OFFSET} {};set_instance_parameter_value {router_027} {PKT_ADDR_H} {64};set_instance_parameter_value {router_027} {PKT_ADDR_L} {36};set_instance_parameter_value {router_027} {PKT_PROTECTION_H} {111};set_instance_parameter_value {router_027} {PKT_PROTECTION_L} {109};set_instance_parameter_value {router_027} {PKT_DEST_ID_H} {107};set_instance_parameter_value {router_027} {PKT_DEST_ID_L} {103};set_instance_parameter_value {router_027} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_027} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_027} {ST_DATA_W} {121};set_instance_parameter_value {router_027} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_027} {DECODER_TYPE} {1};set_instance_parameter_value {router_027} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_027} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_027} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_027} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_027} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_027} {MEMORY_ALIASING_DECODE} {0};add_instance {router_028} {altera_merlin_router};set_instance_parameter_value {router_028} {DESTINATION_ID} {0 };set_instance_parameter_value {router_028} {CHANNEL_ID} {1 };set_instance_parameter_value {router_028} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_028} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_028} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_028} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_028} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_028} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_028} {SPAN_OFFSET} {};set_instance_parameter_value {router_028} {PKT_ADDR_H} {46};set_instance_parameter_value {router_028} {PKT_ADDR_L} {18};set_instance_parameter_value {router_028} {PKT_PROTECTION_H} {93};set_instance_parameter_value {router_028} {PKT_PROTECTION_L} {91};set_instance_parameter_value {router_028} {PKT_DEST_ID_H} {89};set_instance_parameter_value {router_028} {PKT_DEST_ID_L} {85};set_instance_parameter_value {router_028} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {router_028} {PKT_TRANS_READ} {50};set_instance_parameter_value {router_028} {ST_DATA_W} {103};set_instance_parameter_value {router_028} {ST_CHANNEL_W} {21};set_instance_parameter_value {router_028} {DECODER_TYPE} {1};set_instance_parameter_value {router_028} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_028} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_028} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_028} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_028} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {router_028} {MEMORY_ALIASING_DECODE} {0};add_instance {cpu_data_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {cpu_data_master_limiter} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_data_master_limiter} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_data_master_limiter} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_data_master_limiter} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_data_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_data_master_limiter} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_data_master_limiter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_data_master_limiter} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_data_master_limiter} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_data_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {cpu_data_master_limiter} {MAX_OUTSTANDING_RESPONSES} {36};set_instance_parameter_value {cpu_data_master_limiter} {PIPELINED} {0};set_instance_parameter_value {cpu_data_master_limiter} {ST_DATA_W} {121};set_instance_parameter_value {cpu_data_master_limiter} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_data_master_limiter} {VALID_WIDTH} {21};set_instance_parameter_value {cpu_data_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {cpu_data_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {cpu_data_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {cpu_data_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {cpu_data_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_data_master_limiter} {REORDER} {0};add_instance {cpu_instruction_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_DEST_ID_H} {107};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_DEST_ID_L} {103};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_SRC_ID_H} {102};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_SRC_ID_L} {98};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_THREAD_ID_H} {108};set_instance_parameter_value {cpu_instruction_master_limiter} {PKT_THREAD_ID_L} {108};set_instance_parameter_value {cpu_instruction_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {MAX_OUTSTANDING_RESPONSES} {36};set_instance_parameter_value {cpu_instruction_master_limiter} {PIPELINED} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {ST_DATA_W} {121};set_instance_parameter_value {cpu_instruction_master_limiter} {ST_CHANNEL_W} {21};set_instance_parameter_value {cpu_instruction_master_limiter} {VALID_WIDTH} {21};set_instance_parameter_value {cpu_instruction_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {cpu_instruction_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {cpu_instruction_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cpu_instruction_master_limiter} {REORDER} {0};add_instance {ext_flash_avl_mem_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_ADDR_H} {64};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_ADDR_L} {36};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_BURSTWRAP_L} {80};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PKT_TRANS_READ} {68};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ST_DATA_W} {121};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_BYTE_CNT_H} {79};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {OUT_BURSTWRAP_H} {87};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {COMPRESSED_READ_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BURSTWRAP_CONST_MASK} {3};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {BURSTWRAP_CONST_VALUE} {3};set_instance_parameter_value {ext_flash_avl_mem_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {calibration_ram_s1_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BEGIN_BURST} {78};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PKT_TRANS_READ} {50};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_BYTE_CNT_H} {54};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {OUT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {COMPRESSED_READ_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BURSTWRAP_CONST_MASK} {511};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {BURSTWRAP_CONST_VALUE} {511};set_instance_parameter_value {calibration_ram_s1_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {21};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {21};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {4};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {21};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_002} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_002} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_003} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_004} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_005} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_006} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_007} {ST_DATA_W} {121};set_instance_parameter_value {cmd_demux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {4};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_003} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_003} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_003} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_004} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_004} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_004} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_005} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_005} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_005} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_006} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_006} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_006} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_007} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_007} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_007} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_008} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_008} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_008} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_008} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_008} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_008} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_009} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_009} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_009} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_009} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_009} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_009} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_010} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_010} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_010} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_010} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_010} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_010} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_011} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_011} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_011} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_011} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_011} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_011} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_012} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_012} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_012} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_012} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_012} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_012} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_013} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_013} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_013} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_013} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_013} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_013} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_014} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_014} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_014} {NUM_INPUTS} {5};set_instance_parameter_value {cmd_mux_014} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_014} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_014} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SHARES} {1 1 1 1 1 };set_instance_parameter_value {cmd_mux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_015} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_015} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_015} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_015} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_015} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_015} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_015} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_015} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_016} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_016} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_016} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_016} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_016} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_016} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_016} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_016} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_017} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_017} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_017} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_017} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_017} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_017} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_017} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_017} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_018} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_018} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_018} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_018} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_018} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_018} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_018} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_018} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_019} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_019} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_019} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_019} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_019} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_019} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_019} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_019} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_020} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_020} {ST_DATA_W} {121};set_instance_parameter_value {cmd_mux_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {cmd_mux_020} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_020} {PIPELINE_ARB} {0};set_instance_parameter_value {cmd_mux_020} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_020} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux_020} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_020} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {4};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_003} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_004} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_004} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_005} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_006} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_007} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_007} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_008} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_008} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_008} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_008} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_008} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_009} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_009} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_009} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_009} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_009} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_010} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_010} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_010} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_010} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_010} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_011} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_011} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_011} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_011} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_011} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_012} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_012} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_012} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_012} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_012} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_013} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_013} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_013} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_013} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_013} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_014} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_014} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_014} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_014} {NUM_OUTPUTS} {5};set_instance_parameter_value {rsp_demux_014} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_015} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_015} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_015} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_015} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_015} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_016} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_016} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_016} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_016} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_016} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_017} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_017} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_017} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_017} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_017} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_017} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_018} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_018} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_018} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_018} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_018} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_018} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_019} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_019} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_019} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_019} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_019} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_019} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_020} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_020} {ST_DATA_W} {121};set_instance_parameter_value {rsp_demux_020} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_demux_020} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_020} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_020} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {21};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {4};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_002} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_002} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_002} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_002} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_002} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_002} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_002} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_003} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_003} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_003} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_003} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_003} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_004} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_004} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_004} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_004} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_004} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_004} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_004} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_005} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_005} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_005} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_005} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_005} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_006} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_006} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_006} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_006} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_006} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_007} {ST_DATA_W} {121};set_instance_parameter_value {rsp_mux_007} {ST_CHANNEL_W} {21};set_instance_parameter_value {rsp_mux_007} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_007} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_007} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_007} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_007} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};add_instance {calibration_ram_s1_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_WRITE} {49};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {70};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {62};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {52};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ADDR_H} {64};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ADDR_L} {36};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_DATA_H} {31};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {35};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {32};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {79};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {71};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {91};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {89};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {93};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {92};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_ST_DATA_W} {121};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {calibration_ram_s1_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {calibration_ram_s1_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ADDR_H} {64};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ADDR_L} {36};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_DATA_H} {31};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_H} {35};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_L} {32};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {79};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {71};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_WRITE} {67};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {88};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {80};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {91};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {89};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {117};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {116};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {93};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {92};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {118};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {120};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_ST_DATA_W} {121};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ADDR_H} {46};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ADDR_L} {18};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_DATA_H} {15};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {17};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {16};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {61};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {53};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {47};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {73};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {71};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {99};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {98};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {52};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {75};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {74};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {100};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {102};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_ST_DATA_W} {103};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {ST_CHANNEL_W} {21};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {calibration_ram_s1_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {crosser} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser} {DATA_WIDTH} {121};set_instance_parameter_value {crosser} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser} {USE_PACKETS} {1};set_instance_parameter_value {crosser} {USE_CHANNEL} {1};set_instance_parameter_value {crosser} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser} {USE_ERROR} {0};set_instance_parameter_value {crosser} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_001} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_001} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_001} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_001} {USE_PACKETS} {1};set_instance_parameter_value {crosser_001} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_001} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_001} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_001} {USE_ERROR} {0};set_instance_parameter_value {crosser_001} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_001} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_002} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_002} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_002} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_002} {USE_PACKETS} {1};set_instance_parameter_value {crosser_002} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_002} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_002} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_002} {USE_ERROR} {0};set_instance_parameter_value {crosser_002} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_002} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_003} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_003} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_003} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_003} {USE_PACKETS} {1};set_instance_parameter_value {crosser_003} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_003} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_003} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_003} {USE_ERROR} {0};set_instance_parameter_value {crosser_003} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_003} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_004} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_004} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_004} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_004} {USE_PACKETS} {1};set_instance_parameter_value {crosser_004} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_004} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_004} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_004} {USE_ERROR} {0};set_instance_parameter_value {crosser_004} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_004} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_004} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_004} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_005} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_005} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_005} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_005} {USE_PACKETS} {1};set_instance_parameter_value {crosser_005} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_005} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_005} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_005} {USE_ERROR} {0};set_instance_parameter_value {crosser_005} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_005} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_005} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_005} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_006} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_006} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_006} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_006} {USE_PACKETS} {1};set_instance_parameter_value {crosser_006} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_006} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_006} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_006} {USE_ERROR} {0};set_instance_parameter_value {crosser_006} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_006} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_006} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_006} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_007} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_007} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_007} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_007} {USE_PACKETS} {1};set_instance_parameter_value {crosser_007} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_007} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_007} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_007} {USE_ERROR} {0};set_instance_parameter_value {crosser_007} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_007} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_007} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_007} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_008} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_008} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_008} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_008} {USE_PACKETS} {1};set_instance_parameter_value {crosser_008} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_008} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_008} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_008} {USE_ERROR} {0};set_instance_parameter_value {crosser_008} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_008} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_008} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_008} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_009} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_009} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_009} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_009} {USE_PACKETS} {1};set_instance_parameter_value {crosser_009} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_009} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_009} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_009} {USE_ERROR} {0};set_instance_parameter_value {crosser_009} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_009} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_009} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_009} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_010} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_010} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_010} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_010} {USE_PACKETS} {1};set_instance_parameter_value {crosser_010} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_010} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_010} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_010} {USE_ERROR} {0};set_instance_parameter_value {crosser_010} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_010} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_010} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_010} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_011} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_011} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_011} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_011} {USE_PACKETS} {1};set_instance_parameter_value {crosser_011} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_011} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_011} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_011} {USE_ERROR} {0};set_instance_parameter_value {crosser_011} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_011} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_011} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_011} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_012} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_012} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_012} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_012} {USE_PACKETS} {1};set_instance_parameter_value {crosser_012} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_012} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_012} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_012} {USE_ERROR} {0};set_instance_parameter_value {crosser_012} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_012} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_012} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_012} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_013} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_013} {DATA_WIDTH} {121};set_instance_parameter_value {crosser_013} {BITS_PER_SYMBOL} {121};set_instance_parameter_value {crosser_013} {USE_PACKETS} {1};set_instance_parameter_value {crosser_013} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_013} {CHANNEL_WIDTH} {21};set_instance_parameter_value {crosser_013} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_013} {USE_ERROR} {0};set_instance_parameter_value {crosser_013} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_013} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_013} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_013} {USE_OUTPUT_PIPELINE} {0};add_instance {cpu_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {cpu_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {cpu_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {cpu_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {cpu_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ddr3_ram_soft_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ddr3_ram_soft_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ext_flash_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ext_flash_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ext_flash_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ext_flash_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ext_flash_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {eth_tse_reset_connection_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {eth_tse_reset_connection_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {ddr3_ram_avl_translator_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {ddr3_ram_avl_translator_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {sys_clk_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {sys_clk_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {sys_clk_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_instance {ddr3_ram_afi_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {ddr3_ram_afi_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {150000000};set_instance_parameter_value {ddr3_ram_afi_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_instance {ext_flash_clock_bridge_out_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {ext_flash_clock_bridge_out_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {0};set_instance_parameter_value {ext_flash_clock_bridge_out_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {cpu_data_master_translator.avalon_universal_master_0} {cpu_data_master_agent.av} {avalon};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_data_master_translator.avalon_universal_master_0/cpu_data_master_agent.av} {defaultConnection} {false};add_connection {cpu_instruction_master_translator.avalon_universal_master_0} {cpu_instruction_master_agent.av} {avalon};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {cpu_instruction_master_translator.avalon_universal_master_0/cpu_instruction_master_agent.av} {defaultConnection} {false};add_connection {msgdma_tx_mm_read_translator.avalon_universal_master_0} {msgdma_tx_mm_read_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_mm_read_translator.avalon_universal_master_0/msgdma_tx_mm_read_agent.av} {defaultConnection} {false};add_connection {rsp_mux_002.src} {msgdma_tx_mm_read_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_002.src/msgdma_tx_mm_read_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_mm_write_translator.avalon_universal_master_0} {msgdma_rx_mm_write_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_mm_write_translator.avalon_universal_master_0/msgdma_rx_mm_write_agent.av} {defaultConnection} {false};add_connection {rsp_mux_003.src} {msgdma_rx_mm_write_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_003.src/msgdma_rx_mm_write_agent.rp} {qsys_mm.response};add_connection {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0} {msgdma_tx_descriptor_read_master_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_read_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_004.src} {msgdma_tx_descriptor_read_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_004.src/msgdma_tx_descriptor_read_master_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0} {msgdma_rx_descriptor_read_master_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_descriptor_read_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_read_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_005.src} {msgdma_rx_descriptor_read_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_005.src/msgdma_rx_descriptor_read_master_agent.rp} {qsys_mm.response};add_connection {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0} {msgdma_tx_descriptor_write_master_agent.av} {avalon};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_tx_descriptor_write_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_006.src} {msgdma_tx_descriptor_write_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_006.src/msgdma_tx_descriptor_write_master_agent.rp} {qsys_mm.response};add_connection {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0} {msgdma_rx_descriptor_write_master_agent.av} {avalon};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_descriptor_write_master_translator.avalon_universal_master_0/msgdma_rx_descriptor_write_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_007.src} {msgdma_rx_descriptor_write_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_007.src/msgdma_rx_descriptor_write_master_agent.rp} {qsys_mm.response};add_connection {ddr3_ram_avl_agent.m0} {ddr3_ram_avl_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ddr3_ram_avl_agent.m0/ddr3_ram_avl_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ddr3_ram_avl_agent.rf_source} {ddr3_ram_avl_agent_rsp_fifo.in} {avalon_streaming};add_connection {ddr3_ram_avl_agent_rsp_fifo.out} {ddr3_ram_avl_agent.rf_sink} {avalon_streaming};add_connection {ddr3_ram_avl_agent.rdata_fifo_src} {ddr3_ram_avl_agent_rdata_fifo.in} {avalon_streaming};add_connection {ddr3_ram_avl_agent_rdata_fifo.out} {ddr3_ram_avl_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {ddr3_ram_avl_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/ddr3_ram_avl_agent.cp} {qsys_mm.command};add_connection {ext_flash_avl_csr_agent.m0} {ext_flash_avl_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ext_flash_avl_csr_agent.m0/ext_flash_avl_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ext_flash_avl_csr_agent.rf_source} {ext_flash_avl_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_csr_agent_rsp_fifo.out} {ext_flash_avl_csr_agent.rf_sink} {avalon_streaming};add_connection {ext_flash_avl_csr_agent.rdata_fifo_src} {ext_flash_avl_csr_agent_rdata_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_csr_agent_rdata_fifo.out} {ext_flash_avl_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_001.src} {ext_flash_avl_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/ext_flash_avl_csr_agent.cp} {qsys_mm.command};add_connection {ext_flash_avl_mem_agent.m0} {ext_flash_avl_mem_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {ext_flash_avl_mem_agent.m0/ext_flash_avl_mem_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {ext_flash_avl_mem_agent.rf_source} {ext_flash_avl_mem_agent_rsp_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_mem_agent_rsp_fifo.out} {ext_flash_avl_mem_agent.rf_sink} {avalon_streaming};add_connection {ext_flash_avl_mem_agent.rdata_fifo_src} {ext_flash_avl_mem_agent_rdata_fifo.in} {avalon_streaming};add_connection {ext_flash_avl_mem_agent_rdata_fifo.out} {ext_flash_avl_mem_agent.rdata_fifo_sink} {avalon_streaming};add_connection {eth_tse_control_port_agent.m0} {eth_tse_control_port_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {eth_tse_control_port_agent.m0/eth_tse_control_port_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {eth_tse_control_port_agent.rf_source} {eth_tse_control_port_agent_rsp_fifo.in} {avalon_streaming};add_connection {eth_tse_control_port_agent_rsp_fifo.out} {eth_tse_control_port_agent.rf_sink} {avalon_streaming};add_connection {eth_tse_control_port_agent.rdata_fifo_src} {eth_tse_control_port_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_003.src} {eth_tse_control_port_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_003.src/eth_tse_control_port_agent.cp} {qsys_mm.command};add_connection {sysid_control_slave_agent.m0} {sysid_control_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sysid_control_slave_agent.m0/sysid_control_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sysid_control_slave_agent.rf_source} {sysid_control_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sysid_control_slave_agent_rsp_fifo.out} {sysid_control_slave_agent.rf_sink} {avalon_streaming};add_connection {sysid_control_slave_agent.rdata_fifo_src} {sysid_control_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_004.src} {sysid_control_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_004.src/sysid_control_slave_agent.cp} {qsys_mm.command};add_connection {msgdma_tx_csr_agent.m0} {msgdma_tx_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_csr_agent.m0/msgdma_tx_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_tx_csr_agent.rf_source} {msgdma_tx_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_tx_csr_agent_rsp_fifo.out} {msgdma_tx_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_tx_csr_agent.rdata_fifo_src} {msgdma_tx_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_005.src} {msgdma_tx_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_005.src/msgdma_tx_csr_agent.cp} {qsys_mm.command};add_connection {msgdma_rx_csr_agent.m0} {msgdma_rx_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_csr_agent.m0/msgdma_rx_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_rx_csr_agent.rf_source} {msgdma_rx_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_rx_csr_agent_rsp_fifo.out} {msgdma_rx_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_rx_csr_agent.rdata_fifo_src} {msgdma_rx_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_006.src} {msgdma_rx_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_006.src/msgdma_rx_csr_agent.cp} {qsys_mm.command};add_connection {onchip_flash_csr_agent.m0} {onchip_flash_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_flash_csr_agent.m0/onchip_flash_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_flash_csr_agent.rf_source} {onchip_flash_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_flash_csr_agent_rsp_fifo.out} {onchip_flash_csr_agent.rf_sink} {avalon_streaming};add_connection {onchip_flash_csr_agent.rdata_fifo_src} {onchip_flash_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_007.src} {onchip_flash_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_007.src/onchip_flash_csr_agent.cp} {qsys_mm.command};add_connection {udp_generator_csr_agent.m0} {udp_generator_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {udp_generator_csr_agent.m0/udp_generator_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {udp_generator_csr_agent.rf_source} {udp_generator_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {udp_generator_csr_agent_rsp_fifo.out} {udp_generator_csr_agent.rf_sink} {avalon_streaming};add_connection {udp_generator_csr_agent.rdata_fifo_src} {udp_generator_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_008.src} {udp_generator_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_008.src/udp_generator_csr_agent.cp} {qsys_mm.command};add_connection {sensor_interface_csr_agent.m0} {sensor_interface_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sensor_interface_csr_agent.m0/sensor_interface_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sensor_interface_csr_agent.rf_source} {sensor_interface_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {sensor_interface_csr_agent_rsp_fifo.out} {sensor_interface_csr_agent.rf_sink} {avalon_streaming};add_connection {sensor_interface_csr_agent.rdata_fifo_src} {sensor_interface_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_009.src} {sensor_interface_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_009.src/sensor_interface_csr_agent.cp} {qsys_mm.command};add_connection {onchip_flash_data_agent.m0} {onchip_flash_data_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_flash_data_agent.m0/onchip_flash_data_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_flash_data_agent.rf_source} {onchip_flash_data_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_flash_data_agent_rsp_fifo.out} {onchip_flash_data_agent.rf_sink} {avalon_streaming};add_connection {onchip_flash_data_agent.rdata_fifo_src} {onchip_flash_data_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_010.src} {onchip_flash_data_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_010.src/onchip_flash_data_agent.cp} {qsys_mm.command};add_connection {cpu_debug_mem_slave_agent.m0} {cpu_debug_mem_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {cpu_debug_mem_slave_agent.m0/cpu_debug_mem_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {cpu_debug_mem_slave_agent.rf_source} {cpu_debug_mem_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent_rsp_fifo.out} {cpu_debug_mem_slave_agent.rf_sink} {avalon_streaming};add_connection {cpu_debug_mem_slave_agent.rdata_fifo_src} {cpu_debug_mem_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_011.src} {cpu_debug_mem_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_011.src/cpu_debug_mem_slave_agent.cp} {qsys_mm.command};add_connection {msgdma_tx_prefetcher_csr_agent.m0} {msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_tx_prefetcher_csr_agent.m0/msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_tx_prefetcher_csr_agent.rf_source} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_tx_prefetcher_csr_agent_rsp_fifo.out} {msgdma_tx_prefetcher_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_tx_prefetcher_csr_agent.rdata_fifo_src} {msgdma_tx_prefetcher_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_012.src} {msgdma_tx_prefetcher_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_012.src/msgdma_tx_prefetcher_csr_agent.cp} {qsys_mm.command};add_connection {msgdma_rx_prefetcher_csr_agent.m0} {msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {msgdma_rx_prefetcher_csr_agent.m0/msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {msgdma_rx_prefetcher_csr_agent.rf_source} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.in} {avalon_streaming};add_connection {msgdma_rx_prefetcher_csr_agent_rsp_fifo.out} {msgdma_rx_prefetcher_csr_agent.rf_sink} {avalon_streaming};add_connection {msgdma_rx_prefetcher_csr_agent.rdata_fifo_src} {msgdma_rx_prefetcher_csr_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_013.src} {msgdma_rx_prefetcher_csr_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_013.src/msgdma_rx_prefetcher_csr_agent.cp} {qsys_mm.command};add_connection {descriptor_memory_s1_agent.m0} {descriptor_memory_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {descriptor_memory_s1_agent.m0/descriptor_memory_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {descriptor_memory_s1_agent.rf_source} {descriptor_memory_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {descriptor_memory_s1_agent_rsp_fifo.out} {descriptor_memory_s1_agent.rf_sink} {avalon_streaming};add_connection {descriptor_memory_s1_agent.rdata_fifo_src} {descriptor_memory_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_014.src} {descriptor_memory_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_014.src/descriptor_memory_s1_agent.cp} {qsys_mm.command};add_connection {sys_clk_timer_s1_agent.m0} {sys_clk_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sys_clk_timer_s1_agent.m0/sys_clk_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sys_clk_timer_s1_agent.rf_source} {sys_clk_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {sys_clk_timer_s1_agent_rsp_fifo.out} {sys_clk_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {sys_clk_timer_s1_agent.rdata_fifo_src} {sys_clk_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_015.src} {sys_clk_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_015.src/sys_clk_timer_s1_agent.cp} {qsys_mm.command};add_connection {output_pio_s1_agent.m0} {output_pio_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {output_pio_s1_agent.m0/output_pio_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {output_pio_s1_agent.rf_source} {output_pio_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {output_pio_s1_agent_rsp_fifo.out} {output_pio_s1_agent.rf_sink} {avalon_streaming};add_connection {output_pio_s1_agent.rdata_fifo_src} {output_pio_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_016.src} {output_pio_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_016.src/output_pio_s1_agent.cp} {qsys_mm.command};add_connection {button_pio_s1_agent.m0} {button_pio_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {button_pio_s1_agent.m0/button_pio_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {button_pio_s1_agent.rf_source} {button_pio_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {button_pio_s1_agent_rsp_fifo.out} {button_pio_s1_agent.rf_sink} {avalon_streaming};add_connection {button_pio_s1_agent.rdata_fifo_src} {button_pio_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_017.src} {button_pio_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_017.src/button_pio_s1_agent.cp} {qsys_mm.command};add_connection {debug_uart_s1_agent.m0} {debug_uart_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {debug_uart_s1_agent.m0/debug_uart_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {debug_uart_s1_agent.rf_source} {debug_uart_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {debug_uart_s1_agent_rsp_fifo.out} {debug_uart_s1_agent.rf_sink} {avalon_streaming};add_connection {debug_uart_s1_agent.rdata_fifo_src} {debug_uart_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_018.src} {debug_uart_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_018.src/debug_uart_s1_agent.cp} {qsys_mm.command};add_connection {frame_timer_s1_agent.m0} {frame_timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {frame_timer_s1_agent.m0/frame_timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {frame_timer_s1_agent.rf_source} {frame_timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {frame_timer_s1_agent_rsp_fifo.out} {frame_timer_s1_agent.rf_sink} {avalon_streaming};add_connection {frame_timer_s1_agent.rdata_fifo_src} {frame_timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_019.src} {frame_timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_019.src/frame_timer_s1_agent.cp} {qsys_mm.command};add_connection {calibration_ram_s1_agent.m0} {calibration_ram_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {calibration_ram_s1_agent.m0/calibration_ram_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {calibration_ram_s1_agent.rf_source} {calibration_ram_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {calibration_ram_s1_agent_rsp_fifo.out} {calibration_ram_s1_agent.rf_sink} {avalon_streaming};add_connection {calibration_ram_s1_agent.rdata_fifo_src} {calibration_ram_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cpu_data_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_agent.cp/router.sink} {qsys_mm.command};add_connection {cpu_instruction_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {msgdma_tx_mm_read_agent.cp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_mm_read_agent.cp/router_002.sink} {qsys_mm.command};add_connection {router_002.src} {cmd_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/cmd_demux_002.sink} {qsys_mm.command};add_connection {msgdma_rx_mm_write_agent.cp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_mm_write_agent.cp/router_003.sink} {qsys_mm.command};add_connection {router_003.src} {cmd_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/cmd_demux_003.sink} {qsys_mm.command};add_connection {msgdma_tx_descriptor_read_master_agent.cp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_descriptor_read_master_agent.cp/router_004.sink} {qsys_mm.command};add_connection {router_004.src} {cmd_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/cmd_demux_004.sink} {qsys_mm.command};add_connection {msgdma_rx_descriptor_read_master_agent.cp} {router_005.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_descriptor_read_master_agent.cp/router_005.sink} {qsys_mm.command};add_connection {router_005.src} {cmd_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_005.src/cmd_demux_005.sink} {qsys_mm.command};add_connection {msgdma_tx_descriptor_write_master_agent.cp} {router_006.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_descriptor_write_master_agent.cp/router_006.sink} {qsys_mm.command};add_connection {router_006.src} {cmd_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_006.src/cmd_demux_006.sink} {qsys_mm.command};add_connection {msgdma_rx_descriptor_write_master_agent.cp} {router_007.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_descriptor_write_master_agent.cp/router_007.sink} {qsys_mm.command};add_connection {router_007.src} {cmd_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_007.src/cmd_demux_007.sink} {qsys_mm.command};add_connection {ddr3_ram_avl_agent.rp} {router_008.sink} {avalon_streaming};preview_set_connection_tag {ddr3_ram_avl_agent.rp/router_008.sink} {qsys_mm.response};add_connection {router_008.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_008.src/rsp_demux.sink} {qsys_mm.response};add_connection {ext_flash_avl_csr_agent.rp} {router_009.sink} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_csr_agent.rp/router_009.sink} {qsys_mm.response};add_connection {router_009.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_009.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {ext_flash_avl_mem_agent.rp} {router_010.sink} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_mem_agent.rp/router_010.sink} {qsys_mm.response};add_connection {router_010.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_010.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {eth_tse_control_port_agent.rp} {router_011.sink} {avalon_streaming};preview_set_connection_tag {eth_tse_control_port_agent.rp/router_011.sink} {qsys_mm.response};add_connection {router_011.src} {rsp_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_011.src/rsp_demux_003.sink} {qsys_mm.response};add_connection {sysid_control_slave_agent.rp} {router_012.sink} {avalon_streaming};preview_set_connection_tag {sysid_control_slave_agent.rp/router_012.sink} {qsys_mm.response};add_connection {router_012.src} {rsp_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_012.src/rsp_demux_004.sink} {qsys_mm.response};add_connection {msgdma_tx_csr_agent.rp} {router_013.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_csr_agent.rp/router_013.sink} {qsys_mm.response};add_connection {router_013.src} {rsp_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_013.src/rsp_demux_005.sink} {qsys_mm.response};add_connection {msgdma_rx_csr_agent.rp} {router_014.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_csr_agent.rp/router_014.sink} {qsys_mm.response};add_connection {router_014.src} {rsp_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_014.src/rsp_demux_006.sink} {qsys_mm.response};add_connection {onchip_flash_csr_agent.rp} {router_015.sink} {avalon_streaming};preview_set_connection_tag {onchip_flash_csr_agent.rp/router_015.sink} {qsys_mm.response};add_connection {router_015.src} {rsp_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_015.src/rsp_demux_007.sink} {qsys_mm.response};add_connection {udp_generator_csr_agent.rp} {router_016.sink} {avalon_streaming};preview_set_connection_tag {udp_generator_csr_agent.rp/router_016.sink} {qsys_mm.response};add_connection {router_016.src} {rsp_demux_008.sink} {avalon_streaming};preview_set_connection_tag {router_016.src/rsp_demux_008.sink} {qsys_mm.response};add_connection {sensor_interface_csr_agent.rp} {router_017.sink} {avalon_streaming};preview_set_connection_tag {sensor_interface_csr_agent.rp/router_017.sink} {qsys_mm.response};add_connection {router_017.src} {rsp_demux_009.sink} {avalon_streaming};preview_set_connection_tag {router_017.src/rsp_demux_009.sink} {qsys_mm.response};add_connection {onchip_flash_data_agent.rp} {router_018.sink} {avalon_streaming};preview_set_connection_tag {onchip_flash_data_agent.rp/router_018.sink} {qsys_mm.response};add_connection {router_018.src} {rsp_demux_010.sink} {avalon_streaming};preview_set_connection_tag {router_018.src/rsp_demux_010.sink} {qsys_mm.response};add_connection {cpu_debug_mem_slave_agent.rp} {router_019.sink} {avalon_streaming};preview_set_connection_tag {cpu_debug_mem_slave_agent.rp/router_019.sink} {qsys_mm.response};add_connection {router_019.src} {rsp_demux_011.sink} {avalon_streaming};preview_set_connection_tag {router_019.src/rsp_demux_011.sink} {qsys_mm.response};add_connection {msgdma_tx_prefetcher_csr_agent.rp} {router_020.sink} {avalon_streaming};preview_set_connection_tag {msgdma_tx_prefetcher_csr_agent.rp/router_020.sink} {qsys_mm.response};add_connection {router_020.src} {rsp_demux_012.sink} {avalon_streaming};preview_set_connection_tag {router_020.src/rsp_demux_012.sink} {qsys_mm.response};add_connection {msgdma_rx_prefetcher_csr_agent.rp} {router_021.sink} {avalon_streaming};preview_set_connection_tag {msgdma_rx_prefetcher_csr_agent.rp/router_021.sink} {qsys_mm.response};add_connection {router_021.src} {rsp_demux_013.sink} {avalon_streaming};preview_set_connection_tag {router_021.src/rsp_demux_013.sink} {qsys_mm.response};add_connection {descriptor_memory_s1_agent.rp} {router_022.sink} {avalon_streaming};preview_set_connection_tag {descriptor_memory_s1_agent.rp/router_022.sink} {qsys_mm.response};add_connection {router_022.src} {rsp_demux_014.sink} {avalon_streaming};preview_set_connection_tag {router_022.src/rsp_demux_014.sink} {qsys_mm.response};add_connection {sys_clk_timer_s1_agent.rp} {router_023.sink} {avalon_streaming};preview_set_connection_tag {sys_clk_timer_s1_agent.rp/router_023.sink} {qsys_mm.response};add_connection {router_023.src} {rsp_demux_015.sink} {avalon_streaming};preview_set_connection_tag {router_023.src/rsp_demux_015.sink} {qsys_mm.response};add_connection {output_pio_s1_agent.rp} {router_024.sink} {avalon_streaming};preview_set_connection_tag {output_pio_s1_agent.rp/router_024.sink} {qsys_mm.response};add_connection {router_024.src} {rsp_demux_016.sink} {avalon_streaming};preview_set_connection_tag {router_024.src/rsp_demux_016.sink} {qsys_mm.response};add_connection {button_pio_s1_agent.rp} {router_025.sink} {avalon_streaming};preview_set_connection_tag {button_pio_s1_agent.rp/router_025.sink} {qsys_mm.response};add_connection {router_025.src} {rsp_demux_017.sink} {avalon_streaming};preview_set_connection_tag {router_025.src/rsp_demux_017.sink} {qsys_mm.response};add_connection {debug_uart_s1_agent.rp} {router_026.sink} {avalon_streaming};preview_set_connection_tag {debug_uart_s1_agent.rp/router_026.sink} {qsys_mm.response};add_connection {router_026.src} {rsp_demux_018.sink} {avalon_streaming};preview_set_connection_tag {router_026.src/rsp_demux_018.sink} {qsys_mm.response};add_connection {frame_timer_s1_agent.rp} {router_027.sink} {avalon_streaming};preview_set_connection_tag {frame_timer_s1_agent.rp/router_027.sink} {qsys_mm.response};add_connection {router_027.src} {rsp_demux_019.sink} {avalon_streaming};preview_set_connection_tag {router_027.src/rsp_demux_019.sink} {qsys_mm.response};add_connection {calibration_ram_s1_agent.rp} {router_028.sink} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_agent.rp/router_028.sink} {qsys_mm.response};add_connection {router.src} {cpu_data_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router.src/cpu_data_master_limiter.cmd_sink} {qsys_mm.command};add_connection {cpu_data_master_limiter.cmd_src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {cpu_data_master_limiter.cmd_src/cmd_demux.sink} {qsys_mm.command};add_connection {rsp_mux.src} {cpu_data_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/cpu_data_master_limiter.rsp_sink} {qsys_mm.response};add_connection {cpu_data_master_limiter.rsp_src} {cpu_data_master_agent.rp} {avalon_streaming};preview_set_connection_tag {cpu_data_master_limiter.rsp_src/cpu_data_master_agent.rp} {qsys_mm.response};add_connection {router_001.src} {cpu_instruction_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cpu_instruction_master_limiter.cmd_sink} {qsys_mm.command};add_connection {cpu_instruction_master_limiter.cmd_src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_limiter.cmd_src/cmd_demux_001.sink} {qsys_mm.command};add_connection {rsp_mux_001.src} {cpu_instruction_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/cpu_instruction_master_limiter.rsp_sink} {qsys_mm.response};add_connection {cpu_instruction_master_limiter.rsp_src} {cpu_instruction_master_agent.rp} {avalon_streaming};preview_set_connection_tag {cpu_instruction_master_limiter.rsp_src/cpu_instruction_master_agent.rp} {qsys_mm.response};add_connection {cmd_mux_002.src} {ext_flash_avl_mem_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/ext_flash_avl_mem_burst_adapter.sink0} {qsys_mm.command};add_connection {ext_flash_avl_mem_burst_adapter.source0} {ext_flash_avl_mem_agent.cp} {avalon_streaming};preview_set_connection_tag {ext_flash_avl_mem_burst_adapter.source0/ext_flash_avl_mem_agent.cp} {qsys_mm.command};add_connection {calibration_ram_s1_burst_adapter.source0} {calibration_ram_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_burst_adapter.source0/calibration_ram_s1_agent.cp} {qsys_mm.command};add_connection {cmd_demux.src3} {cmd_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src3/cmd_mux_003.sink0} {qsys_mm.command};add_connection {cmd_demux.src4} {cmd_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src4/cmd_mux_004.sink0} {qsys_mm.command};add_connection {cmd_demux.src5} {cmd_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src5/cmd_mux_005.sink0} {qsys_mm.command};add_connection {cmd_demux.src6} {cmd_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src6/cmd_mux_006.sink0} {qsys_mm.command};add_connection {cmd_demux.src7} {cmd_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src7/cmd_mux_007.sink0} {qsys_mm.command};add_connection {cmd_demux.src8} {cmd_mux_008.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src8/cmd_mux_008.sink0} {qsys_mm.command};add_connection {cmd_demux.src9} {cmd_mux_009.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src9/cmd_mux_009.sink0} {qsys_mm.command};add_connection {cmd_demux.src10} {cmd_mux_010.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src10/cmd_mux_010.sink0} {qsys_mm.command};add_connection {cmd_demux.src11} {cmd_mux_011.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src11/cmd_mux_011.sink0} {qsys_mm.command};add_connection {cmd_demux.src12} {cmd_mux_012.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src12/cmd_mux_012.sink0} {qsys_mm.command};add_connection {cmd_demux.src13} {cmd_mux_013.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src13/cmd_mux_013.sink0} {qsys_mm.command};add_connection {cmd_demux.src14} {cmd_mux_014.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src14/cmd_mux_014.sink0} {qsys_mm.command};add_connection {cmd_demux.src15} {cmd_mux_015.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src15/cmd_mux_015.sink0} {qsys_mm.command};add_connection {cmd_demux.src16} {cmd_mux_016.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src16/cmd_mux_016.sink0} {qsys_mm.command};add_connection {cmd_demux.src17} {cmd_mux_017.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src17/cmd_mux_017.sink0} {qsys_mm.command};add_connection {cmd_demux.src18} {cmd_mux_018.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src18/cmd_mux_018.sink0} {qsys_mm.command};add_connection {cmd_demux.src19} {cmd_mux_019.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src19/cmd_mux_019.sink0} {qsys_mm.command};add_connection {cmd_demux.src20} {cmd_mux_020.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src20/cmd_mux_020.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src2} {cmd_mux_010.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src2/cmd_mux_010.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src3} {cmd_mux_011.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src3/cmd_mux_011.sink1} {qsys_mm.command};add_connection {cmd_demux_004.src0} {cmd_mux_014.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_004.src0/cmd_mux_014.sink1} {qsys_mm.command};add_connection {cmd_demux_005.src0} {cmd_mux_014.sink2} {avalon_streaming};preview_set_connection_tag {cmd_demux_005.src0/cmd_mux_014.sink2} {qsys_mm.command};add_connection {cmd_demux_006.src0} {cmd_mux_014.sink3} {avalon_streaming};preview_set_connection_tag {cmd_demux_006.src0/cmd_mux_014.sink3} {qsys_mm.command};add_connection {cmd_demux_007.src0} {cmd_mux_014.sink4} {avalon_streaming};preview_set_connection_tag {cmd_demux_007.src0/cmd_mux_014.sink4} {qsys_mm.command};add_connection {rsp_demux_003.src0} {rsp_mux.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src0/rsp_mux.sink3} {qsys_mm.response};add_connection {rsp_demux_004.src0} {rsp_mux.sink4} {avalon_streaming};preview_set_connection_tag {rsp_demux_004.src0/rsp_mux.sink4} {qsys_mm.response};add_connection {rsp_demux_005.src0} {rsp_mux.sink5} {avalon_streaming};preview_set_connection_tag {rsp_demux_005.src0/rsp_mux.sink5} {qsys_mm.response};add_connection {rsp_demux_006.src0} {rsp_mux.sink6} {avalon_streaming};preview_set_connection_tag {rsp_demux_006.src0/rsp_mux.sink6} {qsys_mm.response};add_connection {rsp_demux_007.src0} {rsp_mux.sink7} {avalon_streaming};preview_set_connection_tag {rsp_demux_007.src0/rsp_mux.sink7} {qsys_mm.response};add_connection {rsp_demux_008.src0} {rsp_mux.sink8} {avalon_streaming};preview_set_connection_tag {rsp_demux_008.src0/rsp_mux.sink8} {qsys_mm.response};add_connection {rsp_demux_009.src0} {rsp_mux.sink9} {avalon_streaming};preview_set_connection_tag {rsp_demux_009.src0/rsp_mux.sink9} {qsys_mm.response};add_connection {rsp_demux_010.src0} {rsp_mux.sink10} {avalon_streaming};preview_set_connection_tag {rsp_demux_010.src0/rsp_mux.sink10} {qsys_mm.response};add_connection {rsp_demux_010.src1} {rsp_mux_001.sink2} {avalon_streaming};preview_set_connection_tag {rsp_demux_010.src1/rsp_mux_001.sink2} {qsys_mm.response};add_connection {rsp_demux_011.src0} {rsp_mux.sink11} {avalon_streaming};preview_set_connection_tag {rsp_demux_011.src0/rsp_mux.sink11} {qsys_mm.response};add_connection {rsp_demux_011.src1} {rsp_mux_001.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_011.src1/rsp_mux_001.sink3} {qsys_mm.response};add_connection {rsp_demux_012.src0} {rsp_mux.sink12} {avalon_streaming};preview_set_connection_tag {rsp_demux_012.src0/rsp_mux.sink12} {qsys_mm.response};add_connection {rsp_demux_013.src0} {rsp_mux.sink13} {avalon_streaming};preview_set_connection_tag {rsp_demux_013.src0/rsp_mux.sink13} {qsys_mm.response};add_connection {rsp_demux_014.src0} {rsp_mux.sink14} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src0/rsp_mux.sink14} {qsys_mm.response};add_connection {rsp_demux_014.src1} {rsp_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src1/rsp_mux_004.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src2} {rsp_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src2/rsp_mux_005.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src3} {rsp_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src3/rsp_mux_006.sink0} {qsys_mm.response};add_connection {rsp_demux_014.src4} {rsp_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src4/rsp_mux_007.sink0} {qsys_mm.response};add_connection {rsp_demux_015.src0} {rsp_mux.sink15} {avalon_streaming};preview_set_connection_tag {rsp_demux_015.src0/rsp_mux.sink15} {qsys_mm.response};add_connection {rsp_demux_016.src0} {rsp_mux.sink16} {avalon_streaming};preview_set_connection_tag {rsp_demux_016.src0/rsp_mux.sink16} {qsys_mm.response};add_connection {rsp_demux_017.src0} {rsp_mux.sink17} {avalon_streaming};preview_set_connection_tag {rsp_demux_017.src0/rsp_mux.sink17} {qsys_mm.response};add_connection {rsp_demux_018.src0} {rsp_mux.sink18} {avalon_streaming};preview_set_connection_tag {rsp_demux_018.src0/rsp_mux.sink18} {qsys_mm.response};add_connection {rsp_demux_019.src0} {rsp_mux.sink19} {avalon_streaming};preview_set_connection_tag {rsp_demux_019.src0/rsp_mux.sink19} {qsys_mm.response};add_connection {rsp_demux_020.src0} {rsp_mux.sink20} {avalon_streaming};preview_set_connection_tag {rsp_demux_020.src0/rsp_mux.sink20} {qsys_mm.response};add_connection {router_028.src} {calibration_ram_s1_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {router_028.src/calibration_ram_s1_rsp_width_adapter.sink} {qsys_mm.response};add_connection {calibration_ram_s1_rsp_width_adapter.src} {rsp_demux_020.sink} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_rsp_width_adapter.src/rsp_demux_020.sink} {qsys_mm.response};add_connection {cmd_mux_020.src} {calibration_ram_s1_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_mux_020.src/calibration_ram_s1_cmd_width_adapter.sink} {qsys_mm.command};add_connection {calibration_ram_s1_cmd_width_adapter.src} {calibration_ram_s1_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {calibration_ram_s1_cmd_width_adapter.src/calibration_ram_s1_burst_adapter.sink0} {qsys_mm.command};add_connection {cmd_demux.src0} {crosser.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/crosser.in} {qsys_mm.command};add_connection {crosser.out} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {crosser.out/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {crosser_001.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/crosser_001.in} {qsys_mm.command};add_connection {crosser_001.out} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {crosser_001.out/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux.src2} {crosser_002.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src2/crosser_002.in} {qsys_mm.command};add_connection {crosser_002.out} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {crosser_002.out/cmd_mux_002.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {crosser_003.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/crosser_003.in} {qsys_mm.command};add_connection {crosser_003.out} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {crosser_003.out/cmd_mux.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {crosser_004.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/crosser_004.in} {qsys_mm.command};add_connection {crosser_004.out} {cmd_mux_002.sink1} {avalon_streaming};preview_set_connection_tag {crosser_004.out/cmd_mux_002.sink1} {qsys_mm.command};add_connection {cmd_demux_002.src0} {crosser_005.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_002.src0/crosser_005.in} {qsys_mm.command};add_connection {crosser_005.out} {cmd_mux.sink2} {avalon_streaming};preview_set_connection_tag {crosser_005.out/cmd_mux.sink2} {qsys_mm.command};add_connection {cmd_demux_003.src0} {crosser_006.in} {avalon_streaming};preview_set_connection_tag {cmd_demux_003.src0/crosser_006.in} {qsys_mm.command};add_connection {crosser_006.out} {cmd_mux.sink3} {avalon_streaming};preview_set_connection_tag {crosser_006.out/cmd_mux.sink3} {qsys_mm.command};add_connection {rsp_demux.src0} {crosser_007.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/crosser_007.in} {qsys_mm.response};add_connection {crosser_007.out} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {crosser_007.out/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {crosser_008.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/crosser_008.in} {qsys_mm.response};add_connection {crosser_008.out} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {crosser_008.out/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux.src2} {crosser_009.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src2/crosser_009.in} {qsys_mm.response};add_connection {crosser_009.out} {rsp_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {crosser_009.out/rsp_mux_002.sink0} {qsys_mm.response};add_connection {rsp_demux.src3} {crosser_010.in} {avalon_streaming};preview_set_connection_tag {rsp_demux.src3/crosser_010.in} {qsys_mm.response};add_connection {crosser_010.out} {rsp_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {crosser_010.out/rsp_mux_003.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {crosser_011.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/crosser_011.in} {qsys_mm.response};add_connection {crosser_011.out} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {crosser_011.out/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {crosser_012.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/crosser_012.in} {qsys_mm.response};add_connection {crosser_012.out} {rsp_mux.sink2} {avalon_streaming};preview_set_connection_tag {crosser_012.out/rsp_mux.sink2} {qsys_mm.response};add_connection {rsp_demux_002.src1} {crosser_013.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src1/crosser_013.in} {qsys_mm.response};add_connection {crosser_013.out} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {crosser_013.out/rsp_mux_001.sink1} {qsys_mm.response};add_connection {cpu_data_master_limiter.cmd_valid} {cmd_demux.sink_valid} {avalon_streaming};add_connection {cpu_instruction_master_limiter.cmd_valid} {cmd_demux_001.sink_valid} {avalon_streaming};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_mm_read_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_mm_write_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_read_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_read_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_write_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_write_master_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_translator.reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_mm_read_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_mm_write_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_read_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_read_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_descriptor_write_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_descriptor_write_master_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {udp_generator_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {sensor_interface_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {onchip_flash_data_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_debug_mem_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {button_pio_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {debug_uart_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {frame_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_agent.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_014.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_015.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_016.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_021.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_025.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_026.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_027.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {router_028.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_data_master_limiter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cpu_instruction_master_limiter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_burst_adapter.cr0_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_010.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_011.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_012.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {cmd_mux_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_008.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_009.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_010.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_011.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_012.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_013.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_017.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_018.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_019.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_demux_020.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_002.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_003.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_004.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_005.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_006.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {rsp_mux_007.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_rsp_width_adapter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {calibration_ram_s1_cmd_width_adapter.clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_001.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_002.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_003.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_004.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_005.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_006.in_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_007.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_008.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_009.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_010.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_011.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_012.out_clk_reset} {reset};add_connection {cpu_reset_reset_bridge.out_reset} {crosser_013.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_translator.reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_translator.reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent_rsp_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_csr_agent_rdata_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent_rsp_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_agent_rdata_fifo.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {router_009.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {router_010.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {ext_flash_avl_mem_burst_adapter.cr0_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_001.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_002.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_004.out_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_011.in_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_012.in_clk_reset} {reset};add_connection {ext_flash_reset_reset_bridge.out_reset} {crosser_013.in_clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_translator.reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {eth_tse_control_port_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sysid_control_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {descriptor_memory_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {sys_clk_timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_agent.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {output_pio_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_011.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_012.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_022.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_023.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {router_024.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_003.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_004.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_014.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_015.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {cmd_mux_016.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_003.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_004.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_014.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_015.clk_reset} {reset};add_connection {eth_tse_reset_connection_reset_bridge.out_reset} {rsp_demux_016.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_translator.reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent_rsp_fifo.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {ddr3_ram_avl_agent_rdata_fifo.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {router_008.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_003.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_005.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_006.out_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_007.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_008.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_009.in_clk_reset} {reset};add_connection {ddr3_ram_avl_translator_reset_reset_bridge.out_reset} {crosser_010.in_clk_reset} {reset};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_mm_read_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_mm_write_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_read_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_read_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_write_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_write_master_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_translator.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_mm_read_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_mm_write_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_read_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_read_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_descriptor_write_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_descriptor_write_master_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_control_port_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sysid_control_slave_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {udp_generator_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sensor_interface_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {onchip_flash_data_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_debug_mem_slave_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_tx_prefetcher_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {msgdma_rx_prefetcher_csr_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {descriptor_memory_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {sys_clk_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {output_pio_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {button_pio_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {debug_uart_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {frame_timer_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_agent.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_agent_rsp_fifo.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_021.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_022.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_023.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_024.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_025.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_026.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_027.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {router_028.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_data_master_limiter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_instruction_master_limiter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_burst_adapter.cr0} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_002.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_demux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_mux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_003.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_004.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_005.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_006.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_007.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_008.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_008.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_009.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_009.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_010.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_010.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_011.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_012.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_013.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_014.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_015.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_016.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_017.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_018.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_019.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cmd_mux_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {rsp_demux_020.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_rsp_width_adapter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {calibration_ram_s1_cmd_width_adapter.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_001.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_002.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_003.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_004.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_005.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_006.in_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_007.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_008.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_009.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_010.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_011.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_012.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {crosser_013.out_clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {cpu_reset_reset_bridge.clk} {clock};add_connection {sys_clk_clk_clock_bridge.out_clk} {eth_tse_reset_connection_reset_bridge.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_translator.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent_rsp_fifo.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_agent_rdata_fifo.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {router_008.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_003.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_005.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_006.out_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_007.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_008.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_009.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {crosser_010.in_clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_soft_reset_reset_bridge.clk} {clock};add_connection {ddr3_ram_afi_clk_clock_bridge.out_clk} {ddr3_ram_avl_translator_reset_reset_bridge.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_translator.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_translator.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent_rsp_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_csr_agent_rdata_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent_rsp_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_agent_rdata_fifo.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {router_009.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {router_010.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_avl_mem_burst_adapter.cr0} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_001.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_002.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_004.out_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_011.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_012.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {crosser_013.in_clk} {clock};add_connection {ext_flash_clock_bridge_out_clk_clock_bridge.out_clk} {ext_flash_reset_reset_bridge.clk} {clock};add_interface {ddr3_ram_afi_clk} {clock} {slave};set_interface_property {ddr3_ram_afi_clk} {EXPORT_OF} {ddr3_ram_afi_clk_clock_bridge.in_clk};add_interface {ext_flash_clock_bridge_out_clk} {clock} {slave};set_interface_property {ext_flash_clock_bridge_out_clk} {EXPORT_OF} {ext_flash_clock_bridge_out_clk_clock_bridge.in_clk};add_interface {sys_clk_clk} {clock} {slave};set_interface_property {sys_clk_clk} {EXPORT_OF} {sys_clk_clk_clock_bridge.in_clk};add_interface {cpu_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {cpu_reset_reset_bridge_in_reset} {EXPORT_OF} {cpu_reset_reset_bridge.in_reset};add_interface {ddr3_ram_avl_translator_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ddr3_ram_avl_translator_reset_reset_bridge_in_reset} {EXPORT_OF} {ddr3_ram_avl_translator_reset_reset_bridge.in_reset};add_interface {ddr3_ram_soft_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ddr3_ram_soft_reset_reset_bridge_in_reset} {EXPORT_OF} {ddr3_ram_soft_reset_reset_bridge.in_reset};add_interface {eth_tse_reset_connection_reset_bridge_in_reset} {reset} {slave};set_interface_property {eth_tse_reset_connection_reset_bridge_in_reset} {EXPORT_OF} {eth_tse_reset_connection_reset_bridge.in_reset};add_interface {ext_flash_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {ext_flash_reset_reset_bridge_in_reset} {EXPORT_OF} {ext_flash_reset_reset_bridge.in_reset};add_interface {cpu_data_master} {avalon} {slave};set_interface_property {cpu_data_master} {EXPORT_OF} {cpu_data_master_translator.avalon_anti_master_0};add_interface {cpu_instruction_master} {avalon} {slave};set_interface_property {cpu_instruction_master} {EXPORT_OF} {cpu_instruction_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_descriptor_read_master} {avalon} {slave};set_interface_property {msgdma_rx_descriptor_read_master} {EXPORT_OF} {msgdma_rx_descriptor_read_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_descriptor_write_master} {avalon} {slave};set_interface_property {msgdma_rx_descriptor_write_master} {EXPORT_OF} {msgdma_rx_descriptor_write_master_translator.avalon_anti_master_0};add_interface {msgdma_rx_mm_write} {avalon} {slave};set_interface_property {msgdma_rx_mm_write} {EXPORT_OF} {msgdma_rx_mm_write_translator.avalon_anti_master_0};add_interface {msgdma_tx_descriptor_read_master} {avalon} {slave};set_interface_property {msgdma_tx_descriptor_read_master} {EXPORT_OF} {msgdma_tx_descriptor_read_master_translator.avalon_anti_master_0};add_interface {msgdma_tx_descriptor_write_master} {avalon} {slave};set_interface_property {msgdma_tx_descriptor_write_master} {EXPORT_OF} {msgdma_tx_descriptor_write_master_translator.avalon_anti_master_0};add_interface {msgdma_tx_mm_read} {avalon} {slave};set_interface_property {msgdma_tx_mm_read} {EXPORT_OF} {msgdma_tx_mm_read_translator.avalon_anti_master_0};add_interface {button_pio_s1} {avalon} {master};set_interface_property {button_pio_s1} {EXPORT_OF} {button_pio_s1_translator.avalon_anti_slave_0};add_interface {calibration_ram_s1} {avalon} {master};set_interface_property {calibration_ram_s1} {EXPORT_OF} {calibration_ram_s1_translator.avalon_anti_slave_0};add_interface {cpu_debug_mem_slave} {avalon} {master};set_interface_property {cpu_debug_mem_slave} {EXPORT_OF} {cpu_debug_mem_slave_translator.avalon_anti_slave_0};add_interface {ddr3_ram_avl} {avalon} {master};set_interface_property {ddr3_ram_avl} {EXPORT_OF} {ddr3_ram_avl_translator.avalon_anti_slave_0};add_interface {debug_uart_s1} {avalon} {master};set_interface_property {debug_uart_s1} {EXPORT_OF} {debug_uart_s1_translator.avalon_anti_slave_0};add_interface {descriptor_memory_s1} {avalon} {master};set_interface_property {descriptor_memory_s1} {EXPORT_OF} {descriptor_memory_s1_translator.avalon_anti_slave_0};add_interface {eth_tse_control_port} {avalon} {master};set_interface_property {eth_tse_control_port} {EXPORT_OF} {eth_tse_control_port_translator.avalon_anti_slave_0};add_interface {ext_flash_avl_csr} {avalon} {master};set_interface_property {ext_flash_avl_csr} {EXPORT_OF} {ext_flash_avl_csr_translator.avalon_anti_slave_0};add_interface {ext_flash_avl_mem} {avalon} {master};set_interface_property {ext_flash_avl_mem} {EXPORT_OF} {ext_flash_avl_mem_translator.avalon_anti_slave_0};add_interface {frame_timer_s1} {avalon} {master};set_interface_property {frame_timer_s1} {EXPORT_OF} {frame_timer_s1_translator.avalon_anti_slave_0};add_interface {msgdma_rx_csr} {avalon} {master};set_interface_property {msgdma_rx_csr} {EXPORT_OF} {msgdma_rx_csr_translator.avalon_anti_slave_0};add_interface {msgdma_rx_prefetcher_csr} {avalon} {master};set_interface_property {msgdma_rx_prefetcher_csr} {EXPORT_OF} {msgdma_rx_prefetcher_csr_translator.avalon_anti_slave_0};add_interface {msgdma_tx_csr} {avalon} {master};set_interface_property {msgdma_tx_csr} {EXPORT_OF} {msgdma_tx_csr_translator.avalon_anti_slave_0};add_interface {msgdma_tx_prefetcher_csr} {avalon} {master};set_interface_property {msgdma_tx_prefetcher_csr} {EXPORT_OF} {msgdma_tx_prefetcher_csr_translator.avalon_anti_slave_0};add_interface {onchip_flash_csr} {avalon} {master};set_interface_property {onchip_flash_csr} {EXPORT_OF} {onchip_flash_csr_translator.avalon_anti_slave_0};add_interface {onchip_flash_data} {avalon} {master};set_interface_property {onchip_flash_data} {EXPORT_OF} {onchip_flash_data_translator.avalon_anti_slave_0};add_interface {output_pio_s1} {avalon} {master};set_interface_property {output_pio_s1} {EXPORT_OF} {output_pio_s1_translator.avalon_anti_slave_0};add_interface {sensor_interface_csr} {avalon} {master};set_interface_property {sensor_interface_csr} {EXPORT_OF} {sensor_interface_csr_translator.avalon_anti_slave_0};add_interface {sys_clk_timer_s1} {avalon} {master};set_interface_property {sys_clk_timer_s1} {EXPORT_OF} {sys_clk_timer_s1_translator.avalon_anti_slave_0};add_interface {sysid_control_slave} {avalon} {master};set_interface_property {sysid_control_slave} {EXPORT_OF} {sysid_control_slave_translator.avalon_anti_slave_0};add_interface {udp_generator_csr} {avalon} {master};set_interface_property {udp_generator_csr} {EXPORT_OF} {udp_generator_csr_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.button_pio.s1} {0};set_module_assignment {interconnect_id.calibration_ram.s1} {1};set_module_assignment {interconnect_id.cpu.data_master} {0};set_module_assignment {interconnect_id.cpu.debug_mem_slave} {2};set_module_assignment {interconnect_id.cpu.instruction_master} {1};set_module_assignment {interconnect_id.ddr3_ram.avl} {3};set_module_assignment {interconnect_id.debug_uart.s1} {4};set_module_assignment {interconnect_id.descriptor_memory.s1} {5};set_module_assignment {interconnect_id.eth_tse.control_port} {6};set_module_assignment {interconnect_id.ext_flash.avl_csr} {7};set_module_assignment {interconnect_id.ext_flash.avl_mem} {8};set_module_assignment {interconnect_id.frame_timer.s1} {9};set_module_assignment {interconnect_id.msgdma_rx.csr} {10};set_module_assignment {interconnect_id.msgdma_rx.descriptor_read_master} {2};set_module_assignment {interconnect_id.msgdma_rx.descriptor_write_master} {3};set_module_assignment {interconnect_id.msgdma_rx.mm_write} {4};set_module_assignment {interconnect_id.msgdma_rx.prefetcher_csr} {11};set_module_assignment {interconnect_id.msgdma_tx.csr} {12};set_module_assignment {interconnect_id.msgdma_tx.descriptor_read_master} {5};set_module_assignment {interconnect_id.msgdma_tx.descriptor_write_master} {6};set_module_assignment {interconnect_id.msgdma_tx.mm_read} {7};set_module_assignment {interconnect_id.msgdma_tx.prefetcher_csr} {13};set_module_assignment {interconnect_id.onchip_flash.csr} {14};set_module_assignment {interconnect_id.onchip_flash.data} {15};set_module_assignment {interconnect_id.output_pio.s1} {16};set_module_assignment {interconnect_id.sensor_interface.csr} {17};set_module_assignment {interconnect_id.sys_clk_timer.s1} {18};set_module_assignment {interconnect_id.sysid.control_slave} {19};set_module_assignment {interconnect_id.udp_generator.csr} {20};" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_001.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_002.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_004.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_008.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_009.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_010.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_022.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_028.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_traffic_limiter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_reorder_memory.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_new.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_incr_burst_converter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_wrap_burst_converter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_default_burst_converter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_001.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_002.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_001.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_002.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_014.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_001.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_002.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_010.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_014.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_001.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_002.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_width_adapter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_clock_crosser.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc"
|
|
type="SDC"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter.v"
|
|
type="VERILOG" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020.v"
|
|
type="VERILOG" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys" as="mm_interconnect_1" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 33 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_1"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InitialInterconnectTransform</message>
|
|
<message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
|
|
<message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
|
|
<message level="Debug">Transform: DefaultSlaveTransform</message>
|
|
<message level="Debug">Transform: TranslatorTransform</message>
|
|
<message level="Debug">No Avalon connections, skipping transform </message>
|
|
<message level="Debug">Transform: IDPadTransform</message>
|
|
<message level="Debug">Transform: DomainTransform</message>
|
|
<message level="Debug">Transform: RouterTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterTransform</message>
|
|
<message level="Debug">Transform: BurstTransform</message>
|
|
<message level="Debug">Transform: TreeTransform</message>
|
|
<message level="Debug">Transform: NetworkToSwitchTransform</message>
|
|
<message level="Debug">Transform: WidthTransform</message>
|
|
<message level="Debug">Transform: RouterTableTransform</message>
|
|
<message level="Debug">Transform: ThreadIDMappingTableTransform</message>
|
|
<message level="Debug">Transform: ClockCrossingTransform</message>
|
|
<message level="Debug">Transform: PipelineTransform</message>
|
|
<message level="Debug">Transform: SpotPipelineTransform</message>
|
|
<message level="Debug">Transform: PerformanceMonitorTransform</message>
|
|
<message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
|
|
<message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
|
|
<message level="Debug">Transform: InterconnectConnectionsTagger</message>
|
|
<message level="Debug">Transform: HierarchyTransform</message>
|
|
<message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>197</b> modules, <b>679</b> connections]]></message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.007s/0.008s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_001">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.006s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_002">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_002.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_002.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_002.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_002">Timing: COM:3/0.005s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_003">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_003.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_003.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_003.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_003">Timing: COM:3/0.007s/0.009s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_004">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_004.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_004.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
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<message level="Debug" culprit="avalon_st_adapter_004.error_adapter_0">Timing: ELA:1/0.003s</message>
|
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<message level="Debug" culprit="avalon_st_adapter_004">Timing: COM:3/0.005s/0.006s</message>
|
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<message level="Progress" culprit="min"></message>
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|
<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
|
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<message level="Info" culprit="avalon_st_adapter_005">Inserting error_adapter: error_adapter_0</message>
|
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<message level="Debug" culprit="avalon_st_adapter_005.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_005.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_005.error_adapter_0">Timing: ELA:1/0.003s</message>
|
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<message level="Debug" culprit="avalon_st_adapter_005">Timing: COM:3/0.005s/0.006s</message>
|
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
|
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<message level="Progress" culprit="current"></message>
|
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<message level="Info" culprit="avalon_st_adapter_006">Inserting error_adapter: error_adapter_0</message>
|
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<message level="Debug" culprit="avalon_st_adapter_006.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
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<message level="Debug" culprit="avalon_st_adapter_006.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_006.error_adapter_0">Timing: ELA:1/0.003s</message>
|
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<message level="Debug" culprit="avalon_st_adapter_006">Timing: COM:3/0.006s/0.007s</message>
|
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
|
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<message level="Progress" culprit="current"></message>
|
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<message level="Info" culprit="avalon_st_adapter_007">Inserting error_adapter: error_adapter_0</message>
|
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<message level="Debug" culprit="avalon_st_adapter_007.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_007.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_007.error_adapter_0">Timing: ELA:1/0.004s</message>
|
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<message level="Debug" culprit="avalon_st_adapter_007">Timing: COM:3/0.006s/0.007s</message>
|
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<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
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<message level="Progress" culprit="current"></message>
|
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<message level="Info" culprit="avalon_st_adapter_008">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_008.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_008.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_008.error_adapter_0">Timing: ELA:1/0.003s</message>
|
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<message level="Debug" culprit="avalon_st_adapter_008">Timing: COM:3/0.006s/0.006s</message>
|
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<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
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<message level="Progress" culprit="current"></message>
|
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<message level="Info" culprit="avalon_st_adapter_009">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_009.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_009.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_009.error_adapter_0">Timing: ELA:1/0.004s</message>
|
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<message level="Debug" culprit="avalon_st_adapter_009">Timing: COM:3/0.006s/0.007s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_010">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_010.clk_bridge_0">Timing: ELA:1/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_010.rst_bridge_0">Timing: ELA:2/0.001s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_010.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_010">Timing: COM:3/0.020s/0.048s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_011">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_011.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_011.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_011.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_011">Timing: COM:3/0.005s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_012">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_012.clk_bridge_0">Timing: ELA:1/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_012.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_012.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_012">Timing: COM:3/0.006s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_013">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_013.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_013.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_013.error_adapter_0">Timing: ELA:1/0.004s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_013">Timing: COM:3/0.006s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_014">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_014.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_014.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_014.error_adapter_0">Timing: ELA:1/0.002s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_014">Timing: COM:3/0.006s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_015">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_015.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_015.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_015.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_015">Timing: COM:3/0.005s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_016">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_016.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_016.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_016.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_016">Timing: COM:3/0.006s/0.007s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_017">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_017.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_017.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_017.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_017">Timing: COM:3/0.006s/0.007s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_018">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_018.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_018.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_018.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_018">Timing: COM:3/0.006s/0.007s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_019">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_019.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_019.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_019.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_019">Timing: COM:3/0.006s/0.006s</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Info" culprit="avalon_st_adapter_020">Inserting error_adapter: error_adapter_0</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_020.clk_bridge_0">Timing: ELA:1/0.000s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_020.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_020.error_adapter_0">Timing: ELA:1/0.003s</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_020">Timing: COM:3/0.006s/0.006s</message>
|
|
<message
|
|
level="Debug"
|
|
culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>218</b> modules, <b>742</b> connections]]></message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_004</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_008</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_010</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_022</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_009</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_router</b> "<b>submodules/q_sys_mm_interconnect_1_router_028</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_014</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_mux_001</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux</b>"]]></message>
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<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_001</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_010</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_010</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_demux_014</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_cmd_demux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_001</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/q_sys_mm_interconnect_1_rsp_mux_002</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
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|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_handshake_clock_crosser</b> "<b>submodules/altera_avalon_st_handshake_clock_crosser</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="mm_interconnect_1"><![CDATA["<b>mm_interconnect_1</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020</b>"]]></message>
|
|
<message level="Info" culprit="mm_interconnect_1"><![CDATA["<b>q_sys</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
|
|
<message
|
|
level="Info"
|
|
culprit="sensor_interface_calibration_ram_interface_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>sensor_interface_calibration_ram_interface_translator</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
|
|
<message level="Info" culprit="calibration_ram_s2_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>calibration_ram_s2_translator</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 187 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
|
|
<message level="Info" culprit="cpu_data_master_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>cpu_data_master_agent</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 179 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
|
|
<message level="Info" culprit="ddr3_ram_avl_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>ddr3_ram_avl_agent</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 178 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
|
|
<message level="Info" culprit="ddr3_ram_avl_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>ddr3_ram_avl_agent_rsp_fifo</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 134 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router"</message>
|
|
<message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 133 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_001"</message>
|
|
<message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 132 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002"</message>
|
|
<message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 130 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"</message>
|
|
<message level="Info" culprit="router_004"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_004</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 126 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_008"</message>
|
|
<message level="Info" culprit="router_008"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_008</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 125 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"</message>
|
|
<message level="Info" culprit="router_009"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_009</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 124 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"</message>
|
|
<message level="Info" culprit="router_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_010</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 112 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_022"</message>
|
|
<message level="Info" culprit="router_022"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_022</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 106 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_028"</message>
|
|
<message level="Info" culprit="router_028"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_028</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 105 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"</message>
|
|
<message level="Info" culprit="cpu_data_master_limiter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>cpu_data_master_limiter</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 103 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
|
|
<message level="Info" culprit="ext_flash_avl_mem_burst_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>ext_flash_avl_mem_burst_adapter</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 101 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux"</message>
|
|
<message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 100 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_001"</message>
|
|
<message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 99 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"</message>
|
|
<message level="Info" culprit="cmd_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_002</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 93 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux"</message>
|
|
<message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 92 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"</message>
|
|
<message level="Info" culprit="cmd_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_001</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 91 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"</message>
|
|
<message level="Info" culprit="cmd_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_002</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 79 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_014"</message>
|
|
<message level="Info" culprit="cmd_mux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_014</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 72 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux"</message>
|
|
<message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 71 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_001"</message>
|
|
<message level="Info" culprit="rsp_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_001</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 70 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_002"</message>
|
|
<message level="Info" culprit="rsp_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_002</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 62 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010"</message>
|
|
<message level="Info" culprit="rsp_demux_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_010</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 58 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_014"</message>
|
|
<message level="Info" culprit="rsp_demux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_014</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 51 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux"</message>
|
|
<message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 50 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_001"</message>
|
|
<message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 49 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"</message>
|
|
<message level="Info" culprit="rsp_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_002</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 43 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
|
|
<message level="Info" culprit="calibration_ram_s1_rsp_width_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>calibration_ram_s1_rsp_width_adapter</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 41 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"</message>
|
|
<message level="Info" culprit="crosser"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_handshake_clock_crosser</b> "<b>crosser</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v</b>]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 27 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0</b>"]]></message>
|
|
<message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"</message>
|
|
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 8 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_020"><![CDATA["<b>avalon_st_adapter_020</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0</b>"]]></message>
|
|
<message level="Info" culprit="avalon_st_adapter_020"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_020</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0"</message>
|
|
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_020</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_irq_mapper:19.1:AUTO_DEVICE_FAMILY=MAX 10,IRQ_MAP=0:2,1:3,2:5,3:0,4:4,NUM_RCVRS=5,SENDER_IRQ_WIDTH=32"
|
|
instancePathKey="q_sys:.:irq_mapper"
|
|
kind="altera_irq_mapper"
|
|
version="19.1"
|
|
name="q_sys_irq_mapper">
|
|
<parameter name="NUM_RCVRS" value="5" />
|
|
<parameter name="IRQ_MAP" value="0:2,1:3,2:5,3:0,4:4" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="SENDER_IRQ_WIDTH" value="32" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_irq_mapper.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="irq_mapper" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 242 starting:altera_irq_mapper "submodules/q_sys_irq_mapper"</message>
|
|
<message level="Info" culprit="irq_mapper"><![CDATA["<b>q_sys</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_irq_clock_crosser:19.1:AUTO_RECEIVER_INTERRUPTS_USED=-1,IRQ_WIDTH=1"
|
|
instancePathKey="q_sys:.:irq_synchronizer"
|
|
kind="altera_irq_clock_crosser"
|
|
version="19.1"
|
|
name="altera_irq_clock_crosser">
|
|
<parameter name="IRQ_WIDTH" value="1" />
|
|
<parameter name="AUTO_RECEIVER_INTERRUPTS_USED" value="-1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_irq_clock_crosser.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_irq_clock_crosser/altera_irq_clock_crosser_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys" as="irq_synchronizer" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 241 starting:altera_irq_clock_crosser "submodules/altera_irq_clock_crosser"</message>
|
|
<message level="Info" culprit="irq_synchronizer"><![CDATA["<b>q_sys</b>" instantiated <b>altera_irq_clock_crosser</b> "<b>irq_synchronizer</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_st_adapter:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,inBitsPerSymbol=8,inChannelWidth=0,inDataWidth=32,inEmptyWidth=2,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inUseEmptyPort=1,inUsePackets=1,inUseReady=1,inUseValid=1,outChannelWidth=0,outDataWidth=32,outEmptyWidth=2,outErrorDescriptor=,outErrorWidth=1,outMaxChannel=0,outReadyLatency=0,outUseEmptyPort=1,outUseReady=1,outUseValid=1(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(error_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,outErrorDescriptor=,outErrorWidth=1)(clock:19.1:)(clock:19.1:)(reset:19.1:)"
|
|
instancePathKey="q_sys:.:avalon_st_adapter"
|
|
kind="altera_avalon_st_adapter"
|
|
version="19.1"
|
|
name="q_sys_avalon_st_adapter">
|
|
<parameter name="inUseValid" value="1" />
|
|
<parameter name="inBitsPerSymbol" value="8" />
|
|
<parameter name="outUseEmptyPort" value="1" />
|
|
<parameter name="inChannelWidth" value="0" />
|
|
<parameter name="outErrorWidth" value="1" />
|
|
<parameter name="outUseValid" value="1" />
|
|
<parameter name="outMaxChannel" value="0" />
|
|
<parameter name="inErrorDescriptor" value="" />
|
|
<parameter name="inUsePackets" value="1" />
|
|
<parameter name="inErrorWidth" value="0" />
|
|
<parameter name="inEmptyWidth" value="2" />
|
|
<parameter name="inUseReady" value="1" />
|
|
<parameter name="outReadyLatency" value="0" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="outDataWidth" value="32" />
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
|
|
<parameter name="inUseEmptyPort" value="1" />
|
|
<parameter name="outChannelWidth" value="0" />
|
|
<parameter name="inMaxChannel" value="0" />
|
|
<parameter name="outUseReady" value="1" />
|
|
<parameter name="inReadyLatency" value="0" />
|
|
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
|
|
<parameter name="inDataWidth" value="32" />
|
|
<parameter name="outErrorDescriptor" value="" />
|
|
<parameter name="outEmptyWidth" value="2" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_error_adapter_0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys" as="avalon_st_adapter" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_avalon_st_adapter_error_adapter_0</b>"]]></message>
|
|
<message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 8 starting:error_adapter "submodules/q_sys_avalon_st_adapter_error_adapter_0"</message>
|
|
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_st_adapter:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,inBitsPerSymbol=8,inChannelWidth=0,inDataWidth=32,inEmptyWidth=2,inErrorDescriptor=,inErrorWidth=6,inMaxChannel=0,inReadyLatency=2,inUseEmptyPort=1,inUsePackets=1,inUseReady=1,inUseValid=1,outChannelWidth=0,outDataWidth=32,outEmptyWidth=2,outErrorDescriptor=,outErrorWidth=6,outMaxChannel=0,outReadyLatency=0,outUseEmptyPort=1,outUseReady=1,outUseValid=1(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(timing_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=6,inMaxChannel=0,inReadyLatency=2,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,inUseValid=true,outReadyLatency=0,outUseReady=true,outUseValid=true)(clock:19.1:)(clock:19.1:)(reset:19.1:)"
|
|
instancePathKey="q_sys:.:avalon_st_adapter_001"
|
|
kind="altera_avalon_st_adapter"
|
|
version="19.1"
|
|
name="q_sys_avalon_st_adapter_001">
|
|
<parameter name="inUseValid" value="1" />
|
|
<parameter name="inBitsPerSymbol" value="8" />
|
|
<parameter name="outUseEmptyPort" value="1" />
|
|
<parameter name="inChannelWidth" value="0" />
|
|
<parameter name="outErrorWidth" value="6" />
|
|
<parameter name="outUseValid" value="1" />
|
|
<parameter name="outMaxChannel" value="0" />
|
|
<parameter name="inErrorDescriptor" value="" />
|
|
<parameter name="inUsePackets" value="1" />
|
|
<parameter name="inErrorWidth" value="6" />
|
|
<parameter name="inEmptyWidth" value="2" />
|
|
<parameter name="inUseReady" value="1" />
|
|
<parameter name="outReadyLatency" value="0" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="outDataWidth" value="32" />
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
|
|
<parameter name="inUseEmptyPort" value="1" />
|
|
<parameter name="outChannelWidth" value="0" />
|
|
<parameter name="inMaxChannel" value="0" />
|
|
<parameter name="outUseReady" value="1" />
|
|
<parameter name="inReadyLatency" value="2" />
|
|
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
|
|
<parameter name="inDataWidth" value="32" />
|
|
<parameter name="outErrorDescriptor" value="" />
|
|
<parameter name="outEmptyWidth" value="2" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys" as="avalon_st_adapter_001" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter_001"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_001"><![CDATA["<b>avalon_st_adapter_001</b>" reuses <b>timing_adapter</b> "<b>submodules/q_sys_avalon_st_adapter_001_timing_adapter_0</b>"]]></message>
|
|
<message level="Info" culprit="avalon_st_adapter_001"><![CDATA["<b>q_sys</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_001</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 7 starting:timing_adapter "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0"</message>
|
|
<message level="Info" culprit="timing_adapter_0"><![CDATA["<b>avalon_st_adapter_001</b>" instantiated <b>timing_adapter</b> "<b>timing_adapter_0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_reset_controller:19.1:ADAPT_RESET_REQUEST=0,MIN_RST_ASSERTION_TIME=3,NUM_RESET_INPUTS=1,OUTPUT_RESET_SYNC_EDGES=deassert,RESET_REQUEST_PRESENT=0,RESET_REQ_EARLY_DSRT_TIME=1,RESET_REQ_WAIT_TIME=1,SYNC_DEPTH=2,USE_RESET_REQUEST_IN0=0,USE_RESET_REQUEST_IN1=0,USE_RESET_REQUEST_IN10=0,USE_RESET_REQUEST_IN11=0,USE_RESET_REQUEST_IN12=0,USE_RESET_REQUEST_IN13=0,USE_RESET_REQUEST_IN14=0,USE_RESET_REQUEST_IN15=0,USE_RESET_REQUEST_IN2=0,USE_RESET_REQUEST_IN3=0,USE_RESET_REQUEST_IN4=0,USE_RESET_REQUEST_IN5=0,USE_RESET_REQUEST_IN6=0,USE_RESET_REQUEST_IN7=0,USE_RESET_REQUEST_IN8=0,USE_RESET_REQUEST_IN9=0,USE_RESET_REQUEST_INPUT=0"
|
|
instancePathKey="q_sys:.:rst_controller"
|
|
kind="altera_reset_controller"
|
|
version="19.1"
|
|
name="altera_reset_controller">
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_reset_controller.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_reset_synchronizer.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_reset_controller.sdc"
|
|
type="SDC"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys"
|
|
as="rst_controller,rst_controller_001,rst_controller_002,rst_controller_003,rst_controller_004,rst_controller_005,rst_controller_006" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 240 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
|
|
<message level="Info" culprit="rst_controller"><![CDATA["<b>q_sys</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_nios2_gen2_unit:19.1:bht_ramBlockType=Automatic,breakAbsoluteAddr=406857760,breakOffset=32,breakSlave=cpu.jtag_debug_module,breakSlave_derived=cpu.debug_mem_slave,cdx_enabled=false,clockFrequency=50000000,cpuArchRev=1,cpuID=0,cpuReset=false,cpu_name=cpu,customInstSlavesSystemInfo=<info/>,dataAddrWidth=29,dataMasterHighPerformanceAddrWidth=1,dataMasterHighPerformanceMapParam=,dataSlaveMapParam=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='calibration_ram.s1' start='0x18403400' end='0x18403680' type='altera_avalon_onchip_memory2.s1' /><slave name='frame_timer.s1' start='0x18403C00' end='0x18403C20' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403C20' end='0x18403C40' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403C40' end='0x18403C60' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403C60' end='0x18403C80' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403C80' end='0x18403CA0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x18403CA0' end='0x18403CC0' type='altera_msgdma.prefetcher_csr' /><slave name='udp_generator.csr' start='0x18403CC0' end='0x18403CE0' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403CE0' end='0x18403D00' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403D00' end='0x18403D20' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403D20' end='0x18403D40' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403D40' end='0x18403D50' type='altera_avalon_pio.s1' /><slave name='sensor_interface.csr' start='0x18403D50' end='0x18403D60' type='sensor_recon.csr' /><slave name='onchip_flash.csr' start='0x18403D60' end='0x18403D68' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403D68' end='0x18403D70' type='altera_avalon_sysid_qsys.control_slave' /></address-map>,data_master_high_performance_paddr_base=0,data_master_high_performance_paddr_top=0,data_master_paddr_base=0,data_master_paddr_top=0,dcache_bursts=false,dcache_bursts_derived=false,dcache_lineSize_derived=32,dcache_numTCDM=0,dcache_ramBlockType=Automatic,dcache_size=2048,dcache_size_derived=2048,dcache_tagramBlockType=Automatic,dcache_victim_buf_impl=ram,debug_OCIOnchipTrace=_128,debug_assignJtagInstanceID=false,debug_datatrace=false,debug_datatrigger=0,debug_debugReqSignals=false,debug_enabled=true,debug_hwbreakpoint=2,debug_insttrace=false,debug_jtagInstanceID=0,debug_offchiptrace=false,debug_onchiptrace=false,debug_traceStorage=onchip_trace,debug_traceType=none,debug_triggerArming=true,deviceFamilyName=MAX 10,deviceFeaturesSystemInfo=ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1,dividerType=no_div,exceptionAbsoluteAddr=134218016,exceptionOffset=288,exceptionSlave=ddr3_ram.avl,faAddrWidth=1,faSlaveMapParam=,fa_cache_line=2,fa_cache_linesize=0,flash_instruction_master_paddr_base=0,flash_instruction_master_paddr_top=0,icache_burstType=None,icache_numTCIM=0,icache_ramBlockType=Automatic,icache_size=2048,icache_tagramBlockType=Automatic,impl=Fast,instAddrWidth=29,instSlaveMapParam=<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>,instructionMasterHighPerformanceAddrWidth=1,instructionMasterHighPerformanceMapParam=,instruction_master_high_performance_paddr_base=0,instruction_master_high_performance_paddr_top=0,instruction_master_paddr_base=0,instruction_master_paddr_top=0,internalIrqMaskSystemInfo=61,io_regionbase=0,io_regionsize=0,master_addr_map=false,mmu_TLBMissExcAbsAddr=0,mmu_TLBMissExcOffset=0,mmu_TLBMissExcSlave=,mmu_autoAssignTlbPtrSz=true,mmu_enabled=false,mmu_processIDNumBits=8,mmu_ramBlockType=Automatic,mmu_tlbNumWays=16,mmu_tlbPtrSz=7,mmu_udtlbNumEntries=6,mmu_uitlbNumEntries=4,mpu_enabled=false,mpu_minDataRegionSize=12,mpu_minInstRegionSize=12,mpu_numOfDataRegion=8,mpu_numOfInstRegion=8,mpu_useLimit=false,mpx_enabled=false,multiplierType=mul_fast32,ocimem_ramBlockType=Automatic,ocimem_ramInit=false,regfile_ramBlockType=Automatic,register_file_por=false,resetAbsoluteAddr=335544320,resetOffset=0,resetSlave=ext_flash.avl_mem,resetrequest_enabled=true,setting_HBreakTest=false,setting_HDLSimCachesCleared=true,setting_activateMonitors=true,setting_activateTestEndChecker=false,setting_activateTrace=true,setting_allow_break_inst=false,setting_alwaysEncrypt=true,setting_asic_add_scan_mode_input=false,setting_asic_enabled=false,setting_asic_synopsys_translate_on_off=false,setting_asic_third_party_synthesis=false,setting_avalonDebugPortPresent=false,setting_bhtPtrSz=8,setting_bigEndian=false,setting_bit31BypassDCache=true,setting_branchPredictionType=Dynamic,setting_breakslaveoveride=false,setting_clearXBitsLDNonBypass=true,setting_dc_ecc_present=false,setting_disableocitrace=false,setting_dtcm_ecc_present=false,setting_ecc_present=false,setting_ecc_sim_test_ports=false,setting_exportPCB=false,setting_export_large_RAMs=false,setting_exportdebuginfo=false,setting_exportvectors=false,setting_fast_register_read=false,setting_ic_ecc_present=true,setting_interruptControllerType=Internal,setting_ioregionBypassDCache=false,setting_itcm_ecc_present=false,setting_mmu_ecc_present=true,setting_oci_export_jtag_signals=false,setting_oci_version=1,setting_preciseIllegalMemAccessException=false,setting_removeRAMinit=false,setting_rf_ecc_present=true,setting_shadowRegisterSets=0,setting_showInternalSettings=false,setting_showUnpublishedSettings=false,setting_support31bitdcachebypass=true,setting_usedesignware=false,shifterType=fast_le_shift,stratix_dspblock_shift_mul=false,tightlyCoupledDataMaster0AddrWidth=1,tightlyCoupledDataMaster0MapParam=,tightlyCoupledDataMaster1AddrWidth=1,tightlyCoupledDataMaster1MapParam=,tightlyCoupledDataMaster2AddrWidth=1,tightlyCoupledDataMaster2MapParam=,tightlyCoupledDataMaster3AddrWidth=1,tightlyCoupledDataMaster3MapParam=,tightlyCoupledInstructionMaster0AddrWidth=1,tightlyCoupledInstructionMaster0MapParam=,tightlyCoupledInstructionMaster1AddrWidth=1,tightlyCoupledInstructionMaster1MapParam=,tightlyCoupledInstructionMaster2AddrWidth=1,tightlyCoupledInstructionMaster2MapParam=,tightlyCoupledInstructionMaster3AddrWidth=1,tightlyCoupledInstructionMaster3MapParam=,tightly_coupled_data_master_0_paddr_base=0,tightly_coupled_data_master_0_paddr_top=0,tightly_coupled_data_master_1_paddr_base=0,tightly_coupled_data_master_1_paddr_top=0,tightly_coupled_data_master_2_paddr_base=0,tightly_coupled_data_master_2_paddr_top=0,tightly_coupled_data_master_3_paddr_base=0,tightly_coupled_data_master_3_paddr_top=0,tightly_coupled_instruction_master_0_paddr_base=0,tightly_coupled_instruction_master_0_paddr_top=0,tightly_coupled_instruction_master_1_paddr_base=0,tightly_coupled_instruction_master_1_paddr_top=0,tightly_coupled_instruction_master_2_paddr_base=0,tightly_coupled_instruction_master_2_paddr_top=0,tightly_coupled_instruction_master_3_paddr_base=0,tightly_coupled_instruction_master_3_paddr_top=0,tmr_enabled=false,tracefilename=,translate_off= "synthesis translate_off" ,translate_on= "synthesis translate_on" ,userDefinedSettings="
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instancePathKey="q_sys:.:cpu:.:cpu"
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kind="altera_nios2_gen2_unit"
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version="19.1"
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name="q_sys_cpu_cpu">
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<parameter name="icache_burstType" value="None" />
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<parameter name="setting_oci_version" value="1" />
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<parameter name="mpx_enabled" value="false" />
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<parameter name="ocimem_ramBlockType" value="Automatic" />
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<parameter name="dcache_victim_buf_impl" value="ram" />
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<parameter name="setting_exportPCB" value="false" />
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<parameter name="setting_ic_ecc_present" value="true" />
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<parameter name="dcache_size_derived" value="2048" />
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<parameter name="mmu_udtlbNumEntries" value="6" />
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<parameter name="tightly_coupled_instruction_master_3_paddr_top" value="0" />
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<parameter
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name="deviceFeaturesSystemInfo"
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value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" />
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<parameter name="bht_ramBlockType" value="Automatic" />
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<parameter name="instruction_master_high_performance_paddr_base" value="0" />
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<parameter name="mmu_TLBMissExcSlave" value="" />
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|
<parameter name="impl" value="Fast" />
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|
<parameter name="regfile_ramBlockType" value="Automatic" />
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|
<parameter name="dcache_size" value="2048" />
|
|
<parameter name="tightly_coupled_data_master_0_paddr_top" value="0" />
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<parameter name="breakOffset" value="32" />
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|
<parameter name="breakSlave" value="cpu.jtag_debug_module" />
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<parameter name="setting_branchPredictionType" value="Dynamic" />
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<parameter name="exceptionOffset" value="288" />
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<parameter name="flash_instruction_master_paddr_top" value="0" />
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<parameter name="tightlyCoupledDataMaster0MapParam" value="" />
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<parameter name="cpu_name" value="cpu" />
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<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
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<parameter name="breakAbsoluteAddr" value="406857760" />
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<parameter name="setting_activateTrace" value="true" />
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<parameter name="debug_offchiptrace" value="false" />
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<parameter name="setting_avalonDebugPortPresent" value="false" />
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<parameter name="dcache_numTCDM" value="0" />
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<parameter name="setting_ecc_sim_test_ports" value="false" />
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<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
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<parameter name="setting_showUnpublishedSettings" value="false" />
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<parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
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<parameter name="debug_debugReqSignals" value="false" />
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<parameter name="master_addr_map" value="false" />
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<parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
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<parameter name="mmu_processIDNumBits" value="8" />
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<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
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<parameter name="debug_onchiptrace" value="false" />
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<parameter name="setting_rf_ecc_present" value="true" />
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<parameter name="resetAbsoluteAddr" value="335544320" />
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<parameter name="tightly_coupled_data_master_1_paddr_top" value="0" />
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<parameter name="ocimem_ramInit" value="false" />
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|
<parameter name="internalIrqMaskSystemInfo" value="61" />
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|
<parameter name="instruction_master_paddr_top" value="0" />
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<parameter name="cpuArchRev" value="1" />
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<parameter name="setting_dtcm_ecc_present" value="false" />
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<parameter name="exceptionAbsoluteAddr" value="134218016" />
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<parameter name="setting_interruptControllerType" value="Internal" />
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<parameter name="dcache_tagramBlockType" value="Automatic" />
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<parameter name="debug_insttrace" value="false" />
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<parameter name="icache_size" value="2048" />
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<parameter name="setting_itcm_ecc_present" value="false" />
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<parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
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<parameter
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name="dataSlaveMapParam"
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|
value="<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='descriptor_memory.s1' start='0x18400000' end='0x18402000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='eth_tse.control_port' start='0x18403000' end='0x18403400' type='altera_eth_tse.control_port' /><slave name='calibration_ram.s1' start='0x18403400' end='0x18403680' type='altera_avalon_onchip_memory2.s1' /><slave name='frame_timer.s1' start='0x18403C00' end='0x18403C20' type='altera_avalon_timer.s1' /><slave name='debug_uart.s1' start='0x18403C20' end='0x18403C40' type='altera_avalon_uart.s1' /><slave name='output_pio.s1' start='0x18403C40' end='0x18403C60' type='altera_avalon_pio.s1' /><slave name='sys_clk_timer.s1' start='0x18403C60' end='0x18403C80' type='altera_avalon_timer.s1' /><slave name='msgdma_rx.prefetcher_csr' start='0x18403C80' end='0x18403CA0' type='altera_msgdma.prefetcher_csr' /><slave name='msgdma_tx.prefetcher_csr' start='0x18403CA0' end='0x18403CC0' type='altera_msgdma.prefetcher_csr' /><slave name='udp_generator.csr' start='0x18403CC0' end='0x18403CE0' type='udp_generator.csr' /><slave name='msgdma_rx.csr' start='0x18403CE0' end='0x18403D00' type='altera_msgdma.csr' /><slave name='msgdma_tx.csr' start='0x18403D00' end='0x18403D20' type='altera_msgdma.csr' /><slave name='ext_flash.avl_csr' start='0x18403D20' end='0x18403D40' type='altera_generic_quad_spi_controller.avl_csr' /><slave name='button_pio.s1' start='0x18403D40' end='0x18403D50' type='altera_avalon_pio.s1' /><slave name='sensor_interface.csr' start='0x18403D50' end='0x18403D60' type='sensor_recon.csr' /><slave name='onchip_flash.csr' start='0x18403D60' end='0x18403D68' type='altera_onchip_flash.csr' /><slave name='sysid.control_slave' start='0x18403D68' end='0x18403D70' type='altera_avalon_sysid_qsys.control_slave' /></address-map>" />
|
|
<parameter name="mpu_enabled" value="false" />
|
|
<parameter name="setting_ecc_present" value="false" />
|
|
<parameter name="mmu_TLBMissExcAbsAddr" value="0" />
|
|
<parameter name="mpu_useLimit" value="false" />
|
|
<parameter name="stratix_dspblock_shift_mul" value="false" />
|
|
<parameter name="icache_numTCIM" value="0" />
|
|
<parameter name="setting_usedesignware" value="false" />
|
|
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
|
|
<parameter name="instruction_master_high_performance_paddr_top" value="0" />
|
|
<parameter name="setting_ioregionBypassDCache" value="false" />
|
|
<parameter name="mmu_TLBMissExcOffset" value="0" />
|
|
<parameter name="mmu_enabled" value="false" />
|
|
<parameter name="mmu_uitlbNumEntries" value="4" />
|
|
<parameter name="register_file_por" value="false" />
|
|
<parameter name="faAddrWidth" value="1" />
|
|
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
|
|
<parameter name="tightly_coupled_data_master_3_paddr_top" value="0" />
|
|
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
|
|
<parameter name="setting_activateTestEndChecker" value="false" />
|
|
<parameter name="cpuID" value="0" />
|
|
<parameter name="resetrequest_enabled" value="true" />
|
|
<parameter name="setting_asic_enabled" value="false" />
|
|
<parameter name="exceptionSlave" value="ddr3_ram.avl" />
|
|
<parameter name="setting_HDLSimCachesCleared" value="true" />
|
|
<parameter name="debug_triggerArming" value="true" />
|
|
<parameter name="debug_OCIOnchipTrace" value="_128" />
|
|
<parameter name="dataAddrWidth" value="29" />
|
|
<parameter name="setting_bit31BypassDCache" value="true" />
|
|
<parameter name="instAddrWidth" value="29" />
|
|
<parameter name="setting_asic_add_scan_mode_input" value="false" />
|
|
<parameter name="tightly_coupled_instruction_master_1_paddr_top" value="0" />
|
|
<parameter name="io_regionbase" value="0" />
|
|
<parameter name="setting_shadowRegisterSets" value="0" />
|
|
<parameter name="icache_ramBlockType" value="Automatic" />
|
|
<parameter name="data_master_paddr_top" value="0" />
|
|
<parameter name="translate_on" value=" "synthesis translate_on" " />
|
|
<parameter name="faSlaveMapParam" value="" />
|
|
<parameter name="setting_clearXBitsLDNonBypass" value="true" />
|
|
<parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
|
|
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
|
|
<parameter name="mmu_autoAssignTlbPtrSz" value="true" />
|
|
<parameter name="fa_cache_line" value="2" />
|
|
<parameter name="debug_assignJtagInstanceID" value="false" />
|
|
<parameter name="instruction_master_paddr_base" value="0" />
|
|
<parameter name="userDefinedSettings" value="" />
|
|
<parameter name="clockFrequency" value="50000000" />
|
|
<parameter name="setting_activateMonitors" value="true" />
|
|
<parameter name="resetOffset" value="0" />
|
|
<parameter name="dcache_ramBlockType" value="Automatic" />
|
|
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
|
|
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
|
|
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
|
|
<parameter name="tightly_coupled_instruction_master_0_paddr_top" value="0" />
|
|
<parameter name="setting_allow_break_inst" value="false" />
|
|
<parameter name="setting_asic_third_party_synthesis" value="false" />
|
|
<parameter name="io_regionsize" value="0" />
|
|
<parameter name="mpu_minInstRegionSize" value="12" />
|
|
<parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
|
|
<parameter name="translate_off" value=" "synthesis translate_off" " />
|
|
<parameter name="mpu_numOfInstRegion" value="8" />
|
|
<parameter name="flash_instruction_master_paddr_base" value="0" />
|
|
<parameter name="setting_exportdebuginfo" value="false" />
|
|
<parameter name="mmu_tlbPtrSz" value="7" />
|
|
<parameter name="cpuReset" value="false" />
|
|
<parameter name="resetSlave" value="ext_flash.avl_mem" />
|
|
<parameter name="dcache_bursts_derived" value="false" />
|
|
<parameter name="multiplierType" value="mul_fast32" />
|
|
<parameter name="setting_removeRAMinit" value="false" />
|
|
<parameter name="icache_tagramBlockType" value="Automatic" />
|
|
<parameter name="debug_traceStorage" value="onchip_trace" />
|
|
<parameter name="setting_preciseIllegalMemAccessException" value="false" />
|
|
<parameter name="fa_cache_linesize" value="0" />
|
|
<parameter name="setting_mmu_ecc_present" value="true" />
|
|
<parameter name="debug_datatrace" value="false" />
|
|
<parameter name="setting_HBreakTest" value="false" />
|
|
<parameter name="debug_hwbreakpoint" value="2" />
|
|
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
|
|
<parameter name="dataMasterHighPerformanceMapParam" value="" />
|
|
<parameter name="tightly_coupled_data_master_2_paddr_top" value="0" />
|
|
<parameter name="setting_disableocitrace" value="false" />
|
|
<parameter name="setting_bigEndian" value="false" />
|
|
<parameter name="mpu_minDataRegionSize" value="12" />
|
|
<parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
|
|
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
|
|
<parameter name="debug_jtagInstanceID" value="0" />
|
|
<parameter name="setting_showInternalSettings" value="false" />
|
|
<parameter name="setting_breakslaveoveride" value="false" />
|
|
<parameter name="debug_traceType" value="none" />
|
|
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
|
|
<parameter name="tightly_coupled_instruction_master_2_paddr_top" value="0" />
|
|
<parameter name="setting_alwaysEncrypt" value="true" />
|
|
<parameter name="setting_oci_export_jtag_signals" value="false" />
|
|
<parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
|
|
<parameter name="data_master_high_performance_paddr_top" value="0" />
|
|
<parameter name="dcache_lineSize_derived" value="32" />
|
|
<parameter name="deviceFamilyName" value="MAX 10" />
|
|
<parameter name="debug_datatrigger" value="0" />
|
|
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
|
|
<parameter name="debug_enabled" value="true" />
|
|
<parameter name="setting_export_large_RAMs" value="false" />
|
|
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
|
|
<parameter name="setting_dc_ecc_present" value="false" />
|
|
<parameter name="setting_support31bitdcachebypass" value="true" />
|
|
<parameter
|
|
name="instSlaveMapParam"
|
|
value="<address-map><slave name='ddr3_ram.avl' start='0x8000000' end='0x10000000' type='altera_mem_if_ddr3_emif.avl' /><slave name='ext_flash.avl_mem' start='0x14000000' end='0x18000000' type='altera_generic_quad_spi_controller.avl_mem' /><slave name='onchip_flash.data' start='0x18200000' end='0x18360000' type='altera_onchip_flash.data' /><slave name='cpu.debug_mem_slave' start='0x18402800' end='0x18403000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>" />
|
|
<parameter name="dividerType" value="no_div" />
|
|
<parameter name="setting_bhtPtrSz" value="8" />
|
|
<parameter name="setting_exportvectors" value="false" />
|
|
<parameter name="tmr_enabled" value="false" />
|
|
<parameter name="data_master_paddr_base" value="0" />
|
|
<parameter name="breakSlave_derived" value="cpu.debug_mem_slave" />
|
|
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
|
|
<parameter name="mpu_numOfDataRegion" value="8" />
|
|
<parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
|
|
<parameter name="mmu_ramBlockType" value="Automatic" />
|
|
<parameter name="data_master_high_performance_paddr_base" value="0" />
|
|
<parameter name="cdx_enabled" value="false" />
|
|
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
|
|
<parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
|
|
<parameter name="dcache_bursts" value="false" />
|
|
<parameter name="tracefilename" value="" />
|
|
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
|
|
<parameter name="setting_asic_synopsys_translate_on_off" value="false" />
|
|
<parameter name="setting_fast_register_read" value="false" />
|
|
<parameter name="mmu_tlbNumWays" value="16" />
|
|
<parameter name="shifterType" value="fast_le_shift" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_mult_cell.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu.sdc"
|
|
type="SDC"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_bht_ram.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_test_bench.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_sysclk.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_ic_tag_ram.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_tck.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_a.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_rf_ram_b.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_ociram_default_contents.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_dc_tag_ram.mif"
|
|
type="MIF"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_cpu_cpu_debug_slave_wrapper.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_nios2_gen2_rtl_module.ocp"
|
|
type="OTHER"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_cpu" as="cpu" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 233 starting:altera_nios2_gen2_unit "submodules/q_sys_cpu_cpu"</message>
|
|
<message level="Info" culprit="cpu">Starting RTL generation for module 'q_sys_cpu_cpu'</message>
|
|
<message level="Info" culprit="cpu"> Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=q_sys_cpu_cpu --dir=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen/ --quartus_bindir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/ --verilog --config=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen//q_sys_cpu_cpu_processor_configuration.pl --do_build_sim=0 ]</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Starting Nios II generation</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Elaborating CPU configuration settings</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Creating all objects for CPU</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Testbench</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Instruction decoding</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Instruction fields</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:22 (*) Instruction decodes</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Signals for RTL simulation waveforms</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Instruction controls</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Pipeline frontend</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:23 (*) Pipeline backend</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Generating RTL from CPU objects</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Creating plain-text RTL</message>
|
|
<message level="Info" culprit="cpu"># 2024.10.11 10:10:24 (*) Done Nios II generation</message>
|
|
<message level="Info" culprit="cpu">Done RTL generation for module 'q_sys_cpu_cpu'</message>
|
|
<message level="Info" culprit="cpu"><![CDATA["<b>cpu</b>" instantiated <b>altera_nios2_gen2_unit</b> "<b>cpu</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_mem_if_ddr3_pll:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PERIOD_PS=10000,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true"
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instancePathKey="q_sys:.:ddr3_ram:.:pll0"
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kind="altera_mem_if_ddr3_pll"
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version="19.1"
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name="q_sys_ddr3_ram_pll0">
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<parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
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<parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
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<parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
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<parameter name="LRDIMM_INT" value="0" />
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<parameter name="MAX_LATENCY_COUNT_WIDTH" value="5" />
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<parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
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<parameter name="PLL_AFI_CLK_MULT_PARAM" value="3" />
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<parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
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<parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
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<parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
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<parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
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<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
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<parameter name="MEM_LEVELING" value="true" />
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<parameter name="FLY_BY" value="false" />
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<parameter name="TIMING_TQSH" value="0.4" />
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<parameter name="PLL_AFI_HALF_CLK_DIV" value="1" />
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<parameter name="PLL_AFI_PHY_CLK_FREQ" value="0.0" />
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<parameter name="AFI_CLK_PAIR_COUNT" value="1" />
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<parameter name="HARD_EMIF" value="false" />
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<parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
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<parameter name="MEM_REGDIMM_ENABLED" value="false" />
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<parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
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<parameter name="MEM_CLK_MAX_NS" value="1.25" />
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<parameter name="REF_CLK_FREQ_MAX_PARAM" value="500.0" />
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<parameter name="PLL_AFI_CLK_DIV_PARAM" value="2" />
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<parameter name="CALIB_REG_WIDTH" value="8" />
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<parameter name="PLL_HR_CLK_FREQ" value="0.0" />
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<parameter name="AFI_DQ_WIDTH" value="32" />
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<parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
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<parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
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<parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
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<parameter name="AP_MODE_EN" value="0" />
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<parameter name="MEM_TINIT_CK" value="150000" />
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<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
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<parameter name="CALIB_LFIFO_OFFSET" value="4" />
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<parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
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<parameter name="IO_DQS_OUT_RESERVE" value="3" />
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<parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
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<parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
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<parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
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<parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
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<parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
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<parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="0 ps" />
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<parameter name="MEM_BL" value="OTF" />
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<parameter name="MEM_TRAS_NS" value="35.0" />
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<parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
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<parameter name="ENABLE_EXTRA_REPORTING" value="false" />
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<parameter name="IO_DQ_OUT_RESERVE" value="0" />
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<parameter name="IO_DM_OUT_RESERVE" value="0" />
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<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
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<parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
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<parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
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<parameter name="MEM_BT" value="Sequential" />
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<parameter name="DELAY_PER_OPA_TAP" value="416" />
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<parameter name="MEM_TRTP" value="3" />
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<parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
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<parameter name="TREFI" value="35100" />
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<parameter name="HHP_HPS_VERIFICATION" value="false" />
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<parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="PLL_AFI_CLK_DIV_CACHE" value="2" />
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<parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="1" />
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<parameter name="MEM_DQ_PER_DQS" value="8" />
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<parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="2" />
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<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="2500" />
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<parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
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<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
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<parameter name="RDIMM_CONFIG" value="0000000000000000" />
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<parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
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<parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
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<parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
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<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
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<parameter name="PLL_AFI_CLK_MULT_CACHE" value="3" />
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<parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
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<parameter name="MR1_RDQS" value="0" />
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<parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
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<parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="1" />
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<parameter name="DEVICE_WIDTH" value="1" />
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<parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
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<parameter name="MR0_PD" value="0" />
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<parameter name="MEM_VENDOR" value="JEDEC" />
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<parameter name="PLL_HR_CLK_FREQ_STR" value="" />
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<parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
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<parameter name="MEM_IF_CS_PER_RANK" value="1" />
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<parameter name="COMMAND_PHASE_CACHE" value="0.0" />
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<parameter name="AFI_CONTROL_WIDTH" value="2" />
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<parameter name="PLL_HR_CLK_DIV" value="0" />
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<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
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<parameter name="REF_CLK_FREQ_MIN_CACHE" value="10.0" />
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<parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
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<parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
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<parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
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<parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
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<parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
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<parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="0 ps" />
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<parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
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<parameter name="MEM_IF_DM_PINS_EN" value="true" />
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<parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
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<parameter name="USE_MEM_CLK_FREQ" value="false" />
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<parameter name="MEM_DEVICE" value="MISSING_MODEL" />
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<parameter name="IO_DQS_EN_PHASE_MAX" value="7" />
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<parameter name="USER_DEBUG_LEVEL" value="1" />
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<parameter name="RDIMM" value="false" />
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<parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
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<parameter name="PLL_CONFIG_CLK_FREQ" value="0.0" />
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<parameter name="PLL_PHASE_COUNTER_WIDTH" value="4" />
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<parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
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<parameter name="MEM_TRC" value="15" />
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<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
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<parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="6668 ps" />
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<parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
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<parameter name="DATA_RATE_RATIO" value="2" />
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<parameter name="AFI_CS_WIDTH" value="2" />
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<parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
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<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
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<parameter name="PLL_NIOS_CLK_MULT" value="0" />
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<parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
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<parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
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<parameter name="MEM_CLK_NS" value="3.333" />
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<parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
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<parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="270.0" />
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<parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
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<parameter name="PLL_AFI_CLK_MULT" value="3" />
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<parameter name="SKIP_MEM_INIT" value="true" />
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<parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
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<parameter name="MR1_TDQS" value="0" />
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<parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
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<parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="300.0 MHz" />
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<parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="1" />
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<parameter name="PLL_WRITE_CLK_FREQ_STR" value="300.0 MHz" />
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<parameter name="RATE" value="Half" />
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<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
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<parameter name="DEVICE_FAMILY" value="MAX 10" />
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<parameter name="MR1_WL" value="0" />
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<parameter name="REFRESH_BURST_VALIDATION" value="false" />
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<parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
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<parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="270.0" />
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<parameter name="MR3_MPR_RF" value="0" />
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<parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
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<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
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<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
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<parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
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<parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
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<parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="1" />
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<parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
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<parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="50" />
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<parameter name="MEM_IF_ADDR_WIDTH" value="14" />
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<parameter name="PLL_DR_CLK_DIV" value="0" />
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<parameter name="USE_SEQUENCER_BFM" value="false" />
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<parameter name="DELAY_PER_DCHAIN_TAP" value="50" />
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<parameter name="MEM_CLK_MAX_PS" value="1250.0" />
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<parameter name="CSR_ADDR_WIDTH" value="8" />
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<parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
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<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
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<parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="3" />
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<parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
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<parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
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<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
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<parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
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<parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
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<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
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<parameter name="EXPORT_AFI_HALF_CLK" value="false" />
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<parameter name="MEM_BURST_LENGTH" value="8" />
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<parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="6668 ps" />
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<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
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<parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
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<parameter name="PLL_AFI_CLK_FREQ_STR" value="150.0 MHz" />
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<parameter name="IO_DQDQS_OUT_PHASE_MAX" value="14" />
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<parameter name="MEM_TRRD" value="2" />
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<parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
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<parameter name="RDIMM_INT" value="0" />
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<parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
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<parameter name="READ_VALID_FIFO_SIZE" value="16" />
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<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
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<parameter name="REFRESH_INTERVAL" value="15000" />
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<parameter name="DLL_MASTER" value="true" />
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<parameter name="PLL_WRITE_CLK_DIV_PARAM" value="1" />
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<parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
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<parameter name="MEM_TWTR" value="6" />
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<parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
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<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_INIT_EN" value="false" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="Unknown" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
|
|
<parameter name="MEM_TRFC_NS" value="110.0" />
|
|
<parameter name="TIMING_BOARD_TDH_APPLIED" value="0.145" />
|
|
<parameter name="ADDR_RATE_RATIO" value="1" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
|
|
<parameter name="ENABLE_ISS_PROBES" value="false" />
|
|
<parameter name="MR2_RTT_WR" value="0" />
|
|
<parameter name="TIMING_BOARD_TDS_APPLIED" value="0.16" />
|
|
<parameter name="AFI_ODT_WIDTH" value="2" />
|
|
<parameter name="PLL_MASTER" value="true" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
|
|
<parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
|
|
<parameter name="DISCRETE_FLY_BY" value="true" />
|
|
<parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
|
|
<parameter name="MEM_RTT_NOM" value="ODT Disabled" />
|
|
<parameter name="QVLD_WR_ADDRESS_OFFSET" value="4" />
|
|
<parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="1" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="TB_PLL_DLL_MASTER" value="true" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT" value="0" />
|
|
<parameter name="MEM_IF_DM_WIDTH" value="1" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS" value="2500" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="AFI_WRANK_WIDTH" value="2" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="2500" />
|
|
<parameter name="LRDIMM" value="false" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="2500" />
|
|
<parameter name="MR1_DLL" value="0" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
|
|
<parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
|
|
<parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PHY_CLKBUF" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="SEQUENCER_TYPE" value="NIOS" />
|
|
<parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
|
|
<parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="MEM_IF_CHIP_BITS" value="1" />
|
|
<parameter name="VFIFO_AS_SHIFT_REG" value="true" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
|
|
<parameter name="MEM_IF_CK_WIDTH" value="1" />
|
|
<parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
|
|
<parameter name="MEM_TCL" value="5" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
|
|
<parameter name="TIMING_TDQSCK" value="225" />
|
|
<parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
|
|
<parameter name="DLL_SHARING_MODE" value="None" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="2500" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="PLL_DR_CLK_MULT" value="0" />
|
|
<parameter name="USE_USER_RDIMM_VALUE" value="false" />
|
|
<parameter name="MEM_FORMAT" value="DISCRETE" />
|
|
<parameter name="AFI_RATE_RATIO" value="2" />
|
|
<parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
|
|
<parameter name="PLL_MEM_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="CFG_TCCD_NS" value="2.5" />
|
|
<parameter name="IO_DQS_IN_RESERVE" value="3" />
|
|
<parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="AFI_WLAT_WIDTH" value="6" />
|
|
<parameter name="ENABLE_NIOS_OCI" value="false" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="FIX_READ_LATENCY" value="8" />
|
|
<parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
|
|
<parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
|
|
<parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
|
|
<parameter name="RATE_CACHE" value="Unknown" />
|
|
<parameter name="COMMAND_PHASE" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT" value="3" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
|
|
<parameter name="MR1_ODS" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="MEM_TRFC" value="34" />
|
|
<parameter name="PHY_CSR_ENABLED" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="DQ_DDR" value="1" />
|
|
<parameter name="PLL_WRITE_CLK_MULT_PARAM" value="3" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_DEG" value="270.0" />
|
|
<parameter name="MEM_INIT_FILE" value="" />
|
|
<parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="MEM_CK_PHASE" value="0.0" />
|
|
<parameter name="FORCE_DQS_TRACKING" value="AUTO" />
|
|
<parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="0.02286" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
|
|
<parameter name="TB_RATE" value="HALF" />
|
|
<parameter name="REF_CLK_FREQ_CACHE_VALID" value="true" />
|
|
<parameter name="MEM_CK_WIDTH" value="1" />
|
|
<parameter name="MEM_ATCL" value="Disabled" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="DISABLE_CHILD_MESSAGING" value="true" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
|
|
<parameter name="MEM_TDQSCK" value="1" />
|
|
<parameter name="MEM_VERBOSE" value="true" />
|
|
<parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
|
|
<parameter name="HARD_PHY" value="false" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="MR2_SRF" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
|
|
<parameter name="REF_CLK_FREQ_MIN_PARAM" value="10.0" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="MEM_WTCL" value="5" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="PLL_MEM_CLK_MULT" value="3" />
|
|
<parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="MEM_IF_CS_PER_DIMM" value="1" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="VCALIB_COUNT_WIDTH" value="2" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
|
|
<parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="DLL_USE_DR_CLK" value="false" />
|
|
<parameter name="AC_PARITY" value="false" />
|
|
<parameter name="PLL_WRITE_CLK_DIV" value="1" />
|
|
<parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
|
|
<parameter name="MR1_DQS" value="0" />
|
|
<parameter name="MR2_SRT" value="0" />
|
|
<parameter name="CALIB_VFIFO_OFFSET" value="12" />
|
|
<parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="3" />
|
|
<parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
|
|
<parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
|
|
<parameter name="MR1_QOFF" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="MEM_DRV_STR" value="RZQ/6" />
|
|
<parameter name="MEM_TREFI" value="2341" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
|
|
<parameter name="TB_MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="NUM_SUBGROUP_PER_READ_DQS" value="1" />
|
|
<parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_PARAM" value="150.0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="2500" />
|
|
<parameter name="MEM_TRP_NS" value="13.75" />
|
|
<parameter name="DLL_DELAY_CTRL_WIDTH" value="6" />
|
|
<parameter name="QVLD_EXTRA_FLOP_STAGES" value="0" />
|
|
<parameter name="MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="MEM_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ" value="300.0" />
|
|
<parameter name="USE_FAKE_PHY" value="false" />
|
|
<parameter name="EXTRA_SETTINGS" value="" />
|
|
<parameter name="PLL_DR_CLK_FREQ_STR" value="" />
|
|
<parameter name="SEQ_MODE" value="0" />
|
|
<parameter name="MEM_IF_CS_WIDTH" value="1" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
|
|
<parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="MEM_TYPE" value="DDR3" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="REF_CLK_PS" value="10000.0" />
|
|
<parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="false" />
|
|
<parameter name="SEQUENCER_TYPE_CACHE" value="Unknown" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="MR0_BT" value="0" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
|
|
<parameter name="MR1_AL" value="0" />
|
|
<parameter name="DQS_PHASE_SHIFT" value="9000" />
|
|
<parameter name="MR0_BL" value="1" />
|
|
<parameter name="MARGIN_VARIATION_TEST" value="false" />
|
|
<parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
|
|
<parameter name="TIMING_TIS" value="170" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
|
|
<parameter name="MEM_TRCD" value="5" />
|
|
<parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
|
|
<parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
|
|
<parameter name="IO_IN_DELAY_MAX" value="15" />
|
|
<parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
|
|
<parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="REGISTER_C2P" value="false" />
|
|
<parameter name="FAST_SIM_CALIBRATION" value="false" />
|
|
<parameter name="MEM_WTCL_INT" value="5" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
|
|
<parameter name="DQS_EN_DELAY_MAX" value="7" />
|
|
<parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="0 ps" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="DELAY_BUFFER_MODE" value="HIGH" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="REF_CLK_FREQ" value="100.0" />
|
|
<parameter name="AFI_RRANK_WIDTH" value="2" />
|
|
<parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV" value="0" />
|
|
<parameter name="MR0_DLL" value="1" />
|
|
<parameter name="FORCE_SHADOW_REGS" value="AUTO" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PINGPONGPHY_EN" value="false" />
|
|
<parameter name="MR3_MPR" value="0" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="6668 ps" />
|
|
<parameter name="REF_CLK_PERIOD_PS" value="10000" />
|
|
<parameter name="MR2_ASR" value="0" />
|
|
<parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
|
|
<parameter name="MR2_CWL" value="0" />
|
|
<parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV" value="1" />
|
|
<parameter name="HPS_PROTOCOL" value="DEFAULT" />
|
|
<parameter name="MEM_IF_LRDIMM_RM" value="0" />
|
|
<parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="MEM_IF_ODT_WIDTH" value="1" />
|
|
<parameter name="TIMING_TDQSCKDL" value="1200" />
|
|
<parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="TIMING_TDQSCKDS" value="450" />
|
|
<parameter name="TIMING_TDQSCKDM" value="900" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="TIMING_BOARD_TIS" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="DUPLICATE_AC" value="false" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="NIOS_HEX_FILE_LOCATION" value="../" />
|
|
<parameter name="DUAL_WRITE_CLOCK" value="false" />
|
|
<parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="0 ps" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
|
|
<parameter name="TIMING_BOARD_TIH" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_MULT" value="3" />
|
|
<parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
|
|
<parameter name="REF_CLK_FREQ_PARAM_VALID" value="true" />
|
|
<parameter name="PLL_MEM_CLK_DIV_PARAM" value="1" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="TIMING_BOARD_TDS" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
|
|
<parameter name="AFI_BANKADDR_WIDTH" value="6" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="TIMING_BOARD_TDH" value="0.0" />
|
|
<parameter name="PACKAGE_DESKEW" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="TRACKING_WATCH_TEST" value="false" />
|
|
<parameter name="MEM_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
|
|
<parameter name="AFI_DM_WIDTH" value="4" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV" value="0" />
|
|
<parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
|
|
<parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
|
|
<parameter name="USE_SHADOW_REGS" value="false" />
|
|
<parameter name="REF_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="TRACKING_ERROR_TEST" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="REF_CLK_FREQ_STR" value="100.0 MHz" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
|
|
<parameter name="PLL_MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="MEM_IF_DQ_WIDTH" value="8" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
|
|
<parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
|
|
<parameter name="MR1_RTT" value="0" />
|
|
<parameter name="PLL_MEM_CLK_MULT_PARAM" value="3" />
|
|
<parameter name="READ_FIFO_HALF_RATE" value="true" />
|
|
<parameter name="ADDR_CMD_DDR" value="0" />
|
|
<parameter name="GENERIC_PLL" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
|
|
<parameter name="ENABLE_NON_DES_CAL" value="false" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
|
|
<parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
|
|
<parameter name="MR3_MPR_AA" value="0" />
|
|
<parameter name="CSR_DATA_WIDTH" value="32" />
|
|
<parameter name="MEM_DLL_EN" value="true" />
|
|
<parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
|
|
<parameter name="IS_ES_DEVICE" value="false" />
|
|
<parameter name="PRE_V_SERIES_FAMILY" value="false" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="MEM_TFAW_NS" value="30.0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="1" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ" value="300.0" />
|
|
<parameter name="HHP_HPS_SIMULATION" value="false" />
|
|
<parameter name="REF_CLK_NS" value="10.0" />
|
|
<parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="IO_OUT2_DELAY_MAX" value="7" />
|
|
<parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
|
|
<parameter name="AFI_CLK_EN_WIDTH" value="2" />
|
|
<parameter name="TIMING_TQH" value="0.38" />
|
|
<parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_CLK_CACHE_VALID" value="true" />
|
|
<parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
|
|
<parameter name="PLL_MEM_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="HCX_COMPAT_MODE" value="false" />
|
|
<parameter name="PLL_HR_CLK_MULT" value="0" />
|
|
<parameter name="MEM_IF_DQSN_EN" value="true" />
|
|
<parameter name="AC_ROM_MR0" value="0001000010001" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="HHP_HPS" value="false" />
|
|
<parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_TRAS" value="11" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="MEM_TINIT_US" value="500" />
|
|
<parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
|
|
<parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="DAT_DATA_WIDTH" value="32" />
|
|
<parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
|
|
<parameter name="CALIBRATION_MODE" value="Skip" />
|
|
<parameter name="AC_ROM_MR1_CALIB" value="" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
|
|
<parameter name="PLL_MEM_CLK_DIV" value="1" />
|
|
<parameter name="SPEED_GRADE" value="6" />
|
|
<parameter name="AC_ROM_MR2" value="0000000000000" />
|
|
<parameter name="AC_ROM_MR1" value="0000000000000" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV" value="0" />
|
|
<parameter name="AC_ROM_MR3" value="0000000000000" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="MEM_TRCD_NS" value="13.75" />
|
|
<parameter name="USE_HARD_READ_FIFO" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
|
|
<parameter name="AFI_ADDR_WIDTH" value="28" />
|
|
<parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
|
|
<parameter name="PHY_VERSION_NUMBER" value="191" />
|
|
<parameter name="MEM_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="TIMING_BOARD_TIH_APPLIED" value="0.22" />
|
|
<parameter name="USE_HPS_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="MEM_SRT" value="Normal" />
|
|
<parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
|
|
<parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
|
|
<parameter name="EXPORT_CSR_PORT" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="2500 ps" />
|
|
<parameter name="PLL_WRITE_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="EXTRA_VFIFO_SHIFT" value="0" />
|
|
<parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
|
|
<parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="TIMING_TDS" value="10" />
|
|
<parameter name="PLL_CLK_PARAM_VALID" value="true" />
|
|
<parameter name="MEM_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="CFG_TCCD" value="1" />
|
|
<parameter name="MEM_CS_WIDTH" value="1" />
|
|
<parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
|
|
<parameter name="TIMING_TDH" value="45" />
|
|
<parameter name="DELAY_CHAIN_LENGTH" value="8" />
|
|
<parameter name="SCC_DATA_WIDTH" value="1" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ" value="300.0" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="MEM_TREFI_US" value="7.8" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_WRITE_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="USE_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_LRDIMM_ENABLED" value="false" />
|
|
<parameter name="TIMING_BOARD_TIS_APPLIED" value="0.32" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.04429" />
|
|
<parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
|
|
<parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="AC_ROM_MR0_CALIB" value="" />
|
|
<parameter name="MEM_TWR_NS" value="15.0" />
|
|
<parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="MEM_T_WL" value="5" />
|
|
<parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
|
|
<parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="AFI_RLAT_WIDTH" value="6" />
|
|
<parameter name="MEM_TRP" value="5" />
|
|
<parameter name="MEM_CLK_PS" value="3333.0" />
|
|
<parameter name="IS_ES_DEVICE_CACHE" value="false" />
|
|
<parameter name="PLL_AFI_CLK_FREQ" value="150.0" />
|
|
<parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="MEM_TMRD_CK" value="4" />
|
|
<parameter name="MEM_TRRD_NS" value="6.0" />
|
|
<parameter name="IO_OUT1_DELAY_MAX" value="15" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="270.0" />
|
|
<parameter name="DEVICE_DEPTH" value="1" />
|
|
<parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_MULT" value="3" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="DQS_IN_DELAY_MAX" value="15" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="AC_PACKAGE_DESKEW" value="false" />
|
|
<parameter name="MR0_CAS_LATENCY" value="1" />
|
|
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.0" />
|
|
<parameter name="MR0_WR" value="1" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
|
|
<parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
|
|
<parameter name="SEQ_BURST_COUNT_WIDTH" value="1" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="PHY_ONLY" value="false" />
|
|
<parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="false" />
|
|
<parameter name="TRFC" value="350" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="IO_STANDARD" value="SSTL-15" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="TIMING_TDQSS" value="0.27" />
|
|
<parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
|
|
<parameter name="TIMING_TDQSQ" value="100" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="SPEED_GRADE_CACHE" value="" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_CACHE" value="150.0" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="READ_FIFO_SIZE" value="8" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
|
|
<parameter name="USE_2X_FF" value="false" />
|
|
<parameter name="MEM_ASR" value="Manual" />
|
|
<parameter name="PLL_DR_CLK_FREQ" value="0.0" />
|
|
<parameter name="TB_MEM_IF_DQ_WIDTH" value="8" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
|
|
<parameter name="NEGATIVE_WRITE_CK_PHASE" value="true" />
|
|
<parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="ADVANCED_CK_PHASES" value="false" />
|
|
<parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
|
|
<parameter name="NEXTGEN" value="true" />
|
|
<parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
|
|
<parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
|
|
<parameter name="MEM_ATCL_INT" value="0" />
|
|
<parameter name="MEM_T_RL" value="5" />
|
|
<parameter name="MEM_TWR" value="5" />
|
|
<parameter name="USE_DR_CLK" value="false" />
|
|
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="2500" />
|
|
<parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
|
|
<parameter name="ENABLE_EMIT_JTAG_MASTER" value="false" />
|
|
<parameter name="MEM_IF_DQS_WIDTH" value="1" />
|
|
<parameter name="TIMING_TDSS" value="0.18" />
|
|
<parameter name="TIMING_TIH" value="120" />
|
|
<parameter name="CSR_BE_WIDTH" value="4" />
|
|
<parameter name="PLL_LOCATION" value="Top_Bottom" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="2500 ps" />
|
|
<parameter name="MEM_TRTP_NS" value="7.5" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="PLL_SHARING_MODE" value="None" />
|
|
<parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
|
|
<parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="2500" />
|
|
<parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
|
|
<parameter name="AP_MODE" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="false" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
|
|
<parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
|
|
<parameter name="MEM_PD" value="DLL off" />
|
|
<parameter name="MAX10_RTL_SEQ" value="true" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="TIMING_TDSH" value="0.18" />
|
|
<parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
|
|
<parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
|
|
<parameter name="REF_CLK_FREQ_MAX_CACHE" value="500.0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_AFI_CLK_DIV" value="2" />
|
|
<parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
|
|
<parameter name="MEM_TFAW" value="10" />
|
|
<parameter name="MEM_DQ_WIDTH" value="8" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_pll0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/altera_mem_if_pll/altera_mem_if_ddr3_pll/altera_mem_if_ddr3_pll_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
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</sourceFiles>
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<childSourceFiles/>
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<instantiator instantiator="q_sys_ddr3_ram" as="pll0" />
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<messages>
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<message level="Debug" culprit="q_sys">queue size: 232 starting:altera_mem_if_ddr3_pll "submodules/q_sys_ddr3_ram_pll0"</message>
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<message level="Info" culprit="pll0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"]]></message>
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</messages>
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</entity>
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<entity
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path="submodules/"
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parameterizationKey="altera_mem_if_ddr3_phy_core:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=7,DQS_IN_DELAY_MAX=15,DQS_PHASE_SHIFT=9000,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,EARLY_ADDR_CMD_CLK_TRANSFER=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=false,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=14,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=15,IO_OUT1_DELAY_MAX=15,IO_OUT2_DELAY_MAX=7,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_RTL_SEQ=true,MAX_LATENCY_COUNT_WIDTH=5,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=3.333,MEM_CLK_PS=3333.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true"
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instancePathKey="q_sys:.:ddr3_ram:.:p0"
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kind="altera_mem_if_ddr3_phy_core"
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version="19.1"
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name="q_sys_ddr3_ram_p0">
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<parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
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<parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
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<parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
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<parameter name="LRDIMM_INT" value="0" />
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<parameter name="MAX_LATENCY_COUNT_WIDTH" value="5" />
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<parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
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<parameter name="PLL_AFI_CLK_MULT_PARAM" value="3" />
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<parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
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<parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
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<parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
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<parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
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<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
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<parameter name="MEM_LEVELING" value="true" />
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<parameter name="FLY_BY" value="false" />
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<parameter name="TIMING_TQSH" value="0.4" />
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<parameter name="PLL_AFI_HALF_CLK_DIV" value="1" />
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<parameter name="PLL_AFI_PHY_CLK_FREQ" value="0.0" />
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<parameter name="AFI_CLK_PAIR_COUNT" value="1" />
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<parameter name="HARD_EMIF" value="false" />
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<parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
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<parameter name="MEM_REGDIMM_ENABLED" value="false" />
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<parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
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<parameter name="MEM_CLK_MAX_NS" value="1.25" />
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<parameter name="REF_CLK_FREQ_MAX_PARAM" value="500.0" />
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<parameter name="PLL_AFI_CLK_DIV_PARAM" value="2" />
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<parameter name="CALIB_REG_WIDTH" value="8" />
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<parameter name="PLL_HR_CLK_FREQ" value="0.0" />
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<parameter name="AFI_DQ_WIDTH" value="32" />
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<parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
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<parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
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<parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
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<parameter name="AP_MODE_EN" value="0" />
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<parameter name="MEM_TINIT_CK" value="150000" />
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<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
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<parameter name="CALIB_LFIFO_OFFSET" value="4" />
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<parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
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<parameter name="IO_DQS_OUT_RESERVE" value="3" />
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<parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
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<parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
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<parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
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<parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
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<parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
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<parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="0 ps" />
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<parameter name="MEM_BL" value="OTF" />
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<parameter name="MEM_TRAS_NS" value="35.0" />
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<parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
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<parameter name="ENABLE_EXTRA_REPORTING" value="false" />
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<parameter name="IO_DQ_OUT_RESERVE" value="0" />
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<parameter name="IO_DM_OUT_RESERVE" value="0" />
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<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
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<parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
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<parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
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<parameter name="MEM_BT" value="Sequential" />
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<parameter name="DELAY_PER_OPA_TAP" value="416" />
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<parameter name="MEM_TRTP" value="3" />
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<parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
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<parameter name="TREFI" value="35100" />
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<parameter name="HHP_HPS_VERIFICATION" value="false" />
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<parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="PLL_AFI_CLK_DIV_CACHE" value="2" />
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<parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="1" />
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<parameter name="MEM_DQ_PER_DQS" value="8" />
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<parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="2" />
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<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="2500" />
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<parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
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<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
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<parameter name="RDIMM_CONFIG" value="0000000000000000" />
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<parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
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<parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
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<parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
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<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
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<parameter name="PLL_AFI_CLK_MULT_CACHE" value="3" />
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<parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
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<parameter name="MR1_RDQS" value="0" />
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<parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
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<parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="1" />
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<parameter name="DEVICE_WIDTH" value="1" />
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<parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
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<parameter name="MR0_PD" value="0" />
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<parameter name="MEM_VENDOR" value="JEDEC" />
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<parameter name="PLL_HR_CLK_FREQ_STR" value="" />
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<parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
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<parameter name="MEM_IF_CS_PER_RANK" value="1" />
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<parameter name="COMMAND_PHASE_CACHE" value="0.0" />
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<parameter name="AFI_CONTROL_WIDTH" value="2" />
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<parameter name="PLL_HR_CLK_DIV" value="0" />
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<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
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<parameter name="REF_CLK_FREQ_MIN_CACHE" value="10.0" />
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<parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
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<parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
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<parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
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<parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
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<parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
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<parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="0 ps" />
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<parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
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<parameter name="MEM_IF_DM_PINS_EN" value="true" />
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<parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
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<parameter name="USE_MEM_CLK_FREQ" value="false" />
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<parameter name="MEM_DEVICE" value="MISSING_MODEL" />
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<parameter name="IO_DQS_EN_PHASE_MAX" value="7" />
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<parameter name="USER_DEBUG_LEVEL" value="1" />
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<parameter name="RDIMM" value="false" />
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<parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
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<parameter name="PLL_CONFIG_CLK_FREQ" value="0.0" />
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<parameter name="PLL_PHASE_COUNTER_WIDTH" value="4" />
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<parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
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<parameter name="MEM_TRC" value="15" />
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<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
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<parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="6668 ps" />
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<parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
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<parameter name="DATA_RATE_RATIO" value="2" />
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<parameter name="AFI_CS_WIDTH" value="2" />
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<parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
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<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
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<parameter name="PLL_NIOS_CLK_MULT" value="0" />
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<parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
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<parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
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<parameter name="MEM_CLK_NS" value="3.333" />
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<parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="270.0" />
|
|
<parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
|
|
<parameter name="PLL_AFI_CLK_MULT" value="3" />
|
|
<parameter name="SKIP_MEM_INIT" value="true" />
|
|
<parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="MR1_TDQS" value="0" />
|
|
<parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="1" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="RATE" value="Half" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="MR1_WL" value="0" />
|
|
<parameter name="REFRESH_BURST_VALIDATION" value="false" />
|
|
<parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="270.0" />
|
|
<parameter name="MR3_MPR_RF" value="0" />
|
|
<parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
|
|
<parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="1" />
|
|
<parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
|
|
<parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="50" />
|
|
<parameter name="MEM_IF_ADDR_WIDTH" value="14" />
|
|
<parameter name="PLL_DR_CLK_DIV" value="0" />
|
|
<parameter name="USE_SEQUENCER_BFM" value="false" />
|
|
<parameter name="DELAY_PER_DCHAIN_TAP" value="50" />
|
|
<parameter name="MEM_CLK_MAX_PS" value="1250.0" />
|
|
<parameter name="CSR_ADDR_WIDTH" value="8" />
|
|
<parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="3" />
|
|
<parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
|
|
<parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
|
|
<parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
|
|
<parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="EXPORT_AFI_HALF_CLK" value="false" />
|
|
<parameter name="MEM_BURST_LENGTH" value="8" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="6668 ps" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_STR" value="150.0 MHz" />
|
|
<parameter name="IO_DQDQS_OUT_PHASE_MAX" value="14" />
|
|
<parameter name="MEM_TRRD" value="2" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="RDIMM_INT" value="0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="READ_VALID_FIFO_SIZE" value="16" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
|
|
<parameter name="REFRESH_INTERVAL" value="15000" />
|
|
<parameter name="DLL_MASTER" value="true" />
|
|
<parameter name="PLL_WRITE_CLK_DIV_PARAM" value="1" />
|
|
<parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
|
|
<parameter name="MEM_TWTR" value="6" />
|
|
<parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_INIT_EN" value="false" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="Unknown" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
|
|
<parameter name="MEM_TRFC_NS" value="110.0" />
|
|
<parameter name="TIMING_BOARD_TDH_APPLIED" value="0.145" />
|
|
<parameter name="ADDR_RATE_RATIO" value="1" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
|
|
<parameter name="ENABLE_ISS_PROBES" value="false" />
|
|
<parameter name="MR2_RTT_WR" value="0" />
|
|
<parameter name="TIMING_BOARD_TDS_APPLIED" value="0.16" />
|
|
<parameter name="AFI_ODT_WIDTH" value="2" />
|
|
<parameter name="PLL_MASTER" value="true" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
|
|
<parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
|
|
<parameter name="DISCRETE_FLY_BY" value="true" />
|
|
<parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
|
|
<parameter name="MEM_RTT_NOM" value="ODT Disabled" />
|
|
<parameter name="QVLD_WR_ADDRESS_OFFSET" value="4" />
|
|
<parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="1" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="TB_PLL_DLL_MASTER" value="true" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT" value="0" />
|
|
<parameter name="MEM_IF_DM_WIDTH" value="1" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS" value="2500" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="AFI_WRANK_WIDTH" value="2" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="2500" />
|
|
<parameter name="LRDIMM" value="false" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="2500" />
|
|
<parameter name="MR1_DLL" value="0" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
|
|
<parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
|
|
<parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PHY_CLKBUF" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="SEQUENCER_TYPE" value="NIOS" />
|
|
<parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
|
|
<parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="MEM_IF_CHIP_BITS" value="1" />
|
|
<parameter name="VFIFO_AS_SHIFT_REG" value="true" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
|
|
<parameter name="MEM_IF_CK_WIDTH" value="1" />
|
|
<parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
|
|
<parameter name="MEM_TCL" value="5" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
|
|
<parameter name="TIMING_TDQSCK" value="225" />
|
|
<parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
|
|
<parameter name="DLL_SHARING_MODE" value="None" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="2500" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="PLL_DR_CLK_MULT" value="0" />
|
|
<parameter name="USE_USER_RDIMM_VALUE" value="false" />
|
|
<parameter name="MEM_FORMAT" value="DISCRETE" />
|
|
<parameter name="AFI_RATE_RATIO" value="2" />
|
|
<parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
|
|
<parameter name="PLL_MEM_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="CFG_TCCD_NS" value="2.5" />
|
|
<parameter name="IO_DQS_IN_RESERVE" value="3" />
|
|
<parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="AFI_WLAT_WIDTH" value="6" />
|
|
<parameter name="ENABLE_NIOS_OCI" value="false" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="FIX_READ_LATENCY" value="8" />
|
|
<parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
|
|
<parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
|
|
<parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
|
|
<parameter name="RATE_CACHE" value="Unknown" />
|
|
<parameter name="COMMAND_PHASE" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT" value="3" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
|
|
<parameter name="MR1_ODS" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="MEM_TRFC" value="34" />
|
|
<parameter name="PHY_CSR_ENABLED" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="DQ_DDR" value="1" />
|
|
<parameter name="PLL_WRITE_CLK_MULT_PARAM" value="3" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_DEG" value="270.0" />
|
|
<parameter name="MEM_INIT_FILE" value="" />
|
|
<parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="MEM_CK_PHASE" value="0.0" />
|
|
<parameter name="FORCE_DQS_TRACKING" value="AUTO" />
|
|
<parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="0.02286" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
|
|
<parameter name="TB_RATE" value="HALF" />
|
|
<parameter name="REF_CLK_FREQ_CACHE_VALID" value="true" />
|
|
<parameter name="MEM_CK_WIDTH" value="1" />
|
|
<parameter name="MEM_ATCL" value="Disabled" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="DISABLE_CHILD_MESSAGING" value="true" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
|
|
<parameter name="MEM_TDQSCK" value="1" />
|
|
<parameter name="MEM_VERBOSE" value="true" />
|
|
<parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
|
|
<parameter name="HARD_PHY" value="false" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="MR2_SRF" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
|
|
<parameter name="REF_CLK_FREQ_MIN_PARAM" value="10.0" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="MEM_WTCL" value="5" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="PLL_MEM_CLK_MULT" value="3" />
|
|
<parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="MEM_IF_CS_PER_DIMM" value="1" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="VCALIB_COUNT_WIDTH" value="2" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
|
|
<parameter name="OCT_TERM_CONTROL_WIDTH" value="14" />
|
|
<parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
|
|
<parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="DLL_USE_DR_CLK" value="false" />
|
|
<parameter name="AC_PARITY" value="false" />
|
|
<parameter name="PLL_WRITE_CLK_DIV" value="1" />
|
|
<parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
|
|
<parameter name="MR1_DQS" value="0" />
|
|
<parameter name="MR2_SRT" value="0" />
|
|
<parameter name="CALIB_VFIFO_OFFSET" value="12" />
|
|
<parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="3" />
|
|
<parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
|
|
<parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
|
|
<parameter name="MR1_QOFF" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="MEM_DRV_STR" value="RZQ/6" />
|
|
<parameter name="MEM_TREFI" value="2341" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
|
|
<parameter name="TB_MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="NUM_SUBGROUP_PER_READ_DQS" value="1" />
|
|
<parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_PARAM" value="150.0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="2500" />
|
|
<parameter name="MEM_TRP_NS" value="13.75" />
|
|
<parameter name="DLL_DELAY_CTRL_WIDTH" value="6" />
|
|
<parameter name="QVLD_EXTRA_FLOP_STAGES" value="0" />
|
|
<parameter name="MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="MEM_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ" value="300.0" />
|
|
<parameter name="USE_FAKE_PHY" value="false" />
|
|
<parameter name="EXTRA_SETTINGS" value="" />
|
|
<parameter name="PLL_DR_CLK_FREQ_STR" value="" />
|
|
<parameter name="SEQ_MODE" value="0" />
|
|
<parameter name="MEM_IF_CS_WIDTH" value="1" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
|
|
<parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="MEM_TYPE" value="DDR3" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="REF_CLK_PS" value="10000.0" />
|
|
<parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="false" />
|
|
<parameter name="SEQUENCER_TYPE_CACHE" value="Unknown" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="MR0_BT" value="0" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
|
|
<parameter name="MR1_AL" value="0" />
|
|
<parameter name="DQS_PHASE_SHIFT" value="9000" />
|
|
<parameter name="MR0_BL" value="1" />
|
|
<parameter name="MARGIN_VARIATION_TEST" value="false" />
|
|
<parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
|
|
<parameter name="TIMING_TIS" value="170" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
|
|
<parameter name="MEM_TRCD" value="5" />
|
|
<parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
|
|
<parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
|
|
<parameter name="IO_IN_DELAY_MAX" value="15" />
|
|
<parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
|
|
<parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="REGISTER_C2P" value="false" />
|
|
<parameter name="FAST_SIM_CALIBRATION" value="false" />
|
|
<parameter name="MEM_WTCL_INT" value="5" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
|
|
<parameter name="DQS_EN_DELAY_MAX" value="7" />
|
|
<parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="0 ps" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="DELAY_BUFFER_MODE" value="HIGH" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
|
|
<parameter name="REF_CLK_FREQ" value="100.0" />
|
|
<parameter name="AFI_RRANK_WIDTH" value="2" />
|
|
<parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV" value="0" />
|
|
<parameter name="MR0_DLL" value="1" />
|
|
<parameter name="FORCE_SHADOW_REGS" value="AUTO" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PINGPONGPHY_EN" value="false" />
|
|
<parameter name="MR3_MPR" value="0" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="6668 ps" />
|
|
<parameter name="MR2_ASR" value="0" />
|
|
<parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
|
|
<parameter name="MR2_CWL" value="0" />
|
|
<parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV" value="1" />
|
|
<parameter name="HPS_PROTOCOL" value="DEFAULT" />
|
|
<parameter name="MEM_IF_LRDIMM_RM" value="0" />
|
|
<parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="MEM_IF_ODT_WIDTH" value="1" />
|
|
<parameter name="TIMING_TDQSCKDL" value="1200" />
|
|
<parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="TIMING_TDQSCKDS" value="450" />
|
|
<parameter name="TIMING_TDQSCKDM" value="900" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="TIMING_BOARD_TIS" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="DUPLICATE_AC" value="false" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="NIOS_HEX_FILE_LOCATION" value="../" />
|
|
<parameter name="DUAL_WRITE_CLOCK" value="false" />
|
|
<parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="0 ps" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
|
|
<parameter name="TIMING_BOARD_TIH" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_MULT" value="3" />
|
|
<parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
|
|
<parameter name="REF_CLK_FREQ_PARAM_VALID" value="true" />
|
|
<parameter name="PLL_MEM_CLK_DIV_PARAM" value="1" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="TIMING_BOARD_TDS" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
|
|
<parameter name="AFI_BANKADDR_WIDTH" value="6" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="TIMING_BOARD_TDH" value="0.0" />
|
|
<parameter name="PACKAGE_DESKEW" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="TRACKING_WATCH_TEST" value="false" />
|
|
<parameter name="MEM_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
|
|
<parameter name="AFI_DM_WIDTH" value="4" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV" value="0" />
|
|
<parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
|
|
<parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
|
|
<parameter name="USE_SHADOW_REGS" value="false" />
|
|
<parameter name="REF_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="TRACKING_ERROR_TEST" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="REF_CLK_FREQ_STR" value="100.0 MHz" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
|
|
<parameter name="PLL_MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="MEM_IF_DQ_WIDTH" value="8" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
|
|
<parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
|
|
<parameter name="MR1_RTT" value="0" />
|
|
<parameter name="PLL_MEM_CLK_MULT_PARAM" value="3" />
|
|
<parameter name="READ_FIFO_HALF_RATE" value="true" />
|
|
<parameter name="ADDR_CMD_DDR" value="0" />
|
|
<parameter name="GENERIC_PLL" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
|
|
<parameter name="ENABLE_NON_DES_CAL" value="false" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
|
|
<parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
|
|
<parameter name="MR3_MPR_AA" value="0" />
|
|
<parameter name="CSR_DATA_WIDTH" value="32" />
|
|
<parameter name="MEM_DLL_EN" value="true" />
|
|
<parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
|
|
<parameter name="IS_ES_DEVICE" value="false" />
|
|
<parameter name="PRE_V_SERIES_FAMILY" value="false" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="MEM_TFAW_NS" value="30.0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="1" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ" value="300.0" />
|
|
<parameter name="HHP_HPS_SIMULATION" value="false" />
|
|
<parameter name="REF_CLK_NS" value="10.0" />
|
|
<parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="IO_OUT2_DELAY_MAX" value="7" />
|
|
<parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
|
|
<parameter name="AFI_CLK_EN_WIDTH" value="2" />
|
|
<parameter name="TIMING_TQH" value="0.38" />
|
|
<parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_CLK_CACHE_VALID" value="true" />
|
|
<parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
|
|
<parameter name="PLL_MEM_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="HCX_COMPAT_MODE" value="false" />
|
|
<parameter name="PLL_HR_CLK_MULT" value="0" />
|
|
<parameter name="MEM_IF_DQSN_EN" value="true" />
|
|
<parameter name="AC_ROM_MR0" value="0001000010001" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="HHP_HPS" value="false" />
|
|
<parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_TRAS" value="11" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="MEM_TINIT_US" value="500" />
|
|
<parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
|
|
<parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="DAT_DATA_WIDTH" value="32" />
|
|
<parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
|
|
<parameter name="CALIBRATION_MODE" value="Skip" />
|
|
<parameter name="AC_ROM_MR1_CALIB" value="" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
|
|
<parameter name="PLL_MEM_CLK_DIV" value="1" />
|
|
<parameter name="SPEED_GRADE" value="6" />
|
|
<parameter name="OCT_SHARING_MODE" value="None" />
|
|
<parameter name="AC_ROM_MR2" value="0000000000000" />
|
|
<parameter name="AC_ROM_MR1" value="0000000000000" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV" value="0" />
|
|
<parameter name="AC_ROM_MR3" value="0000000000000" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="MEM_TRCD_NS" value="13.75" />
|
|
<parameter name="USE_HARD_READ_FIFO" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
|
|
<parameter name="AFI_ADDR_WIDTH" value="28" />
|
|
<parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
|
|
<parameter name="PHY_VERSION_NUMBER" value="191" />
|
|
<parameter name="MEM_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="TIMING_BOARD_TIH_APPLIED" value="0.22" />
|
|
<parameter name="USE_HPS_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="MEM_SRT" value="Normal" />
|
|
<parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
|
|
<parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
|
|
<parameter name="EXPORT_CSR_PORT" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="2500 ps" />
|
|
<parameter name="PLL_WRITE_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="EXTRA_VFIFO_SHIFT" value="0" />
|
|
<parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
|
|
<parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="TIMING_TDS" value="10" />
|
|
<parameter name="PLL_CLK_PARAM_VALID" value="true" />
|
|
<parameter name="MEM_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="CFG_TCCD" value="1" />
|
|
<parameter name="MEM_CS_WIDTH" value="1" />
|
|
<parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
|
|
<parameter name="TIMING_TDH" value="45" />
|
|
<parameter name="DELAY_CHAIN_LENGTH" value="8" />
|
|
<parameter name="SCC_DATA_WIDTH" value="1" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ" value="300.0" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="MEM_TREFI_US" value="7.8" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_WRITE_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="USE_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_LRDIMM_ENABLED" value="false" />
|
|
<parameter name="TIMING_BOARD_TIS_APPLIED" value="0.32" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.04429" />
|
|
<parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
|
|
<parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="AC_ROM_MR0_CALIB" value="" />
|
|
<parameter name="MEM_TWR_NS" value="15.0" />
|
|
<parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="MEM_T_WL" value="5" />
|
|
<parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
|
|
<parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="AFI_RLAT_WIDTH" value="6" />
|
|
<parameter name="MEM_TRP" value="5" />
|
|
<parameter name="MEM_CLK_PS" value="3333.0" />
|
|
<parameter name="IS_ES_DEVICE_CACHE" value="false" />
|
|
<parameter name="PLL_AFI_CLK_FREQ" value="150.0" />
|
|
<parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="MEM_TMRD_CK" value="4" />
|
|
<parameter name="MEM_TRRD_NS" value="6.0" />
|
|
<parameter name="IO_OUT1_DELAY_MAX" value="15" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="270.0" />
|
|
<parameter name="DEVICE_DEPTH" value="1" />
|
|
<parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_MULT" value="3" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="DQS_IN_DELAY_MAX" value="15" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="AC_PACKAGE_DESKEW" value="false" />
|
|
<parameter name="MR0_CAS_LATENCY" value="1" />
|
|
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.0" />
|
|
<parameter name="MR0_WR" value="1" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
|
|
<parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
|
|
<parameter name="SEQ_BURST_COUNT_WIDTH" value="1" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="PHY_ONLY" value="false" />
|
|
<parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="false" />
|
|
<parameter name="TRFC" value="350" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="IO_STANDARD" value="SSTL-15" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="TIMING_TDQSS" value="0.27" />
|
|
<parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
|
|
<parameter name="TIMING_TDQSQ" value="100" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="SPEED_GRADE_CACHE" value="" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_CACHE" value="150.0" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="READ_FIFO_SIZE" value="8" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
|
|
<parameter name="USE_2X_FF" value="false" />
|
|
<parameter name="MEM_ASR" value="Manual" />
|
|
<parameter name="PLL_DR_CLK_FREQ" value="0.0" />
|
|
<parameter name="TB_MEM_IF_DQ_WIDTH" value="8" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
|
|
<parameter name="NEGATIVE_WRITE_CK_PHASE" value="true" />
|
|
<parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="ADVANCED_CK_PHASES" value="false" />
|
|
<parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
|
|
<parameter name="NEXTGEN" value="true" />
|
|
<parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
|
|
<parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
|
|
<parameter name="MEM_ATCL_INT" value="0" />
|
|
<parameter name="MEM_T_RL" value="5" />
|
|
<parameter name="MEM_TWR" value="5" />
|
|
<parameter name="USE_DR_CLK" value="false" />
|
|
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="2500" />
|
|
<parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
|
|
<parameter name="ENABLE_EMIT_JTAG_MASTER" value="false" />
|
|
<parameter name="MEM_IF_DQS_WIDTH" value="1" />
|
|
<parameter name="TIMING_TDSS" value="0.18" />
|
|
<parameter name="TIMING_TIH" value="120" />
|
|
<parameter name="CSR_BE_WIDTH" value="4" />
|
|
<parameter name="PLL_LOCATION" value="Top_Bottom" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="2500 ps" />
|
|
<parameter name="MEM_TRTP_NS" value="7.5" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="PLL_SHARING_MODE" value="None" />
|
|
<parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
|
|
<parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="2500" />
|
|
<parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
|
|
<parameter name="AP_MODE" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="false" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
|
|
<parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
|
|
<parameter name="MEM_PD" value="DLL off" />
|
|
<parameter name="MAX10_RTL_SEQ" value="true" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="TIMING_TDSH" value="0.18" />
|
|
<parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
|
|
<parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
|
|
<parameter name="REF_CLK_FREQ_MAX_CACHE" value="500.0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_AFI_CLK_DIV" value="2" />
|
|
<parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
|
|
<parameter name="MEM_TFAW" value="10" />
|
|
<parameter name="MEM_DQ_WIDTH" value="8" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_clock_pair_generator.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_valid_selector.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_datapath.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_m10.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_memphy_m10.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_dqdqs_pads_m10.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_reset_sync.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_fr_cycle_shifter.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_read_datapath_m10.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_write_datapath_m10.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_simple_ddio_out_m10.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/max10emif_dcfifo.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_iss_probe.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_addr_cmd_pads_m10.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_flop_mem.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.ppf"
|
|
type="OTHER"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0.sdc"
|
|
type="SDC"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_timing.tcl"
|
|
type="OTHER"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_report_timing.tcl"
|
|
type="OTHER"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_report_timing_core.tcl"
|
|
type="OTHER"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_pin_map.tcl"
|
|
type="OTHER"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_pin_assignments.tcl"
|
|
type="OTHER"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_p0_parameters.tcl"
|
|
type="OTHER"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_phys/alt_mem_if_ddr3_phy_core/altera_mem_if_ddr3_phy_core_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_ddr3_ram" as="p0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 231 starting:altera_mem_if_ddr3_phy_core "submodules/q_sys_ddr3_ram_p0"</message>
|
|
<message level="Info" culprit="p0">Generating clock pair generator</message>
|
|
<message level="Info" culprit="p0">Generating altgpio</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0">*****************************</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0">Remember to run the q_sys_ddr3_ram_p0_pin_assignments.tcl</message>
|
|
<message level="Info" culprit="p0">script after running Synthesis and before Fitting.</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0">*****************************</message>
|
|
<message level="Info" culprit="p0"></message>
|
|
<message level="Info" culprit="p0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_mem_if_ddr3_afi_mux:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,CFG_TCCD=1,CFG_TCCD_NS=2.5,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,IS_ES_DEVICE=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEXTGEN=true,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,PRE_V_SERIES_FAMILY=false,RATE=Half,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SPEED_GRADE=6,SYS_INFO_DEVICE_FAMILY=MAX 10,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false"
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instancePathKey="q_sys:.:ddr3_ram:.:m0"
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kind="altera_mem_if_ddr3_afi_mux"
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version="19.1"
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name="afi_mux_ddr3_ddrx">
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<parameter name="LRDIMM_INT" value="0" />
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<parameter name="MEM_IF_CS_WIDTH" value="1" />
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<parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
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<parameter name="MEM_TYPE" value="DDR3" />
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<parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
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<parameter name="MEM_LEVELING" value="true" />
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<parameter name="FLY_BY" value="true" />
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<parameter name="TIMING_TQSH" value="0.4" />
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<parameter name="AFI_CLK_PAIR_COUNT" value="1" />
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<parameter name="HARD_EMIF" value="false" />
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<parameter name="MR0_BT" value="0" />
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<parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
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<parameter name="MR1_AL" value="0" />
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<parameter name="MEM_REGDIMM_ENABLED" value="false" />
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<parameter name="MEM_CLK_MAX_NS" value="1.25" />
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<parameter name="MR0_BL" value="1" />
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<parameter name="TIMING_TIS" value="170" />
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<parameter name="AFI_DQ_WIDTH" value="32" />
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<parameter name="MEM_TRCD" value="5" />
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<parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
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<parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
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<parameter name="MEM_WTCL_INT" value="5" />
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<parameter name="AP_MODE_EN" value="0" />
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<parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
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<parameter name="MEM_TINIT_CK" value="150000" />
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<parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
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<parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
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<parameter name="MEM_BL" value="OTF" />
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<parameter name="MEM_TRAS_NS" value="35.0" />
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<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
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<parameter name="MEM_BT" value="Sequential" />
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<parameter name="AFI_RRANK_WIDTH" value="2" />
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<parameter name="MEM_TRTP" value="3" />
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<parameter name="MR0_DLL" value="1" />
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<parameter name="FORCE_SHADOW_REGS" value="AUTO" />
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<parameter name="HHP_HPS_VERIFICATION" value="false" />
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<parameter name="MEM_DQ_PER_DQS" value="8" />
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<parameter name="PINGPONGPHY_EN" value="false" />
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<parameter name="MR3_MPR" value="0" />
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<parameter name="MR2_ASR" value="0" />
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<parameter name="MR2_CWL" value="0" />
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<parameter name="HPS_PROTOCOL" value="DEFAULT" />
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<parameter name="RDIMM_CONFIG" value="0000000000000000" />
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<parameter name="MEM_IF_LRDIMM_RM" value="0" />
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<parameter name="MEM_IF_ODT_WIDTH" value="1" />
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<parameter name="TIMING_TDQSCKDL" value="1200" />
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<parameter name="TIMING_TDQSCKDS" value="450" />
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<parameter name="TIMING_TDQSCKDM" value="900" />
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<parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
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<parameter name="MR1_RDQS" value="0" />
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<parameter name="DUPLICATE_AC" value="false" />
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<parameter name="DEVICE_WIDTH" value="1" />
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<parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
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<parameter name="MR0_PD" value="0" />
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<parameter name="MEM_VENDOR" value="JEDEC" />
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<parameter name="MEM_IF_CS_PER_RANK" value="1" />
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<parameter name="AFI_CONTROL_WIDTH" value="2" />
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<parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
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<parameter name="MEM_IF_DM_PINS_EN" value="true" />
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<parameter name="USE_MEM_CLK_FREQ" value="false" />
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<parameter name="AFI_BANKADDR_WIDTH" value="6" />
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<parameter name="RDIMM" value="false" />
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<parameter name="MEM_COL_ADDR_WIDTH" value="10" />
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<parameter name="AFI_DM_WIDTH" value="4" />
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<parameter name="MEM_TRC" value="15" />
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<parameter name="DATA_RATE_RATIO" value="2" />
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<parameter name="AFI_CS_WIDTH" value="2" />
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<parameter name="USE_SHADOW_REGS" value="false" />
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<parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
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<parameter name="MEM_IF_DQ_WIDTH" value="8" />
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<parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
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<parameter name="MR1_RTT" value="0" />
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<parameter name="ADDR_CMD_DDR" value="0" />
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<parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
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<parameter name="MR1_TDQS" value="0" />
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<parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
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<parameter name="MR3_MPR_AA" value="0" />
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<parameter name="MEM_DLL_EN" value="true" />
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<parameter name="IS_ES_DEVICE" value="false" />
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<parameter name="PRE_V_SERIES_FAMILY" value="false" />
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<parameter name="RATE" value="Half" />
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<parameter name="MEM_TFAW_NS" value="30.0" />
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<parameter name="DEVICE_FAMILY" value="MAX 10" />
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<parameter name="MR1_WL" value="0" />
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<parameter name="REFRESH_BURST_VALIDATION" value="false" />
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<parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
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<parameter name="HHP_HPS_SIMULATION" value="false" />
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<parameter name="MR3_MPR_RF" value="0" />
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<parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
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<parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
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<parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
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<parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
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<parameter name="AFI_CLK_EN_WIDTH" value="2" />
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<parameter name="TIMING_TQH" value="0.38" />
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<parameter name="MEM_IF_ADDR_WIDTH" value="14" />
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<parameter name="MEM_CLK_MAX_PS" value="1250.0" />
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<parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
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<parameter name="MEM_IF_DQSN_EN" value="true" />
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<parameter name="AC_ROM_MR0" value="0001000010001" />
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<parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
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<parameter name="HHP_HPS" value="false" />
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<parameter name="MEM_BURST_LENGTH" value="8" />
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<parameter name="MEM_TRAS" value="11" />
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<parameter name="MEM_TRRD" value="2" />
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<parameter name="MEM_MIRROR_ADDRESSING" value="0" />
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<parameter name="RDIMM_INT" value="0" />
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<parameter name="MEM_TINIT_US" value="500" />
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<parameter name="DAT_DATA_WIDTH" value="32" />
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<parameter name="AC_ROM_MR1_CALIB" value="" />
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<parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
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<parameter name="MEM_TWTR" value="6" />
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<parameter name="MEM_INIT_EN" value="false" />
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<parameter name="SPEED_GRADE" value="6" />
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<parameter name="MEM_TRFC_NS" value="110.0" />
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<parameter name="ADDR_RATE_RATIO" value="1" />
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<parameter name="AC_ROM_MR2" value="0000000000000" />
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<parameter name="AC_ROM_MR1" value="0000000000000" />
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<parameter name="AC_ROM_MR3" value="0000000000000" />
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<parameter name="MR2_RTT_WR" value="0" />
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<parameter name="MEM_TRCD_NS" value="13.75" />
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<parameter name="AFI_ODT_WIDTH" value="2" />
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<parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
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<parameter name="AFI_ADDR_WIDTH" value="28" />
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<parameter name="DISCRETE_FLY_BY" value="true" />
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<parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
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<parameter name="MEM_RTT_NOM" value="ODT Disabled" />
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<parameter name="MEM_BANKADDR_WIDTH" value="3" />
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<parameter name="USE_HPS_DQS_TRACKING" value="false" />
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<parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
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<parameter name="MEM_SRT" value="Normal" />
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<parameter name="MEM_IF_DM_WIDTH" value="1" />
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<parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
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<parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
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<parameter name="AFI_WRANK_WIDTH" value="2" />
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<parameter name="LRDIMM" value="false" />
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<parameter name="MR1_DLL" value="0" />
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<parameter name="TIMING_TDS" value="10" />
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<parameter name="CFG_TCCD" value="1" />
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<parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
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<parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
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<parameter name="MEM_CS_WIDTH" value="1" />
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<parameter name="MEM_IF_CHIP_BITS" value="1" />
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<parameter name="TIMING_TDH" value="45" />
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<parameter name="SCC_DATA_WIDTH" value="1" />
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<parameter name="MEM_IF_CK_WIDTH" value="1" />
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<parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
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<parameter name="MEM_TREFI_US" value="7.8" />
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<parameter name="USE_DQS_TRACKING" value="false" />
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<parameter name="MEM_LRDIMM_ENABLED" value="false" />
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<parameter name="MEM_TCL" value="5" />
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<parameter name="TIMING_TDQSCK" value="225" />
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<parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
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<parameter name="AC_ROM_MR0_CALIB" value="" />
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<parameter name="MEM_TWR_NS" value="15.0" />
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<parameter name="MEM_FORMAT" value="DISCRETE" />
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<parameter name="AFI_RATE_RATIO" value="2" />
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<parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
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<parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
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<parameter name="AFI_RLAT_WIDTH" value="6" />
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<parameter name="MEM_TRP" value="5" />
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<parameter name="CFG_TCCD_NS" value="2.5" />
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<parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
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<parameter name="AFI_WLAT_WIDTH" value="6" />
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<parameter name="MEM_TMRD_CK" value="4" />
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<parameter name="MEM_TRRD_NS" value="6.0" />
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<parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
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<parameter name="DEVICE_DEPTH" value="1" />
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<parameter name="MR1_ODS" value="0" />
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<parameter name="MEM_TRFC" value="34" />
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<parameter name="DQ_DDR" value="1" />
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<parameter name="MR0_CAS_LATENCY" value="1" />
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<parameter name="MEM_INIT_FILE" value="" />
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<parameter name="MR0_WR" value="1" />
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<parameter name="FORCE_DQS_TRACKING" value="AUTO" />
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<parameter name="MEM_CK_WIDTH" value="1" />
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<parameter name="MEM_ATCL" value="Disabled" />
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<parameter name="TIMING_TDQSS" value="0.27" />
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<parameter name="TIMING_TDQSQ" value="100" />
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<parameter name="DISABLE_CHILD_MESSAGING" value="true" />
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<parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
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<parameter name="MEM_TDQSCK" value="1" />
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<parameter name="MEM_VERBOSE" value="true" />
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<parameter name="HARD_PHY" value="false" />
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<parameter name="MR2_SRF" value="0" />
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<parameter name="MEM_ASR" value="Manual" />
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<parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
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<parameter name="NEXTGEN" value="true" />
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<parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
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<parameter name="MEM_ATCL_INT" value="0" />
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<parameter name="MEM_WTCL" value="5" />
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<parameter name="MEM_TWR" value="5" />
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<parameter name="MEM_IF_CS_PER_DIMM" value="1" />
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<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
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<parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
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<parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
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<parameter name="MEM_IF_DQS_WIDTH" value="1" />
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<parameter name="TIMING_TDSS" value="0.18" />
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<parameter name="TIMING_TIH" value="120" />
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<parameter name="AC_PARITY" value="false" />
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<parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
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<parameter name="MR1_DQS" value="0" />
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<parameter name="MEM_TRTP_NS" value="7.5" />
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<parameter name="MR2_SRT" value="0" />
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<parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
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<parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
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<parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
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<parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
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<parameter name="AP_MODE" value="false" />
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<parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
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<parameter name="MR1_QOFF" value="0" />
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<parameter name="MEM_DRV_STR" value="RZQ/6" />
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<parameter name="MEM_TREFI" value="2341" />
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<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
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<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
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<parameter name="MEM_PD" value="DLL off" />
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<parameter name="TIMING_TDSH" value="0.18" />
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<parameter name="MEM_TRP_NS" value="13.75" />
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<parameter name="MEM_CLK_FREQ" value="300.0" />
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<parameter name="MEM_CLK_EN_WIDTH" value="1" />
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<parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
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<parameter name="MEM_TFAW" value="10" />
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<parameter name="MEM_DQ_WIDTH" value="8" />
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<generatedFiles>
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/afi_mux_ddr3_ddrx.v"
|
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type="VERILOG"
|
|
attributes="" />
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</generatedFiles>
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/altera_mem_if_afi_muxes/altera_mem_if_ddr3_afi_mux/altera_mem_if_ddr3_afi_mux_hw.tcl" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
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<file
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|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
|
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
|
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<file
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
|
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
|
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
|
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_ddr3_ram" as="m0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 230 starting:altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx"</message>
|
|
<message level="Info" culprit="m0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_mem_if_ddr3_qseq:19.1:ABSTRACT_REAL_COMPARE_TEST=false,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_RATE_RATIO=1,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_MAX_READ_LATENCY_COUNT_WIDTH=6,AFI_MAX_WRITE_LATENCY_COUNT_WIDTH=6,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AVL_ADDR_WIDTH=13,AVL_DATA_WIDTH=32,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=4,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=12,CFG_TCCD=1,CFG_TCCD_NS=2.5,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CUT_NEW_FAMILY_TIMING=true,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=50,DELAY_PER_DQS_EN_DCHAIN_TAP=50,DELAY_PER_OPA_TAP=416,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 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off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_T_RL=5,MEM_T_WL=5,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=1,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=191,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=1,PLL_ADDR_CMD_CLK_DIV_CACHE=1,PLL_ADDR_CMD_CLK_DIV_PARAM=1,PLL_ADDR_CMD_CLK_FREQ=300.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=300.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=300.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_ADDR_CMD_CLK_FREQ_STR=300.0 MHz,PLL_ADDR_CMD_CLK_MULT=3,PLL_ADDR_CMD_CLK_MULT_CACHE=3,PLL_ADDR_CMD_CLK_MULT_PARAM=3,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_ADDR_CMD_CLK_PHASE_PS_STR=0 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=2,PLL_AFI_CLK_FREQ=150.0,PLL_AFI_CLK_FREQ_CACHE=150.0,PLL_AFI_CLK_FREQ_PARAM=150.0,PLL_AFI_CLK_FREQ_SIM_STR=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=6668 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=6668 ps,PLL_AFI_CLK_FREQ_STR=150.0 MHz,PLL_AFI_CLK_MULT=3,PLL_AFI_CLK_MULT_CACHE=3,PLL_AFI_CLK_MULT_PARAM=3,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=1,PLL_AFI_HALF_CLK_DIV_CACHE=1,PLL_AFI_HALF_CLK_DIV_PARAM=1,PLL_AFI_HALF_CLK_FREQ=300.0,PLL_AFI_HALF_CLK_FREQ_CACHE=300.0,PLL_AFI_HALF_CLK_FREQ_PARAM=300.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_AFI_HALF_CLK_FREQ_STR=300.0 MHz,PLL_AFI_HALF_CLK_MULT=3,PLL_AFI_HALF_CLK_MULT_CACHE=3,PLL_AFI_HALF_CLK_MULT_PARAM=3,PLL_AFI_HALF_CLK_PHASE_DEG=270.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=270.0,PLL_AFI_HALF_CLK_PHASE_PS=2500,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=2500,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM=2500,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_AFI_HALF_CLK_PHASE_PS_STR=2500 ps,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=0 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=true,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=0 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=1,PLL_MEM_CLK_DIV_CACHE=1,PLL_MEM_CLK_DIV_PARAM=1,PLL_MEM_CLK_FREQ=300.0,PLL_MEM_CLK_FREQ_CACHE=300.0,PLL_MEM_CLK_FREQ_PARAM=300.0,PLL_MEM_CLK_FREQ_SIM_STR=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_MEM_CLK_FREQ_STR=300.0 MHz,PLL_MEM_CLK_MULT=3,PLL_MEM_CLK_MULT_CACHE=3,PLL_MEM_CLK_MULT_PARAM=3,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=0 ps,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=0 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=1,PLL_WRITE_CLK_DIV_CACHE=1,PLL_WRITE_CLK_DIV_PARAM=1,PLL_WRITE_CLK_FREQ=300.0,PLL_WRITE_CLK_FREQ_CACHE=300.0,PLL_WRITE_CLK_FREQ_PARAM=300.0,PLL_WRITE_CLK_FREQ_SIM_STR=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=3334 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=3334 ps,PLL_WRITE_CLK_FREQ_STR=300.0 MHz,PLL_WRITE_CLK_MULT=3,PLL_WRITE_CLK_MULT_CACHE=3,PLL_WRITE_CLK_MULT_PARAM=3,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=2500,PLL_WRITE_CLK_PHASE_PS_CACHE=2500,PLL_WRITE_CLK_PHASE_PS_PARAM=2500,PLL_WRITE_CLK_PHASE_PS_SIM=2500,PLL_WRITE_CLK_PHASE_PS_SIM_STR=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=2500 ps,PLL_WRITE_CLK_PHASE_PS_STR=2500 ps,PRE_V_SERIES_FAMILY=false,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=4,RATE=Half,RATE_CACHE=Unknown,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=true,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=100.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=500.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=10.0,REF_CLK_FREQ_PARAM_VALID=true,REF_CLK_FREQ_STR=100.0 MHz,REF_CLK_NS=10.0,REF_CLK_PS=10000.0,REGISTER_C2P=false,SCC_DATA_WIDTH=1,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=1,SEQ_MODE=0,SKIP_MEM_INIT=true,SPEED_GRADE=6,SPEED_GRADE_CACHE=,SYS_INFO_DEVICE_FAMILY=MAX 10,TB_MEM_CLK_FREQ=300.0,TB_MEM_IF_DQ_WIDTH=8,TB_MEM_IF_READ_DQS_WIDTH=1,TB_PLL_DLL_MASTER=true,TB_RATE=HALF,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.07801,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=-0.04709,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=-0.01152,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.2443,TIMING_BOARD_MAX_DQS_DELAY=0.21929,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.04246,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.04429,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.02286,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.02286,TIMING_BOARD_SKEW_WITHIN_DQS=0.01806,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.145,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.16,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.22,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.32,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VFIFO_AS_SHIFT_REG=true"
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instancePathKey="q_sys:.:ddr3_ram:.:s0"
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kind="altera_mem_if_ddr3_qseq"
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version="19.1"
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name="q_sys_ddr3_ram_s0">
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<parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
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<parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
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<parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
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<parameter name="LRDIMM_INT" value="0" />
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<parameter name="MAX_LATENCY_COUNT_WIDTH" value="5" />
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<parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
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<parameter name="PLL_AFI_CLK_MULT_PARAM" value="3" />
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<parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
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<parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
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<parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
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<parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
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<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
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<parameter name="MEM_LEVELING" value="true" />
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<parameter name="FLY_BY" value="false" />
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<parameter name="TIMING_TQSH" value="0.4" />
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<parameter name="PLL_AFI_HALF_CLK_DIV" value="1" />
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<parameter name="PLL_AFI_PHY_CLK_FREQ" value="0.0" />
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<parameter name="AFI_CLK_PAIR_COUNT" value="1" />
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<parameter name="HARD_EMIF" value="false" />
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<parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
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<parameter name="MEM_REGDIMM_ENABLED" value="false" />
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<parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
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<parameter name="MEM_CLK_MAX_NS" value="1.25" />
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<parameter name="REF_CLK_FREQ_MAX_PARAM" value="500.0" />
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<parameter name="PLL_AFI_CLK_DIV_PARAM" value="2" />
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<parameter name="CALIB_REG_WIDTH" value="8" />
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<parameter name="PLL_HR_CLK_FREQ" value="0.0" />
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<parameter name="AFI_DQ_WIDTH" value="32" />
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<parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
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<parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
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<parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
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<parameter name="AP_MODE_EN" value="0" />
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<parameter name="MEM_TINIT_CK" value="150000" />
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<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
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<parameter name="CALIB_LFIFO_OFFSET" value="4" />
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<parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
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<parameter name="IO_DQS_OUT_RESERVE" value="3" />
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<parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
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<parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
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<parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
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<parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
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<parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
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<parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="0 ps" />
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<parameter name="MEM_BL" value="OTF" />
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<parameter name="MEM_TRAS_NS" value="35.0" />
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<parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
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<parameter name="ENABLE_EXTRA_REPORTING" value="false" />
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<parameter name="IO_DQ_OUT_RESERVE" value="0" />
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<parameter name="IO_DM_OUT_RESERVE" value="0" />
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<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
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<parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
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<parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
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<parameter name="MEM_BT" value="Sequential" />
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<parameter name="DELAY_PER_OPA_TAP" value="416" />
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<parameter name="MEM_TRTP" value="3" />
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<parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
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<parameter name="TREFI" value="35100" />
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<parameter name="HHP_HPS_VERIFICATION" value="false" />
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<parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="PLL_AFI_CLK_DIV_CACHE" value="2" />
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<parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="1" />
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<parameter name="MEM_DQ_PER_DQS" value="8" />
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<parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="2" />
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<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="2500" />
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<parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
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<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
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<parameter name="RDIMM_CONFIG" value="0000000000000000" />
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<parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.04246" />
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<parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="0.0" />
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<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
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<parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
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<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
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<parameter name="AVL_DATA_WIDTH" value="32" />
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<parameter name="PLL_AFI_CLK_MULT_CACHE" value="3" />
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<parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
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<parameter name="MR1_RDQS" value="0" />
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<parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
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<parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="1" />
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<parameter name="DEVICE_WIDTH" value="1" />
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<parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
|
|
<parameter name="MR0_PD" value="0" />
|
|
<parameter name="MEM_VENDOR" value="JEDEC" />
|
|
<parameter name="PLL_HR_CLK_FREQ_STR" value="" />
|
|
<parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
|
|
<parameter name="MEM_IF_CS_PER_RANK" value="1" />
|
|
<parameter name="COMMAND_PHASE_CACHE" value="0.0" />
|
|
<parameter name="AFI_CONTROL_WIDTH" value="2" />
|
|
<parameter name="PLL_HR_CLK_DIV" value="0" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="REF_CLK_FREQ_MIN_CACHE" value="10.0" />
|
|
<parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
|
|
<parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="0 ps" />
|
|
<parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
|
|
<parameter name="MEM_IF_DM_PINS_EN" value="true" />
|
|
<parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
|
|
<parameter name="USE_MEM_CLK_FREQ" value="false" />
|
|
<parameter name="MEM_DEVICE" value="MISSING_MODEL" />
|
|
<parameter name="IO_DQS_EN_PHASE_MAX" value="7" />
|
|
<parameter name="USER_DEBUG_LEVEL" value="1" />
|
|
<parameter name="RDIMM" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ" value="0.0" />
|
|
<parameter name="PLL_PHASE_COUNTER_WIDTH" value="4" />
|
|
<parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="-0.04709" />
|
|
<parameter name="MEM_TRC" value="15" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="6668 ps" />
|
|
<parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
|
|
<parameter name="DATA_RATE_RATIO" value="2" />
|
|
<parameter name="AFI_CS_WIDTH" value="2" />
|
|
<parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_MULT" value="0" />
|
|
<parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
|
|
<parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
|
|
<parameter name="MEM_CLK_NS" value="3.333" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="270.0" />
|
|
<parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
|
|
<parameter name="PLL_AFI_CLK_MULT" value="3" />
|
|
<parameter name="SKIP_MEM_INIT" value="true" />
|
|
<parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="MR1_TDQS" value="0" />
|
|
<parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="1" />
|
|
<parameter name="AFI_MAX_WRITE_LATENCY_COUNT_WIDTH" value="6" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="RATE" value="Half" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="MR1_WL" value="0" />
|
|
<parameter name="REFRESH_BURST_VALIDATION" value="false" />
|
|
<parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="270.0" />
|
|
<parameter name="MR3_MPR_RF" value="0" />
|
|
<parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
|
|
<parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="1" />
|
|
<parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
|
|
<parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="50" />
|
|
<parameter name="MEM_IF_ADDR_WIDTH" value="14" />
|
|
<parameter name="PLL_DR_CLK_DIV" value="0" />
|
|
<parameter name="USE_SEQUENCER_BFM" value="false" />
|
|
<parameter name="DELAY_PER_DCHAIN_TAP" value="50" />
|
|
<parameter name="MEM_CLK_MAX_PS" value="1250.0" />
|
|
<parameter name="CSR_ADDR_WIDTH" value="8" />
|
|
<parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="3" />
|
|
<parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
|
|
<parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
|
|
<parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
|
|
<parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="EXPORT_AFI_HALF_CLK" value="false" />
|
|
<parameter name="MEM_BURST_LENGTH" value="8" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="6668 ps" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_STR" value="150.0 MHz" />
|
|
<parameter name="IO_DQDQS_OUT_PHASE_MAX" value="14" />
|
|
<parameter name="MEM_TRRD" value="2" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="RDIMM_INT" value="0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="READ_VALID_FIFO_SIZE" value="16" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
|
|
<parameter name="REFRESH_INTERVAL" value="15000" />
|
|
<parameter name="DLL_MASTER" value="true" />
|
|
<parameter name="PLL_WRITE_CLK_DIV_PARAM" value="1" />
|
|
<parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
|
|
<parameter name="MEM_TWTR" value="6" />
|
|
<parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_INIT_EN" value="false" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="Unknown" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
|
|
<parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
|
|
<parameter name="MEM_TRFC_NS" value="110.0" />
|
|
<parameter name="TIMING_BOARD_TDH_APPLIED" value="0.145" />
|
|
<parameter name="ADDR_RATE_RATIO" value="1" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="2500 ps" />
|
|
<parameter name="ENABLE_ISS_PROBES" value="false" />
|
|
<parameter name="MR2_RTT_WR" value="0" />
|
|
<parameter name="TIMING_BOARD_TDS_APPLIED" value="0.16" />
|
|
<parameter name="AFI_ODT_WIDTH" value="2" />
|
|
<parameter name="PLL_MASTER" value="true" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
|
|
<parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
|
|
<parameter name="DISCRETE_FLY_BY" value="true" />
|
|
<parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
|
|
<parameter name="MEM_RTT_NOM" value="ODT Disabled" />
|
|
<parameter name="QVLD_WR_ADDRESS_OFFSET" value="4" />
|
|
<parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="1" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="TB_PLL_DLL_MASTER" value="true" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT" value="0" />
|
|
<parameter name="MEM_IF_DM_WIDTH" value="1" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS" value="2500" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.04429" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="AFI_WRANK_WIDTH" value="2" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="2500" />
|
|
<parameter name="LRDIMM" value="false" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="2500" />
|
|
<parameter name="MR1_DLL" value="0" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
|
|
<parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="-0.01152" />
|
|
<parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PHY_CLKBUF" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="SEQUENCER_TYPE" value="NIOS" />
|
|
<parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
|
|
<parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="MEM_IF_CHIP_BITS" value="1" />
|
|
<parameter name="VFIFO_AS_SHIFT_REG" value="true" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
|
|
<parameter name="MEM_IF_CK_WIDTH" value="1" />
|
|
<parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
|
|
<parameter name="MEM_TCL" value="5" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
|
|
<parameter name="TIMING_TDQSCK" value="225" />
|
|
<parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
|
|
<parameter name="DLL_SHARING_MODE" value="None" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="2500" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="PLL_DR_CLK_MULT" value="0" />
|
|
<parameter name="USE_USER_RDIMM_VALUE" value="false" />
|
|
<parameter name="MEM_FORMAT" value="DISCRETE" />
|
|
<parameter name="AFI_RATE_RATIO" value="2" />
|
|
<parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
|
|
<parameter name="PLL_MEM_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="CFG_TCCD_NS" value="2.5" />
|
|
<parameter name="IO_DQS_IN_RESERVE" value="3" />
|
|
<parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="AFI_WLAT_WIDTH" value="6" />
|
|
<parameter name="ENABLE_NIOS_OCI" value="false" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="FIX_READ_LATENCY" value="8" />
|
|
<parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
|
|
<parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
|
|
<parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
|
|
<parameter name="RATE_CACHE" value="Unknown" />
|
|
<parameter name="COMMAND_PHASE" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT" value="3" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
|
|
<parameter name="MR1_ODS" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="MEM_TRFC" value="34" />
|
|
<parameter name="PHY_CSR_ENABLED" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="DQ_DDR" value="1" />
|
|
<parameter name="PLL_WRITE_CLK_MULT_PARAM" value="3" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_DEG" value="270.0" />
|
|
<parameter name="MEM_INIT_FILE" value="" />
|
|
<parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="MEM_CK_PHASE" value="0.0" />
|
|
<parameter name="FORCE_DQS_TRACKING" value="AUTO" />
|
|
<parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="0.02286" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
|
|
<parameter name="TB_RATE" value="HALF" />
|
|
<parameter name="REF_CLK_FREQ_CACHE_VALID" value="true" />
|
|
<parameter name="MEM_CK_WIDTH" value="1" />
|
|
<parameter name="MEM_ATCL" value="Disabled" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="DISABLE_CHILD_MESSAGING" value="true" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
|
|
<parameter name="MEM_TDQSCK" value="1" />
|
|
<parameter name="MEM_VERBOSE" value="true" />
|
|
<parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
|
|
<parameter name="HARD_PHY" value="false" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="MR2_SRF" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
|
|
<parameter name="REF_CLK_FREQ_MIN_PARAM" value="10.0" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="MEM_WTCL" value="5" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="PLL_MEM_CLK_MULT" value="3" />
|
|
<parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="MEM_IF_CS_PER_DIMM" value="1" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="VCALIB_COUNT_WIDTH" value="2" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
|
|
<parameter name="OCT_TERM_CONTROL_WIDTH" value="14" />
|
|
<parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
|
|
<parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="DLL_USE_DR_CLK" value="false" />
|
|
<parameter name="AC_PARITY" value="false" />
|
|
<parameter name="PLL_WRITE_CLK_DIV" value="1" />
|
|
<parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
|
|
<parameter name="MR1_DQS" value="0" />
|
|
<parameter name="MR2_SRT" value="0" />
|
|
<parameter name="CALIB_VFIFO_OFFSET" value="12" />
|
|
<parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="2500 ps" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="3" />
|
|
<parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
|
|
<parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
|
|
<parameter name="MR1_QOFF" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="MEM_DRV_STR" value="RZQ/6" />
|
|
<parameter name="MEM_TREFI" value="2341" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
|
|
<parameter name="TB_MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="NUM_SUBGROUP_PER_READ_DQS" value="1" />
|
|
<parameter name="TIMING_BOARD_AC_SKEW" value="0.07801" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_PARAM" value="150.0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="2500" />
|
|
<parameter name="MEM_TRP_NS" value="13.75" />
|
|
<parameter name="DLL_DELAY_CTRL_WIDTH" value="6" />
|
|
<parameter name="QVLD_EXTRA_FLOP_STAGES" value="0" />
|
|
<parameter name="MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="MEM_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ" value="300.0" />
|
|
<parameter name="USE_FAKE_PHY" value="false" />
|
|
<parameter name="EXTRA_SETTINGS" value="" />
|
|
<parameter name="PLL_DR_CLK_FREQ_STR" value="" />
|
|
<parameter name="SEQ_MODE" value="0" />
|
|
<parameter name="MEM_IF_CS_WIDTH" value="1" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
|
|
<parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="MEM_TYPE" value="DDR3" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="REF_CLK_PS" value="10000.0" />
|
|
<parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="false" />
|
|
<parameter name="SEQUENCER_TYPE_CACHE" value="Unknown" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="MR0_BT" value="0" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01806" />
|
|
<parameter name="MR1_AL" value="0" />
|
|
<parameter name="DQS_PHASE_SHIFT" value="9000" />
|
|
<parameter name="MR0_BL" value="1" />
|
|
<parameter name="MARGIN_VARIATION_TEST" value="false" />
|
|
<parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
|
|
<parameter name="TIMING_TIS" value="170" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02286" />
|
|
<parameter name="MEM_TRCD" value="5" />
|
|
<parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.2443" />
|
|
<parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
|
|
<parameter name="IO_IN_DELAY_MAX" value="15" />
|
|
<parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
|
|
<parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="REGISTER_C2P" value="false" />
|
|
<parameter name="FAST_SIM_CALIBRATION" value="false" />
|
|
<parameter name="MEM_WTCL_INT" value="5" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
|
|
<parameter name="DQS_EN_DELAY_MAX" value="7" />
|
|
<parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="0 ps" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="AVL_ADDR_WIDTH" value="13" />
|
|
<parameter name="DELAY_BUFFER_MODE" value="HIGH" />
|
|
<parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
|
|
<parameter name="REF_CLK_FREQ" value="100.0" />
|
|
<parameter name="AFI_RRANK_WIDTH" value="2" />
|
|
<parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV" value="0" />
|
|
<parameter name="MR0_DLL" value="1" />
|
|
<parameter name="FORCE_SHADOW_REGS" value="AUTO" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PINGPONGPHY_EN" value="false" />
|
|
<parameter name="MR3_MPR" value="0" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="6668 ps" />
|
|
<parameter name="MR2_ASR" value="0" />
|
|
<parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
|
|
<parameter name="AFI_MAX_READ_LATENCY_COUNT_WIDTH" value="6" />
|
|
<parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
|
|
<parameter name="MR2_CWL" value="0" />
|
|
<parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.21929" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV" value="1" />
|
|
<parameter name="HPS_PROTOCOL" value="DEFAULT" />
|
|
<parameter name="MEM_IF_LRDIMM_RM" value="0" />
|
|
<parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="MEM_IF_ODT_WIDTH" value="1" />
|
|
<parameter name="TIMING_TDQSCKDL" value="1200" />
|
|
<parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="TIMING_TDQSCKDS" value="450" />
|
|
<parameter name="TIMING_TDQSCKDM" value="900" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="TIMING_BOARD_TIS" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="DUPLICATE_AC" value="false" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="NIOS_HEX_FILE_LOCATION" value="../" />
|
|
<parameter name="DUAL_WRITE_CLOCK" value="false" />
|
|
<parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="0 ps" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
|
|
<parameter name="TIMING_BOARD_TIH" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_MULT" value="3" />
|
|
<parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
|
|
<parameter name="REF_CLK_FREQ_PARAM_VALID" value="true" />
|
|
<parameter name="PLL_MEM_CLK_DIV_PARAM" value="1" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="TIMING_BOARD_TDS" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
|
|
<parameter name="AFI_BANKADDR_WIDTH" value="6" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="TIMING_BOARD_TDH" value="0.0" />
|
|
<parameter name="PACKAGE_DESKEW" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="TRACKING_WATCH_TEST" value="false" />
|
|
<parameter name="MEM_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
|
|
<parameter name="AFI_DM_WIDTH" value="4" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV" value="0" />
|
|
<parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
|
|
<parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
|
|
<parameter name="USE_SHADOW_REGS" value="false" />
|
|
<parameter name="REF_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="TRACKING_ERROR_TEST" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="REF_CLK_FREQ_STR" value="100.0 MHz" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
|
|
<parameter name="PLL_MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="MEM_IF_DQ_WIDTH" value="8" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
|
|
<parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
|
|
<parameter name="MR1_RTT" value="0" />
|
|
<parameter name="PLL_MEM_CLK_MULT_PARAM" value="3" />
|
|
<parameter name="READ_FIFO_HALF_RATE" value="true" />
|
|
<parameter name="ADDR_CMD_DDR" value="0" />
|
|
<parameter name="GENERIC_PLL" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
|
|
<parameter name="ENABLE_NON_DES_CAL" value="false" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="3334 ps" />
|
|
<parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
|
|
<parameter name="MR3_MPR_AA" value="0" />
|
|
<parameter name="CSR_DATA_WIDTH" value="32" />
|
|
<parameter name="MEM_DLL_EN" value="true" />
|
|
<parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
|
|
<parameter name="IS_ES_DEVICE" value="false" />
|
|
<parameter name="PRE_V_SERIES_FAMILY" value="false" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="MEM_TFAW_NS" value="30.0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="1" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ" value="300.0" />
|
|
<parameter name="HHP_HPS_SIMULATION" value="false" />
|
|
<parameter name="REF_CLK_NS" value="10.0" />
|
|
<parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
|
|
<parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="IO_OUT2_DELAY_MAX" value="7" />
|
|
<parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
|
|
<parameter name="AFI_CLK_EN_WIDTH" value="2" />
|
|
<parameter name="TIMING_TQH" value="0.38" />
|
|
<parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_CLK_CACHE_VALID" value="true" />
|
|
<parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
|
|
<parameter name="PLL_MEM_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
|
|
<parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="HCX_COMPAT_MODE" value="false" />
|
|
<parameter name="PLL_HR_CLK_MULT" value="0" />
|
|
<parameter name="MEM_IF_DQSN_EN" value="true" />
|
|
<parameter name="AC_ROM_MR0" value="0001000010001" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="HHP_HPS" value="false" />
|
|
<parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="MEM_TRAS" value="11" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING" value="0" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="MEM_TINIT_US" value="500" />
|
|
<parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
|
|
<parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
|
|
<parameter name="DAT_DATA_WIDTH" value="32" />
|
|
<parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
|
|
<parameter name="CALIBRATION_MODE" value="Skip" />
|
|
<parameter name="AC_ROM_MR1_CALIB" value="" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
|
|
<parameter name="PLL_MEM_CLK_DIV" value="1" />
|
|
<parameter name="SPEED_GRADE" value="6" />
|
|
<parameter name="OCT_SHARING_MODE" value="None" />
|
|
<parameter name="AC_ROM_MR2" value="0000000000000" />
|
|
<parameter name="AC_ROM_MR1" value="0000000000000" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV" value="0" />
|
|
<parameter name="AC_ROM_MR3" value="0000000000000" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="MEM_TRCD_NS" value="13.75" />
|
|
<parameter name="USE_HARD_READ_FIFO" value="false" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
|
|
<parameter name="AFI_ADDR_WIDTH" value="28" />
|
|
<parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
|
|
<parameter name="PHY_VERSION_NUMBER" value="191" />
|
|
<parameter name="MEM_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="TIMING_BOARD_TIH_APPLIED" value="0.22" />
|
|
<parameter name="USE_HPS_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="MEM_SRT" value="Normal" />
|
|
<parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
|
|
<parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
|
|
<parameter name="EXPORT_CSR_PORT" value="false" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="2500 ps" />
|
|
<parameter name="PLL_WRITE_CLK_MULT_CACHE" value="3" />
|
|
<parameter name="EXTRA_VFIFO_SHIFT" value="0" />
|
|
<parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
|
|
<parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="TIMING_TDS" value="10" />
|
|
<parameter name="PLL_CLK_PARAM_VALID" value="true" />
|
|
<parameter name="MEM_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
|
|
<parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="CFG_TCCD" value="1" />
|
|
<parameter name="MEM_CS_WIDTH" value="1" />
|
|
<parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
|
|
<parameter name="TIMING_TDH" value="45" />
|
|
<parameter name="DELAY_CHAIN_LENGTH" value="8" />
|
|
<parameter name="SCC_DATA_WIDTH" value="1" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ" value="300.0" />
|
|
<parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="MEM_TREFI_US" value="7.8" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_WRITE_CLK_DIV_CACHE" value="1" />
|
|
<parameter name="USE_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_LRDIMM_ENABLED" value="false" />
|
|
<parameter name="TIMING_BOARD_TIS_APPLIED" value="0.32" />
|
|
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.04429" />
|
|
<parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
|
|
<parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
|
|
<parameter name="AC_ROM_MR0_CALIB" value="" />
|
|
<parameter name="MEM_TWR_NS" value="15.0" />
|
|
<parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="MEM_T_WL" value="5" />
|
|
<parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
|
|
<parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="AFI_RLAT_WIDTH" value="6" />
|
|
<parameter name="MEM_TRP" value="5" />
|
|
<parameter name="MEM_CLK_PS" value="3333.0" />
|
|
<parameter name="IS_ES_DEVICE_CACHE" value="false" />
|
|
<parameter name="PLL_AFI_CLK_FREQ" value="150.0" />
|
|
<parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="MEM_TMRD_CK" value="4" />
|
|
<parameter name="MEM_TRRD_NS" value="6.0" />
|
|
<parameter name="IO_OUT1_DELAY_MAX" value="15" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="270.0" />
|
|
<parameter name="DEVICE_DEPTH" value="1" />
|
|
<parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_MULT" value="3" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="DQS_IN_DELAY_MAX" value="15" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="300.0" />
|
|
<parameter name="AC_PACKAGE_DESKEW" value="false" />
|
|
<parameter name="MR0_CAS_LATENCY" value="1" />
|
|
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.0" />
|
|
<parameter name="MR0_WR" value="1" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
|
|
<parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
|
|
<parameter name="SEQ_BURST_COUNT_WIDTH" value="1" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
|
|
<parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="PHY_ONLY" value="false" />
|
|
<parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="false" />
|
|
<parameter name="TRFC" value="350" />
|
|
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="3334 ps" />
|
|
<parameter name="IO_STANDARD" value="SSTL-15" />
|
|
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="TIMING_TDQSS" value="0.27" />
|
|
<parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
|
|
<parameter name="TIMING_TDQSQ" value="100" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
|
|
<parameter name="SPEED_GRADE_CACHE" value="" />
|
|
<parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
|
|
<parameter name="PLL_AFI_CLK_FREQ_CACHE" value="150.0" />
|
|
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="3334 ps" />
|
|
<parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
|
|
<parameter name="READ_FIFO_SIZE" value="8" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="0 ps" />
|
|
<parameter name="USE_2X_FF" value="false" />
|
|
<parameter name="MEM_ASR" value="Manual" />
|
|
<parameter name="PLL_DR_CLK_FREQ" value="0.0" />
|
|
<parameter name="TB_MEM_IF_DQ_WIDTH" value="8" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="2500 ps" />
|
|
<parameter name="NEGATIVE_WRITE_CK_PHASE" value="true" />
|
|
<parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
|
|
<parameter name="ADVANCED_CK_PHASES" value="false" />
|
|
<parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
|
|
<parameter name="NEXTGEN" value="true" />
|
|
<parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
|
|
<parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
|
|
<parameter name="MEM_ATCL_INT" value="0" />
|
|
<parameter name="MEM_T_RL" value="5" />
|
|
<parameter name="MEM_TWR" value="5" />
|
|
<parameter name="USE_DR_CLK" value="false" />
|
|
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
|
|
<parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
|
|
<parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
|
|
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="300.0" />
|
|
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="2500" />
|
|
<parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
|
|
<parameter name="ENABLE_EMIT_JTAG_MASTER" value="false" />
|
|
<parameter name="MEM_IF_DQS_WIDTH" value="1" />
|
|
<parameter name="TIMING_TDSS" value="0.18" />
|
|
<parameter name="TIMING_TIH" value="120" />
|
|
<parameter name="CSR_BE_WIDTH" value="4" />
|
|
<parameter name="PLL_LOCATION" value="Top_Bottom" />
|
|
<parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="2500 ps" />
|
|
<parameter name="MEM_TRTP_NS" value="7.5" />
|
|
<parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
|
|
<parameter name="PLL_SHARING_MODE" value="None" />
|
|
<parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
|
|
<parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
|
|
<parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
|
|
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="2500" />
|
|
<parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
|
|
<parameter name="AP_MODE" value="false" />
|
|
<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
|
|
<parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="300.0 MHz" />
|
|
<parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="false" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
|
|
<parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
|
|
<parameter name="MEM_PD" value="DLL off" />
|
|
<parameter name="MAX10_RTL_SEQ" value="true" />
|
|
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="0" />
|
|
<parameter name="TIMING_TDSH" value="0.18" />
|
|
<parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
|
|
<parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
|
|
<parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
|
|
<parameter name="REF_CLK_FREQ_MAX_CACHE" value="500.0" />
|
|
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
|
|
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="0 ps" />
|
|
<parameter name="PLL_AFI_CLK_DIV" value="2" />
|
|
<parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
|
|
<parameter name="MEM_TFAW" value="10" />
|
|
<parameter name="MEM_DQ_WIDTH" value="8" />
|
|
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|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
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<file
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
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<file
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
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<file
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
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</sourceFiles>
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<childSourceFiles/>
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<instantiator instantiator="q_sys_ddr3_ram" as="s0" />
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<messages>
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<message level="Debug" culprit="q_sys">queue size: 229 starting:altera_mem_if_ddr3_qseq "submodules/q_sys_ddr3_ram_s0"</message>
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<message level="Info" culprit="s0">Generating Qsys sequencer system</message>
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<message level="Info" culprit="s0">QSYS sequencer system generated successfully</message>
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<message level="Info" culprit="s0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"]]></message>
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</messages>
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</entity>
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<entity
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path="submodules/"
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parameterizationKey="altera_mem_if_nextgen_ddr3_controller:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6(altera_mem_if_nextgen_ddr3_controller_core:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=1,AUTO_CLK_CLOCK_RATE=-1,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=none,USE_RESET_REQUEST=0)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(alt_mem_ddrx_mm_st_converter:19.1:AVL_ADDR_WIDTH=25,AVL_BYTE_ENABLE=true,AVL_DATA_WIDTH=32,AVL_NUM_SYMBOLS=4,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,CFG_DWIDTH_RATIO=4,CTL_AUTOPCH_EN=false,CTL_ECC_ENABLED=false,ENABLE_CTRL_AVALON_INTERFACE=true,LOCAL_ID_WIDTH=8,MAX_PENDING_READ_TRANSACTION=32,MULTICAST_EN=false)(clock:19.1:)(clock:19.1:)(reset:19.1:)(conduit:19.1:endPort=,endPortLSB=0,startPort=,startPortLSB=0,width=0)(clock:19.1:)(clock:19.1:)(reset:19.1:)(reset:19.1:)"
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instancePathKey="q_sys:.:ddr3_ram:.:c0"
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kind="altera_mem_if_nextgen_ddr3_controller"
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version="19.1"
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name="q_sys_ddr3_ram_c0">
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<parameter name="VECT_ATTR_COUNTER_ZERO_MATCH" value="0" />
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<parameter name="ENUM_GANGED_ARF" value="DISABLED" />
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<parameter name="LRDIMM_INT" value="0" />
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<parameter name="ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
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<parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
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<parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
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<parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
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<parameter name="MEM_LEVELING" value="true" />
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<parameter name="CV_ENUM_PRIORITY_1_0" value="WEIGHT_0" />
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<parameter name="ENUM_MEM_IF_TRRD" value="TRRD_4" />
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<parameter name="CV_ENUM_PRIORITY_1_2" value="WEIGHT_0" />
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<parameter name="ENUM_ATTR_COUNTER_ZERO_RESET" value="DISABLED" />
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<parameter name="CV_ENUM_PRIORITY_1_1" value="WEIGHT_0" />
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<parameter name="MEM_ADD_LAT" value="0" />
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<parameter name="CV_ENUM_PRIORITY_1_4" value="WEIGHT_0" />
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<parameter name="CV_ENUM_PRIORITY_1_3" value="WEIGHT_0" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR" value="0" />
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<parameter name="CV_ENUM_PRIORITY_1_5" value="WEIGHT_0" />
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<parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT" value="0" />
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<parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
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<parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
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<parameter name="ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
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<parameter name="INTG_MEM_IF_TRFC" value="34" />
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<parameter name="MEM_REGDIMM_ENABLED" value="false" />
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<parameter name="AFI_DQ_WIDTH" value="32" />
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<parameter name="AP_MODE_EN" value="0" />
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<parameter name="ENUM_CPORT5_RDY_ALMOST_FULL" value="NOT_FULL" />
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<parameter name="INTG_SUM_WT_PRIORITY_4" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_5" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_6" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_7" value="0" />
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<parameter name="ENUM_CPORT2_RDY_ALMOST_FULL" value="NOT_FULL" />
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<parameter name="VECT_ATTR_COUNTER_ZERO_MASK" value="0" />
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<parameter name="ALLOCATED_WFIFO_PORT" value="0,None,None,None,None,None" />
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<parameter name="MEM_TRAS_NS" value="35.0" />
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<parameter name="INTG_SUM_WT_PRIORITY_0" value="0" />
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<parameter name="CV_ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
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<parameter name="INTG_SUM_WT_PRIORITY_1" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_2" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_3" value="0" />
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<parameter name="ENABLE_BONDING" value="false" />
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<parameter name="HHP_HPS_VERIFICATION" value="false" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC" value="0" />
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<parameter name="CV_ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
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<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP" value="0" />
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<parameter name="ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
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<parameter name="RDIMM_CONFIG" value="0000000000000000" />
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<parameter name="CV_ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
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<parameter name="ENUM_ENABLE_INTR" value="DISABLED" />
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<parameter name="INTG_MEM_AUTO_PD_CYCLES" value="0" />
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<parameter name="AVL_DATA_WIDTH" value="32" />
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<parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
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<parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
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<parameter name="MR1_RDQS" value="0" />
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<parameter name="ENUM_MEM_IF_ROWADDR_WIDTH" value="ADDR_WIDTH_16" />
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<parameter name="MR0_PD" value="0" />
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<parameter name="MEM_VENDOR" value="JEDEC" />
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<parameter name="MEM_IF_CS_PER_RANK" value="1" />
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<parameter name="CV_PORT_1_CONNECT_TO_AV_PORT" value="1" />
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<parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
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<parameter name="CV_ENUM_CPORT1_TYPE" value="DISABLE" />
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<parameter name="USE_MEM_CLK_FREQ" value="false" />
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<parameter name="CV_MSB_WFIFO_PORT_5" value="5" />
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<parameter name="CFG_READ_ODT_CHIP" value="0" />
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<parameter name="CV_MSB_WFIFO_PORT_4" value="5" />
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<parameter name="CV_MSB_WFIFO_PORT_3" value="5" />
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<parameter name="RDIMM" value="false" />
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<parameter name="ENUM_MEM_IF_COLADDR_WIDTH" value="ADDR_WIDTH_12" />
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<parameter name="ENABLE_USER_ECC" value="false" />
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<parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD" value="0" />
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<parameter name="MEM_TRC" value="15" />
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<parameter name="AVL_ADDR_WIDTH_PORT_2" value="0" />
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<parameter name="ENUM_PRIORITY_6_4" value="WEIGHT_0" />
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<parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID" value="0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_3" value="USE_NO" />
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<parameter name="AVL_ADDR_WIDTH_PORT_1" value="0" />
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<parameter name="ENUM_PRIORITY_6_5" value="WEIGHT_0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_2" value="USE_NO" />
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<parameter name="AVL_ADDR_WIDTH_PORT_0" value="0" />
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<parameter name="ENUM_PRIORITY_6_2" value="WEIGHT_0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_5" value="USE_NO" />
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<parameter name="ENUM_PRIORITY_6_3" value="WEIGHT_0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_4" value="USE_NO" />
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<parameter name="ENUM_PRIORITY_6_0" value="WEIGHT_0" />
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<parameter name="AFI_CS_WIDTH" value="2" />
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<parameter name="AVL_ADDR_WIDTH_PORT_5" value="0" />
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<parameter name="ENUM_PRIORITY_6_1" value="WEIGHT_0" />
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<parameter name="AVL_ADDR_WIDTH_PORT_4" value="0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_1" value="USE_NO" />
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<parameter name="AVL_ADDR_WIDTH_PORT_3" value="0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_0" value="USE_NO" />
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<parameter name="CV_MSB_WFIFO_PORT_2" value="5" />
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<parameter name="CV_MSB_WFIFO_PORT_1" value="5" />
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<parameter name="ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
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<parameter name="CV_MSB_WFIFO_PORT_0" value="5" />
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<parameter name="TG_TEMP_PORT_5" value="0" />
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<parameter name="TG_TEMP_PORT_3" value="0" />
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<parameter name="TG_TEMP_PORT_4" value="0" />
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<parameter name="TG_TEMP_PORT_1" value="0" />
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<parameter name="TG_TEMP_PORT_2" value="0" />
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<parameter name="TG_TEMP_PORT_0" value="0" />
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<parameter name="ENUM_MEM_IF_BURSTLENGTH" value="MEM_IF_BURSTLENGTH_8" />
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<parameter name="CFG_ENABLE_NO_DM" value="0" />
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<parameter name="MR1_TDQS" value="0" />
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<parameter name="INTG_MEM_CLK_ENTRY_CYCLES" value="10" />
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<parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
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<parameter name="CTL_ECC_MULTIPLES_16_24_40_72" value="1" />
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<parameter name="CV_ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
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<parameter name="ENUM_MEM_IF_TCWL" value="TCWL_5" />
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<parameter name="DEVICE_FAMILY" value="MAX 10" />
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<parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
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<parameter name="REFRESH_BURST_VALIDATION" value="false" />
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<parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID" value="0" />
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<parameter name="ENUM_MEM_IF_TRTP" value="TRTP_4" />
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<parameter name="INTG_POWER_SAVING_EXIT_CYCLES" value="5" />
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<parameter name="MEM_IF_ADDR_WIDTH" value="14" />
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<parameter name="CSR_ADDR_WIDTH" value="8" />
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<parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID" value="0" />
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<parameter name="CV_ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
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<parameter name="CV_ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
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<parameter name="RDIMM_INT" value="0" />
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<parameter name="CV_ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
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<parameter name="CTL_CSR_READ_ONLY" value="1" />
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<parameter name="ENUM_MASK_DBE_INTR" value="DISABLED" />
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<parameter name="CV_ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
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<parameter name="CV_ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
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<parameter name="CV_ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
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<parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
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<parameter name="MEM_TWTR" value="6" />
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<parameter name="ENUM_ENABLE_BURST_INTERRUPT" value="DISABLED" />
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<parameter name="CV_ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
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<parameter name="WEIGHT_PORT_2" value="0" />
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<parameter name="WEIGHT_PORT_1" value="0" />
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<parameter name="WEIGHT_PORT_0" value="0" />
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<parameter name="WEIGHT_PORT_5" value="0" />
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<parameter name="WEIGHT_PORT_4" value="0" />
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<parameter name="WEIGHT_PORT_3" value="0" />
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<parameter name="ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
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<parameter name="CV_ENUM_ENABLE_BONDING_2" value="DISABLED" />
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<parameter name="CV_ENUM_ENABLE_BONDING_3" value="DISABLED" />
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<parameter name="MEM_TRFC_NS" value="110.0" />
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<parameter name="CV_ENUM_ENABLE_BONDING_4" value="DISABLED" />
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<parameter name="CV_ENUM_ENABLE_BONDING_5" value="DISABLED" />
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<parameter name="MR2_RTT_WR" value="0" />
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<parameter name="ENUM_MEM_IF_TFAW" value="TFAW_16" />
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<parameter name="AFI_ODT_WIDTH" value="2" />
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<parameter name="CV_ENUM_ENABLE_BONDING_0" value="DISABLED" />
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<parameter name="CV_ENUM_ENABLE_BONDING_1" value="DISABLED" />
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<parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL" value="NOT_FULL" />
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<parameter name="DISCRETE_FLY_BY" value="true" />
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<parameter name="AVL_SYMBOL_WIDTH" value="8" />
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<parameter name="MEM_IF_DM_WIDTH" value="1" />
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<parameter name="LOCAL_CS_WIDTH" value="0" />
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<parameter name="CTL_ECC_ENABLED" value="false" />
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<parameter name="AUTO_POWERDN_EN" value="false" />
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<parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL" value="NOT_FULL" />
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<parameter name="MAX_PENDING_WR_CMD" value="16" />
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<parameter name="ENUM_ATTR_COUNTER_ONE_RESET" value="DISABLED" />
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<parameter name="ENUM_WRITE_ODT_CHIP" value="ODT_DISABLED" />
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<parameter name="MEM_IF_CHIP_BITS" value="1" />
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<parameter name="ENUM_MEM_IF_CS_PER_RANK" value="MEM_IF_CS_PER_RANK_1" />
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<parameter name="MEM_IF_CK_WIDTH" value="1" />
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<parameter name="MEM_TCL" value="5" />
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<parameter name="ENUM_LOCAL_IF_CS_WIDTH" value="ADDR_WIDTH_2" />
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<parameter name="TIMING_TDQSCK" value="225" />
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<parameter name="CTL_USR_REFRESH_EN" value="false" />
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<parameter name="ENUM_WR_FIFO_IN_USE_3" value="FALSE" />
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<parameter name="ENUM_WR_FIFO_IN_USE_2" value="FALSE" />
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<parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP" value="1" />
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<parameter name="ENUM_WR_FIFO_IN_USE_1" value="FALSE" />
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<parameter name="ENUM_WR_FIFO_IN_USE_0" value="FALSE" />
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<parameter name="ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
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<parameter name="AFI_RATE_RATIO" value="2" />
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<parameter name="ENUM_THLD_JAR2_3" value="THRESHOLD_16" />
|
|
<parameter name="ENUM_THLD_JAR2_4" value="THRESHOLD_16" />
|
|
<parameter name="ENUM_THLD_JAR2_5" value="THRESHOLD_16" />
|
|
<parameter name="AV_PORT_0_CONNECT_TO_CV_PORT" value="0" />
|
|
<parameter name="ENUM_CTL_ECC_RMW_ENABLED" value="CTL_ECC_RMW_DISABLED" />
|
|
<parameter name="CFG_TCCD_NS" value="2.5" />
|
|
<parameter name="AVL_NUM_SYMBOLS" value="4" />
|
|
<parameter name="CTL_OUTPUT_REGD" value="false" />
|
|
<parameter name="CV_PORT_0_CONNECT_TO_AV_PORT" value="0" />
|
|
<parameter name="CTL_CSR_ENABLED" value="false" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH" value="0" />
|
|
<parameter name="DQ_DDR" value="1" />
|
|
<parameter name="MEM_INIT_FILE" value="" />
|
|
<parameter name="AVL_PORT" value="" />
|
|
<parameter name="ALLOCATED_RFIFO_PORT" value="0,None,None,None,None,None" />
|
|
<parameter name="MEM_CK_WIDTH" value="1" />
|
|
<parameter name="MEM_ATCL" value="Disabled" />
|
|
<parameter name="DISABLE_CHILD_MESSAGING" value="true" />
|
|
<parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
|
|
<parameter name="MEM_TDQSCK" value="1" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD" value="0" />
|
|
<parameter name="MEM_WTCL" value="5" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP" value="0" />
|
|
<parameter name="CV_ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="MEM_IF_CS_PER_DIMM" value="1" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
|
|
<parameter name="CTL_ECC_CSR_ENABLED" value="false" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP" value="0" />
|
|
<parameter name="MEM_AUTO_PD_CYCLES" value="0" />
|
|
<parameter name="CV_ENUM_CPORT3_TYPE" value="DISABLE" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
|
|
<parameter name="CTL_ECC_MULTIPLES_40_72" value="1" />
|
|
<parameter name="MSB_RFIFO_PORT_2" value="5" />
|
|
<parameter name="MSB_RFIFO_PORT_3" value="5" />
|
|
<parameter name="MSB_RFIFO_PORT_4" value="5" />
|
|
<parameter name="MSB_RFIFO_PORT_5" value="5" />
|
|
<parameter name="CV_ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="MEM_DRV_STR" value="RZQ/6" />
|
|
<parameter name="MEM_TREFI" value="2341" />
|
|
<parameter name="MSB_RFIFO_PORT_0" value="5" />
|
|
<parameter name="MEM_TRP_NS" value="13.75" />
|
|
<parameter name="MSB_RFIFO_PORT_1" value="5" />
|
|
<parameter name="CTL_HRB_ENABLED" value="false" />
|
|
<parameter name="ENUM_MMR_CFG_MEM_BL" value="MP_BL_8" />
|
|
<parameter name="MEM_IF_CS_WIDTH" value="1" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_1" value="USE_NO" />
|
|
<parameter name="STARVE_LIMIT" value="10" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_2" value="USE_NO" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_3" value="USE_NO" />
|
|
<parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP" value="1" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_4" value="USE_NO" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_0" value="USE_NO" />
|
|
<parameter name="CTL_USR_REFRESH" value="0" />
|
|
<parameter name="AV_PORT_2_CONNECT_TO_CV_PORT" value="2" />
|
|
<parameter name="CV_ENUM_WR_PORT_INFO_5" value="USE_NO" />
|
|
<parameter name="MR0_BT" value="0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL" value="0" />
|
|
<parameter name="MR1_AL" value="0" />
|
|
<parameter name="MR0_BL" value="1" />
|
|
<parameter name="MEM_TRCD" value="5" />
|
|
<parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
|
|
<parameter name="MAX_PENDING_RD_CMD" value="32" />
|
|
<parameter name="MEM_WTCL_INT" value="5" />
|
|
<parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
|
|
<parameter name="ENUM_CPORT1_TYPE" value="DISABLE" />
|
|
<parameter name="AV_PORT_5_CONNECT_TO_CV_PORT" value="5" />
|
|
<parameter name="MR0_DLL" value="1" />
|
|
<parameter name="FORCE_SHADOW_REGS" value="AUTO" />
|
|
<parameter name="PINGPONGPHY_EN" value="false" />
|
|
<parameter name="CFG_WRITE_ODT_CHIP" value="1" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_5" value="2" />
|
|
<parameter name="MR2_ASR" value="0" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_3" value="2" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_4" value="2" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_1" value="2" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_2" value="2" />
|
|
<parameter name="MR2_CWL" value="0" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_0" value="2" />
|
|
<parameter name="HPS_PROTOCOL" value="DEFAULT" />
|
|
<parameter name="MEM_IF_LRDIMM_RM" value="0" />
|
|
<parameter name="VECT_ATTR_COUNTER_ONE_MATCH" value="0" />
|
|
<parameter name="ENUM_PRIORITY_1_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="DUPLICATE_AC" value="false" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_5" value="2" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_1" value="2" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_2" value="2" />
|
|
<parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_3" value="2" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_4" value="2" />
|
|
<parameter name="CFG_POWER_SAVING_EXIT_CYCLES" value="5" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_0" value="2" />
|
|
<parameter name="CV_PORT_2_CONNECT_TO_AV_PORT" value="2" />
|
|
<parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
|
|
<parameter name="AUTO_PD_CYCLES" value="0" />
|
|
<parameter name="ENUM_CPORT5_TYPE" value="DISABLE" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD" value="0" />
|
|
<parameter name="AFI_BANKADDR_WIDTH" value="6" />
|
|
<parameter name="CV_ENUM_CPORT0_TYPE" value="DISABLE" />
|
|
<parameter name="ENUM_THLD_JAR2_0" value="THRESHOLD_16" />
|
|
<parameter name="CTL_DEEP_POWERDN_EN" value="false" />
|
|
<parameter name="CTL_TBP_NUM" value="4" />
|
|
<parameter name="ENUM_THLD_JAR2_1" value="THRESHOLD_16" />
|
|
<parameter name="MEM_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="ENUM_THLD_JAR2_2" value="THRESHOLD_16" />
|
|
<parameter name="CTL_ENABLE_BURST_TERMINATE_INT" value="false" />
|
|
<parameter name="CFG_ECC_DECODER_REG" value="0" />
|
|
<parameter name="CTL_ENABLE_BURST_INTERRUPT_INT" value="false" />
|
|
<parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
|
|
<parameter name="MR1_RTT" value="0" />
|
|
<parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
|
|
<parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
|
|
<parameter name="CSR_DATA_WIDTH" value="32" />
|
|
<parameter name="MEM_DLL_EN" value="true" />
|
|
<parameter name="IS_ES_DEVICE" value="false" />
|
|
<parameter name="PRE_V_SERIES_FAMILY" value="false" />
|
|
<parameter name="USE_MM_ADAPTOR" value="true" />
|
|
<parameter name="HHP_HPS_SIMULATION" value="false" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_1" value="WEIGHT_0" />
|
|
<parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_0" value="WEIGHT_0" />
|
|
<parameter name="HCX_COMPAT_MODE" value="false" />
|
|
<parameter name="MEM_IF_DQSN_EN" value="true" />
|
|
<parameter name="ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="AC_ROM_MR0" value="0001000010001" />
|
|
<parameter name="MEM_TRAS" value="11" />
|
|
<parameter name="ENUM_ECC_DQ_WIDTH" value="ECC_DQ_WIDTH_0" />
|
|
<parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP" value="0" />
|
|
<parameter name="MEM_TINIT_US" value="500" />
|
|
<parameter name="CTL_SELF_REFRESH" value="0" />
|
|
<parameter name="ENUM_MEM_IF_TWTR" value="TWTR_4" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
|
|
<parameter name="ENUM_USER_ECC_EN" value="DISABLE" />
|
|
<parameter name="AC_ROM_MR2" value="0000000000000" />
|
|
<parameter name="AC_ROM_MR1" value="0000000000000" />
|
|
<parameter name="AC_ROM_MR3" value="0000000000000" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH" value="0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID" value="0" />
|
|
<parameter name="ENUM_CFG_BURST_LENGTH" value="BL_8" />
|
|
<parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_2" value="WEIGHT_0" />
|
|
<parameter name="MEM_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_4" value="WEIGHT_0" />
|
|
<parameter name="MEM_SRT" value="Normal" />
|
|
<parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
|
|
<parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
|
|
<parameter name="CFG_TYPE" value="2" />
|
|
<parameter name="ENUM_CLR_INTR" value="NO_CLR_INTR" />
|
|
<parameter name="ENUM_CPORT3_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_1" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_2" value="WEIGHT_0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID" value="0" />
|
|
<parameter name="ENUM_PRIORITY_5_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_0" value="WEIGHT_0" />
|
|
<parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="AV_PORT_1_CONNECT_TO_CV_PORT" value="1" />
|
|
<parameter name="CV_PORT_5_CONNECT_TO_AV_PORT" value="5" />
|
|
<parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="MEM_TMRD_CK" value="4" />
|
|
<parameter name="CFG_INTERFACE_WIDTH" value="8" />
|
|
<parameter name="DEVICE_DEPTH" value="1" />
|
|
<parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
|
|
<parameter name="CV_ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_MASK_CORR_DROPPED_INTR" value="DISABLED" />
|
|
<parameter name="ENUM_ATTR_STATIC_CONFIG_VALID" value="DISABLED" />
|
|
<parameter name="CTL_ENABLE_WDATA_PATH_LATENCY" value="false" />
|
|
<parameter name="ENUM_CLOCK_OFF_2" value="DISABLED" />
|
|
<parameter name="ENUM_CLOCK_OFF_1" value="DISABLED" />
|
|
<parameter name="ENUM_CLOCK_OFF_0" value="DISABLED" />
|
|
<parameter name="CFG_BURST_LENGTH" value="8" />
|
|
<parameter name="ENUM_CLOCK_OFF_5" value="DISABLED" />
|
|
<parameter name="ENUM_CLOCK_OFF_4" value="DISABLED" />
|
|
<parameter name="ENUM_CLOCK_OFF_3" value="DISABLED" />
|
|
<parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="CFG_MEM_CLK_ENTRY_CYCLES" value="20" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
|
|
<parameter name="ENUM_CFG_INTERFACE_WIDTH" value="DWIDTH_32" />
|
|
<parameter name="ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="MEM_ATCL_INT" value="0" />
|
|
<parameter name="ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="CV_ENUM_CPORT4_TYPE" value="DISABLE" />
|
|
<parameter name="TIMING_TDSS" value="0.18" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_1" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_0" value="WEIGHT_0" />
|
|
<parameter name="CSR_BE_WIDTH" value="4" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_2" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_4" value="WEIGHT_0" />
|
|
<parameter name="MEM_TRTP_NS" value="7.5" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_2" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_3" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_0" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_1" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_4" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_5" value="0" />
|
|
<parameter name="ENUM_PRIORITY_3_5" value="WEIGHT_0" />
|
|
<parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
|
|
<parameter name="AP_MODE" value="false" />
|
|
<parameter name="ENUM_PRIORITY_3_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_3_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_3_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_3_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_3_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_MEM_IF_MEMTYPE" value="DDR3_SDRAM" />
|
|
<parameter name="MEM_PD" value="DLL off" />
|
|
<parameter name="TIMING_TDSH" value="0.18" />
|
|
<parameter name="CTL_AUTOPCH_EN" value="false" />
|
|
<parameter name="ENUM_PDN_EXIT_CYCLES" value="SLOW_EXIT" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID" value="0" />
|
|
<parameter name="MEM_DQ_WIDTH" value="8" />
|
|
<parameter name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES" value="" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="FLY_BY" value="true" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="TIMING_TQSH" value="0.4" />
|
|
<parameter name="CV_ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="LSB_RFIFO_PORT_0" value="5" />
|
|
<parameter name="AFI_CLK_PAIR_COUNT" value="1" />
|
|
<parameter name="HARD_EMIF" value="false" />
|
|
<parameter name="LSB_RFIFO_PORT_5" value="5" />
|
|
<parameter name="LSB_RFIFO_PORT_3" value="5" />
|
|
<parameter name="LSB_RFIFO_PORT_4" value="5" />
|
|
<parameter name="LSB_RFIFO_PORT_1" value="5" />
|
|
<parameter name="CV_ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="LSB_RFIFO_PORT_2" value="5" />
|
|
<parameter name="MEM_CLK_MAX_NS" value="1.25" />
|
|
<parameter name="DWIDTH_RATIO" value="4" />
|
|
<parameter name="INTG_MEM_IF_TREFI" value="3120" />
|
|
<parameter name="CFG_CLR_INTR" value="0" />
|
|
<parameter name="ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_ENABLE_NO_DM" value="DISABLED" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="MEM_TINIT_CK" value="150000" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
|
|
<parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
|
|
<parameter name="MEM_BL" value="OTF" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
|
|
<parameter name="ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
|
|
<parameter name="MEM_BT" value="Sequential" />
|
|
<parameter name="ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
|
|
<parameter name="CONTROLLER_LATENCY" value="5" />
|
|
<parameter name="MEM_TRTP" value="3" />
|
|
<parameter name="ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
|
|
<parameter name="ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
|
|
<parameter name="MEM_DQ_PER_DQS" value="8" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CTL_REGDIMM_ENABLED" value="REGDIMM_DISABLED" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_2" value="WEIGHT_0" />
|
|
<parameter name="ENABLE_BURST_MERGE" value="false" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_CPORT5_TYPE" value="DISABLE" />
|
|
<parameter name="ENUM_ENABLE_BURST_TERMINATE" value="DISABLED" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
|
|
<parameter name="VECT_ATTR_DEBUG_SELECT_BYTE" value="0" />
|
|
<parameter name="CV_PORT_4_CONNECT_TO_AV_PORT" value="4" />
|
|
<parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
|
|
<parameter name="DEVICE_WIDTH" value="1" />
|
|
<parameter name="SOPC_COMPAT_RESET" value="false" />
|
|
<parameter name="ENUM_ENABLE_PIPELINEGLOBAL" value="DISABLED" />
|
|
<parameter name="AFI_CONTROL_WIDTH" value="2" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_6" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_7" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_4" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_5" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_2" value="0" />
|
|
<parameter name="MEM_IF_DM_PINS_EN" value="true" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_3" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_0" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_1" value="0" />
|
|
<parameter name="ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
|
|
<parameter name="ENUM_SINGLE_READY_3" value="CONCATENATE_RDY" />
|
|
<parameter name="ENUM_SINGLE_READY_1" value="CONCATENATE_RDY" />
|
|
<parameter name="ENUM_SINGLE_READY_2" value="CONCATENATE_RDY" />
|
|
<parameter name="ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_GEN_DBE" value="GEN_DBE_DISABLED" />
|
|
<parameter name="ENUM_SINGLE_READY_0" value="CONCATENATE_RDY" />
|
|
<parameter name="DATA_RATE_RATIO" value="2" />
|
|
<parameter name="ENUM_ENABLE_DQS_TRACKING" value="DISABLED" />
|
|
<parameter name="ENUM_ENABLE_BONDING_3" value="DISABLED" />
|
|
<parameter name="ENUM_ENABLE_BONDING_2" value="DISABLED" />
|
|
<parameter name="ENUM_ENABLE_BONDING_5" value="DISABLED" />
|
|
<parameter name="ENUM_MEM_IF_TCL" value="TCL_6" />
|
|
<parameter name="ENUM_ENABLE_BONDING_4" value="DISABLED" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="LOW_LATENCY" value="false" />
|
|
<parameter name="ENUM_ENABLE_BONDING_1" value="DISABLED" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
|
|
<parameter name="ENUM_ENABLE_BONDING_0" value="DISABLED" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="ENUM_MEM_IF_DQ_PER_CHIP" value="MEM_IF_DQ_PER_CHIP_8" />
|
|
<parameter name="ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="RATE" value="Half" />
|
|
<parameter name="MR1_WL" value="0" />
|
|
<parameter name="POWER_OF_TWO_BUS" value="false" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="MR3_MPR_RF" value="0" />
|
|
<parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
|
|
<parameter name="DEBUG_MODE" value="false" />
|
|
<parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
|
|
<parameter name="CFG_STARVE_LIMIT" value="10" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT" value="0" />
|
|
<parameter name="ENUM_PRIORITY_7_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_7_4" value="WEIGHT_0" />
|
|
<parameter name="MEM_CLK_MAX_PS" value="1250.0" />
|
|
<parameter name="ENUM_PRIORITY_7_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_7_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_7_0" value="WEIGHT_0" />
|
|
<parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
|
|
<parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
|
|
<parameter name="ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
|
|
<parameter name="MEM_BURST_LENGTH" value="8" />
|
|
<parameter name="ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
|
|
<parameter name="ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
|
|
<parameter name="ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
|
|
<parameter name="MEM_TRRD" value="2" />
|
|
<parameter name="ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
|
|
<parameter name="ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
|
|
<parameter name="ENUM_PRIORITY_7_5" value="WEIGHT_0" />
|
|
<parameter name="MEM_INIT_EN" value="false" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH" value="0" />
|
|
<parameter name="ADDR_RATE_RATIO" value="1" />
|
|
<parameter name="CFG_SELF_RFSH_EXIT_CYCLES" value="512" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
|
|
<parameter name="CTL_REGDIMM_ENABLED" value="false" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_1" value="5" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_0" value="5" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_0" value="0" />
|
|
<parameter name="CV_ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_GEN_SBE" value="GEN_SBE_DISABLED" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
|
|
<parameter name="ENUM_ENABLE_BONDING_WRAPBACK" value="DISABLED" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_2" value="0" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_1" value="0" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
|
|
<parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
|
|
<parameter name="ENUM_THLD_JAR1_4" value="THRESHOLD_32" />
|
|
<parameter name="MEM_RTT_NOM" value="ODT Disabled" />
|
|
<parameter name="ENUM_THLD_JAR1_5" value="THRESHOLD_32" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_4" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_3" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_5" value="0" />
|
|
<parameter name="AFI_WRANK_WIDTH" value="2" />
|
|
<parameter name="LRDIMM" value="false" />
|
|
<parameter name="MR1_DLL" value="0" />
|
|
<parameter name="CFG_ADDR_ORDER" value="0" />
|
|
<parameter name="ENUM_WR_PORT_INFO_0" value="USE_NO" />
|
|
<parameter name="CTL_ODT_ENABLED" value="false" />
|
|
<parameter name="ENUM_WR_PORT_INFO_5" value="USE_NO" />
|
|
<parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ENUM_WR_PORT_INFO_1" value="USE_NO" />
|
|
<parameter name="ENUM_WR_PORT_INFO_2" value="USE_NO" />
|
|
<parameter name="ENUM_WR_PORT_INFO_3" value="USE_NO" />
|
|
<parameter name="ENUM_WR_PORT_INFO_4" value="USE_NO" />
|
|
<parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
|
|
<parameter name="ENUM_THLD_JAR1_0" value="THRESHOLD_32" />
|
|
<parameter name="ENUM_THLD_JAR1_1" value="THRESHOLD_32" />
|
|
<parameter name="ENUM_THLD_JAR1_2" value="THRESHOLD_32" />
|
|
<parameter name="ENUM_THLD_JAR1_3" value="THRESHOLD_32" />
|
|
<parameter name="ENUM_CPORT2_TYPE" value="DISABLE" />
|
|
<parameter name="ENUM_ENABLE_ATPG" value="DISABLED" />
|
|
<parameter name="MEM_FORMAT" value="DISCRETE" />
|
|
<parameter name="CONTROLLER_TYPE" value="nextgen_v110" />
|
|
<parameter name="AFI_WLAT_WIDTH" value="6" />
|
|
<parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
|
|
<parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
|
|
<parameter name="CTL_CS_WIDTH" value="1" />
|
|
<parameter name="ENUM_OUTPUT_REGD" value="DISABLED" />
|
|
<parameter name="MR1_ODS" value="0" />
|
|
<parameter name="MEM_TRFC" value="34" />
|
|
<parameter name="AV_PORT_4_CONNECT_TO_CV_PORT" value="4" />
|
|
<parameter name="ENUM_SYNC_MODE_1" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_SYNC_MODE_0" value="ASYNCHRONOUS" />
|
|
<parameter name="ENUM_SYNC_MODE_3" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_SYNC_MODE_2" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CPORT1_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="ENUM_SYNC_MODE_5" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CPORT4_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="ENUM_SYNC_MODE_4" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="FORCE_DQS_TRACKING" value="AUTO" />
|
|
<parameter name="ENUM_CFG_TYPE" value="DDR3" />
|
|
<parameter name="CV_ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="ADDR_ORDER" value="0" />
|
|
<parameter name="MEM_VERBOSE" value="true" />
|
|
<parameter name="HARD_PHY" value="false" />
|
|
<parameter name="MR2_SRF" value="0" />
|
|
<parameter name="ENUM_CPORT4_TYPE" value="DISABLE" />
|
|
<parameter name="ENUM_MEM_IF_BANKADDR_WIDTH" value="ADDR_WIDTH_3" />
|
|
<parameter name="ENUM_MASK_SBE_INTR" value="DISABLED" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK" value="0" />
|
|
<parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
|
|
<parameter name="ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_READ_ODT_CHIP" value="ODT_DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
|
|
<parameter name="VECT_ATTR_COUNTER_ONE_MASK" value="0" />
|
|
<parameter name="MULTICAST_EN" value="false" />
|
|
<parameter name="CV_ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
|
|
<parameter name="ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="AC_PARITY" value="false" />
|
|
<parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
|
|
<parameter name="MR1_DQS" value="0" />
|
|
<parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES" value="DISABLED" />
|
|
<parameter name="MR2_SRT" value="0" />
|
|
<parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
|
|
<parameter name="ENUM_MEM_IF_TMRD" value="" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_3" value="5" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_2" value="5" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_5" value="5" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_4" value="5" />
|
|
<parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
|
|
<parameter name="MR1_QOFF" value="0" />
|
|
<parameter name="MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="MEM_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="CV_ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_MEM_IF_TWR" value="TWR_6" />
|
|
<parameter name="ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="MEM_TYPE" value="DDR3" />
|
|
<parameter name="ENUM_MEM_IF_TRAS" value="TRAS_16" />
|
|
<parameter name="ENUM_INC_SYNC" value="FIFO_SET_2" />
|
|
<parameter name="ENUM_MEM_IF_TRCD" value="TRCD_6" />
|
|
<parameter name="TIMING_TIS" value="170" />
|
|
<parameter name="ENUM_PRIORITY_0_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_0_5" value="WEIGHT_0" />
|
|
<parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
|
|
<parameter name="ENUM_PRIORITY_0_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_0_3" value="WEIGHT_0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID" value="0" />
|
|
<parameter name="ENUM_PRIORITY_0_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_0_1" value="WEIGHT_0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR" value="0" />
|
|
<parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
|
|
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
|
|
<parameter name="AVL_ADDR_WIDTH" value="25" />
|
|
<parameter name="CV_ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="MAX10_CFG" value="true" />
|
|
<parameter name="CFG_REORDER_DATA" value="true" />
|
|
<parameter name="ENUM_ENABLE_FAST_EXIT_PPD" value="DISABLED" />
|
|
<parameter name="ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="CONTINUE_AFTER_CAL_FAIL" value="false" />
|
|
<parameter name="AFI_RRANK_WIDTH" value="2" />
|
|
<parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="MR3_MPR" value="0" />
|
|
<parameter name="ENUM_CFG_STARVE_LIMIT" value="STARVE_LIMIT_32" />
|
|
<parameter name="MEM_IF_ODT_WIDTH" value="1" />
|
|
<parameter name="TIMING_TDQSCKDL" value="1200" />
|
|
<parameter name="TIMING_TDQSCKDS" value="450" />
|
|
<parameter name="TIMING_TDQSCKDM" value="900" />
|
|
<parameter name="ENUM_MEM_IF_TCCD" value="TCCD_4" />
|
|
<parameter name="CV_ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="AVL_BE_WIDTH" value="4" />
|
|
<parameter name="AVL_MAX_SIZE" value="4" />
|
|
<parameter name="ENUM_CTL_USR_REFRESH" value="CTL_USR_REFRESH_DISABLED" />
|
|
<parameter name="CV_ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CFG_ERRCMD_FIFO_REG" value="0" />
|
|
<parameter name="ENUM_DISABLE_MERGING" value="MERGING_ENABLED" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CTL_ADDR_ORDER" value="CHIP_BANK_ROW_COL" />
|
|
<parameter name="AFI_DM_WIDTH" value="4" />
|
|
<parameter name="ENUM_CTL_ECC_ENABLED" value="CTL_ECC_DISABLED" />
|
|
<parameter name="BYTE_ENABLE" value="true" />
|
|
<parameter name="USE_SHADOW_REGS" value="false" />
|
|
<parameter name="ENUM_MEM_IF_CS_WIDTH" value="MEM_IF_CS_WIDTH_1" />
|
|
<parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="CV_ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="ENUM_CAL_REQ" value="DISABLED" />
|
|
<parameter name="ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="MEM_IF_DQ_WIDTH" value="8" />
|
|
<parameter name="ADDR_CMD_DDR" value="0" />
|
|
<parameter name="MR3_MPR_AA" value="0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_1" value="0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_0" value="0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_3" value="0" />
|
|
<parameter name="MEM_TFAW_NS" value="30.0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_2" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_5" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_4" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_3" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_2" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_1" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_0" value="0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_5" value="0" />
|
|
<parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_4" value="0" />
|
|
<parameter name="AFI_CLK_EN_WIDTH" value="2" />
|
|
<parameter name="TIMING_TQH" value="0.38" />
|
|
<parameter name="ENUM_MEM_IF_DWIDTH" value="MEM_IF_DWIDTH_32" />
|
|
<parameter name="ENUM_RD_PORT_INFO_2" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_PORT_INFO_3" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_PORT_INFO_4" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
|
|
<parameter name="ENUM_MEM_IF_SPEEDBIN" value="DDR3_1066_6_6_6" />
|
|
<parameter name="ENUM_RD_PORT_INFO_5" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
|
|
<parameter name="ENUM_CPORT0_TYPE" value="DISABLE" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_MEM_IF_TRP" value="TRP_6" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_1" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_5" value="WEIGHT_0" />
|
|
<parameter name="HHP_HPS" value="false" />
|
|
<parameter name="CV_ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="AVL_SIZE_WIDTH" value="3" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING" value="0" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
|
|
<parameter name="RDBUFFER_ADDR_WIDTH" value="7" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
|
|
<parameter name="ENUM_MEM_IF_TRC" value="TRC_22" />
|
|
<parameter name="ENUM_RD_PORT_INFO_0" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_PORT_INFO_1" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
|
|
<parameter name="DAT_DATA_WIDTH" value="32" />
|
|
<parameter
|
|
name="CPORT_TYPE_PORT"
|
|
value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
|
|
<parameter name="AC_ROM_MR1_CALIB" value="" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_5" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_4" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_3" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_2" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_1" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_0" value="1" />
|
|
<parameter name="SPEED_GRADE" value="6" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_1" value="WEIGHT_0" />
|
|
<parameter name="MEM_TRCD_NS" value="13.75" />
|
|
<parameter name="ENUM_PRIORITY_4_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_0" value="WEIGHT_0" />
|
|
<parameter name="AFI_ADDR_WIDTH" value="28" />
|
|
<parameter name="ENUM_PRIORITY_4_1" value="WEIGHT_0" />
|
|
<parameter name="USE_HPS_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="EXPORT_CSR_PORT" value="false" />
|
|
<parameter name="CTL_SELF_REFRESH_EN" value="false" />
|
|
<parameter name="MSB_WFIFO_PORT_0" value="5" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_5" value="5" />
|
|
<parameter name="MSB_WFIFO_PORT_1" value="5" />
|
|
<parameter name="TIMING_TDS" value="10" />
|
|
<parameter name="MSB_WFIFO_PORT_2" value="5" />
|
|
<parameter name="MSB_WFIFO_PORT_3" value="5" />
|
|
<parameter name="MSB_WFIFO_PORT_4" value="5" />
|
|
<parameter name="MSB_WFIFO_PORT_5" value="5" />
|
|
<parameter name="CFG_TCCD" value="1" />
|
|
<parameter name="ENUM_MEM_IF_AL" value="AL_0" />
|
|
<parameter name="ENUM_TEST_MODE" value="NORMAL_MODE" />
|
|
<parameter name="MEM_CS_WIDTH" value="1" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_0" value="5" />
|
|
<parameter name="ENUM_CPORT0_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_2" value="5" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_1" value="5" />
|
|
<parameter name="TIMING_TDH" value="45" />
|
|
<parameter name="AV_PORT_3_CONNECT_TO_CV_PORT" value="3" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_4" value="5" />
|
|
<parameter name="SCC_DATA_WIDTH" value="1" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_3" value="5" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC" value="0" />
|
|
<parameter name="CV_ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="MEM_TREFI_US" value="7.8" />
|
|
<parameter name="USE_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_LRDIMM_ENABLED" value="false" />
|
|
<parameter name="ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_MEM_IF_DQS_WIDTH" value="DQS_WIDTH_4" />
|
|
<parameter name="CTL_ZQCAL_EN" value="false" />
|
|
<parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
|
|
<parameter name="ENUM_DFX_BYPASS_ENABLE" value="DFX_BYPASS_DISABLED" />
|
|
<parameter name="AC_ROM_MR0_CALIB" value="" />
|
|
<parameter name="MEM_TWR_NS" value="15.0" />
|
|
<parameter name="ENUM_CTRL_WIDTH" value="DATA_WIDTH_64_BIT" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_4" value="WEIGHT_0" />
|
|
<parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_CPORT2_TYPE" value="DISABLE" />
|
|
<parameter name="AFI_RLAT_WIDTH" value="6" />
|
|
<parameter name="ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="MEM_TRP" value="5" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR" value="0" />
|
|
<parameter name="ENUM_USE_ALMOST_EMPTY_1" value="EMPTY" />
|
|
<parameter name="ENUM_USE_ALMOST_EMPTY_2" value="EMPTY" />
|
|
<parameter name="ENUM_USE_ALMOST_EMPTY_3" value="EMPTY" />
|
|
<parameter name="MEM_TRRD_NS" value="6.0" />
|
|
<parameter name="CV_PORT_3_CONNECT_TO_AV_PORT" value="3" />
|
|
<parameter name="ENUM_DELAY_BONDING" value="BONDING_LATENCY_0" />
|
|
<parameter name="ENUM_USE_ALMOST_EMPTY_0" value="EMPTY" />
|
|
<parameter name="LSB_WFIFO_PORT_4" value="5" />
|
|
<parameter name="LSB_WFIFO_PORT_5" value="5" />
|
|
<parameter name="LSB_WFIFO_PORT_2" value="5" />
|
|
<parameter name="LSB_WFIFO_PORT_3" value="5" />
|
|
<parameter name="MR0_CAS_LATENCY" value="1" />
|
|
<parameter name="LSB_WFIFO_PORT_0" value="5" />
|
|
<parameter name="LSB_WFIFO_PORT_1" value="5" />
|
|
<parameter name="CFG_PDN_EXIT_CYCLES" value="10" />
|
|
<parameter name="MR0_WR" value="1" />
|
|
<parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_2" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_1" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_3" value="WEIGHT_0" />
|
|
<parameter name="LOCAL_ID_WIDTH" value="8" />
|
|
<parameter name="TIMING_TDQSS" value="0.27" />
|
|
<parameter name="TIMING_TDQSQ" value="100" />
|
|
<parameter name="ENUM_PRIORITY_2_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_2_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_PRIORITY_2_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_2_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_2_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="ENUM_PRIORITY_2_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="MEM_ASR" value="Manual" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_2" value="FALSE" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_3" value="FALSE" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_0" value="FALSE" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_1" value="FALSE" />
|
|
<parameter name="ENUM_REORDER_DATA" value="DATA_REORDERING" />
|
|
<parameter name="NEXTGEN" value="true" />
|
|
<parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
|
|
<parameter name="PRIORITY_PORT_0" value="0" />
|
|
<parameter name="MEM_TWR" value="5" />
|
|
<parameter name="PRIORITY_PORT_2" value="0" />
|
|
<parameter name="PRIORITY_PORT_1" value="0" />
|
|
<parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
|
|
<parameter name="CPORT_TYPE_PORT_3" value="0" />
|
|
<parameter name="MEM_IF_DQS_WIDTH" value="1" />
|
|
<parameter name="CPORT_TYPE_PORT_2" value="0" />
|
|
<parameter name="CPORT_TYPE_PORT_1" value="0" />
|
|
<parameter name="TIMING_TIH" value="120" />
|
|
<parameter name="CPORT_TYPE_PORT_0" value="0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD" value="0" />
|
|
<parameter name="USE_AXI_ADAPTOR" value="false" />
|
|
<parameter name="PRIORITY_PORT_4" value="0" />
|
|
<parameter name="PRIORITY_PORT_3" value="0" />
|
|
<parameter name="PRIORITY_PORT_5" value="0" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
|
|
<parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
|
|
<parameter name="ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
|
|
<parameter name="NUM_OF_PORTS" value="1" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_5" value="WEIGHT_0" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
|
|
<parameter name="ENUM_CPORT3_TYPE" value="DISABLE" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
|
|
<parameter name="CPORT_TYPE_PORT_5" value="0" />
|
|
<parameter name="CPORT_TYPE_PORT_4" value="0" />
|
|
<parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_1" value="5" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_0" value="5" />
|
|
<parameter name="ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_5" value="5" />
|
|
<parameter name="MEM_TFAW" value="10" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_4" value="5" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_3" value="5" />
|
|
<parameter name="CV_ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_2" value="5" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ddr3_ram_c0.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_odt_gen.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_arbiter.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_burst_gen.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_cmd_gen.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_csr.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_buffer.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_buffer_manager.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_burst_tracking.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_dataid_manager.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_fifo.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_list.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rdata_path.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_wdata_path.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_define.iv"
|
|
type="VERILOG_INCLUDE"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_input_if.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rank_timer.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_sideband.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_tbp.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_timing_param.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_controller.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_controller_st_top.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller/alt_mem_if_nextgen_ddr3_controller_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
|
|
</sourceFiles>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller_core/alt_mem_if_nextgen_ddr3_controller_core_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/guava-27.1-jre.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/hamcrest-all-1.3.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr_controller_110/rtl/alt_mem_ddrx_mm_st_converter/alt_mem_ddrx_mm_st_converter_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys_ddr3_ram" as="c0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 228 starting:altera_mem_if_nextgen_ddr3_controller "submodules/q_sys_ddr3_ram_c0"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>5</b> modules, <b>8</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>submodules/alt_mem_if_nextgen_ddr3_controller_core</b>"]]></message>
|
|
<message level="Debug" culprit="c0"><![CDATA["<b>c0</b>" reuses <b>alt_mem_ddrx_mm_st_converter</b> "<b>submodules/alt_mem_ddrx_mm_st_converter</b>"]]></message>
|
|
<message level="Info" culprit="c0"><![CDATA["<b>ddr3_ram</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller</b> "<b>c0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 6 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core"</message>
|
|
<message level="Info" culprit="ng0"><![CDATA["<b>c0</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>ng0</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 5 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter"</message>
|
|
<message level="Info" culprit="a0"><![CDATA["<b>c0</b>" instantiated <b>alt_mem_ddrx_mm_st_converter</b> "<b>a0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_eth_tse_mac:19.1:CORE_VERSION=4865,CRC32CHECK16BIT=0,CRC32DWIDTH=8,CRC32GENDELAY=6,CRC32S1L2_EXTERN=false,CUST_VERSION=0,DEVICE_FAMILY=MAX10,EG_ADDR=11,EG_FIFO=2048,ENABLE_ECC=false,ENABLE_ENA=32,ENABLE_EXTENDED_STAT_REG=false,ENABLE_GMII_LOOPBACK=true,ENABLE_HD_LOGIC=true,ENABLE_LGTH_CHECK=true,ENABLE_MAC_FLOW_CTRL=false,ENABLE_MAC_RX_VLAN=false,ENABLE_MAC_TXADDR_SET=true,ENABLE_MAC_TX_VLAN=false,ENABLE_MAGIC_DETECT=true,ENABLE_MDIO=true,ENABLE_PADDING=true,ENABLE_SHIFT16=true,ENABLE_SUP_ADDR=false,ENA_HASH=false,GBIT_ONLY=true,ING_ADDR=11,ING_FIFO=2048,INSERT_TA=false,MBIT_ONLY=true,MDIO_CLK_DIV=40,RAM_TYPE=AUTO,REDUCED_CONTROL=false,REDUCED_INTERFACE_ENA=true,RESET_LEVEL=1,STAT_CNT_ENA=true,SYNCHRONIZER_DEPTH=3,USE_SYNC_RESET=true,connect_to_pcs=false,ifGMII=RGMII,use_mac_clken=false,use_misc_ports=true"
|
|
instancePathKey="q_sys:.:eth_tse:.:i_tse_mac"
|
|
kind="altera_eth_tse_mac"
|
|
version="19.1"
|
|
name="altera_eth_tse_mac">
|
|
<parameter name="CORE_VERSION" value="4865" />
|
|
<parameter name="CRC32GENDELAY" value="6" />
|
|
<parameter name="ENABLE_GMII_LOOPBACK" value="true" />
|
|
<parameter name="connect_to_pcs" value="false" />
|
|
<parameter name="ENABLE_MAC_RX_VLAN" value="false" />
|
|
<parameter name="DEVICE_FAMILY" value="MAX10" />
|
|
<parameter name="RAM_TYPE" value="AUTO" />
|
|
<parameter name="ifGMII" value="RGMII" />
|
|
<parameter name="use_mac_clken" value="false" />
|
|
<parameter name="ENABLE_LGTH_CHECK" value="true" />
|
|
<parameter name="MBIT_ONLY" value="true" />
|
|
<parameter name="CUST_VERSION" value="0" />
|
|
<parameter name="REDUCED_INTERFACE_ENA" value="true" />
|
|
<parameter name="ENABLE_MDIO" value="true" />
|
|
<parameter name="CRC32CHECK16BIT" value="0" />
|
|
<parameter name="ING_ADDR" value="11" />
|
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|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_34.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_1246.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_14_44.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_a_fifo_opt_36_10.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_gray_cnt.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_sdpm_altsyncram.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_bin_cnt.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ph_calculator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_sdpm_gen.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x10.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x10_wrapper.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x14.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x14_wrapper.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x2.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x2_wrapper.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x23.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x23_wrapper.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x36.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x36_wrapper.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x40.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x40_wrapper.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_dec_x30.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_enc_x30_wrapper.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_ecc_status_crosser.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.ocp"
|
|
type="OTHER"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.ocp"
|
|
type="OTHER"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_eth_tse_mac.sdc"
|
|
type="SDC"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/ethernet/tse_ucores/altera_eth_tse_mac/altera_eth_tse_mac_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_eth_tse" as="i_tse_mac" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 229 starting:altera_eth_tse_mac "submodules/altera_eth_tse_mac"</message>
|
|
<message level="Info" culprit="i_tse_mac"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_eth_tse_mac</b> "<b>i_tse_mac</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_gpio_lite:19.1:ASYNC_MODE=none,BUFFER_TYPE=single-ended,BUS_HOLD=false,DEVICE_FAMILY=MAX 10,ENABLE_CLOCK_ENA_PORT=false,ENABLE_HR_CLOCK=false,ENABLE_NSLEEP_PORT=false,ENABLE_OE_HALF_CYCLE_DELAY=true,ENABLE_OE_PORT=false,ENABLE_PHASE_DETECTOR_FOR_CK=false,ENABLE_PHASE_INVERT_CTRL_PORT=false,INVERT_CLKDIV_INPUT_CLOCK=false,INVERT_INPUT_CLOCK=false,INVERT_OE_INCLOCK=false,INVERT_OUTPUT=false,INVERT_OUTPUT_CLOCK=false,OPEN_DRAIN_OUTPUT=false,PIN_TYPE=input,REGISTER_MODE=ddr,SET_REGISTER_OUTPUTS_HIGH=false,SIZE=4,SYNC_MODE=none,USE_ADVANCED_DDR_FEATURES=false,USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY=false,USE_DDIO_REG_TO_DRIVE_OE=false,USE_ONE_REG_TO_DRIVE_OE=false,gui_bus_hold=false,gui_clock_enable=false,gui_enable_aclr_port=false,gui_enable_aset_port=false,gui_enable_hr_clock=false,gui_enable_invert_hr_clock_port=false,gui_enable_nsleep_port=false,gui_enable_oe_half_cycle_delay=true,gui_enable_oe_port=false,gui_enable_oe_port_off_shadow=false,gui_enable_oe_port_on_shadow=true,gui_enable_phase_detector_for_ck=false,gui_enable_phase_detector_for_ck_off_shadow=false,gui_enable_sclr_port=false,gui_invert_clkdiv_input_clock=false,gui_invert_input_clock=false,gui_invert_oe_inclock=false,gui_invert_output=false,gui_invert_output_clock=false,gui_io_reg_mode=ddr,gui_open_drain=false,gui_pseudo_diff_buf=false,gui_set_registers_to_power_up_high=false,gui_true_diff_buf=false,gui_use_advanced_ddr_features=false,gui_use_ddio_reg_to_drive_oe=false,gui_use_ddio_reg_to_drive_oe_off_shadow=false,gui_use_hardened_ddio_input_registers=false,gui_use_register_to_drive_obuf_oe=false,gui_use_register_to_drive_obuf_oe_off_shadow=false"
|
|
instancePathKey="q_sys:.:eth_tse:.:rgmii_in4_0"
|
|
kind="altera_gpio_lite"
|
|
version="19.1"
|
|
name="altera_gpio_lite">
|
|
<parameter name="USE_ONE_REG_TO_DRIVE_OE" value="false" />
|
|
<parameter name="gui_use_hardened_ddio_input_registers" value="false" />
|
|
<parameter name="SYNC_MODE" value="none" />
|
|
<parameter name="SET_REGISTER_OUTPUTS_HIGH" value="false" />
|
|
<parameter name="REGISTER_MODE" value="ddr" />
|
|
<parameter name="gui_set_registers_to_power_up_high" value="false" />
|
|
<parameter name="INVERT_INPUT_CLOCK" value="false" />
|
|
<parameter name="USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY" value="false" />
|
|
<parameter name="gui_enable_invert_hr_clock_port" value="false" />
|
|
<parameter name="SIZE" value="4" />
|
|
<parameter name="BUFFER_TYPE" value="single-ended" />
|
|
<parameter name="gui_enable_sclr_port" value="false" />
|
|
<parameter name="ENABLE_CLOCK_ENA_PORT" value="false" />
|
|
<parameter name="gui_true_diff_buf" value="false" />
|
|
<parameter name="gui_enable_oe_port_off_shadow" value="false" />
|
|
<parameter name="ENABLE_NSLEEP_PORT" value="false" />
|
|
<parameter name="gui_use_ddio_reg_to_drive_oe_off_shadow" value="false" />
|
|
<parameter name="ENABLE_OE_PORT" value="false" />
|
|
<parameter name="gui_enable_nsleep_port" value="false" />
|
|
<parameter name="USE_DDIO_REG_TO_DRIVE_OE" value="false" />
|
|
<parameter name="INVERT_OE_INCLOCK" value="false" />
|
|
<parameter name="gui_invert_input_clock" value="false" />
|
|
<parameter name="gui_bus_hold" value="false" />
|
|
<parameter name="OPEN_DRAIN_OUTPUT" value="false" />
|
|
<parameter name="BUS_HOLD" value="false" />
|
|
<parameter name="INVERT_CLKDIV_INPUT_CLOCK" value="false" />
|
|
<parameter name="USE_ADVANCED_DDR_FEATURES" value="false" />
|
|
<parameter name="ENABLE_OE_HALF_CYCLE_DELAY" value="true" />
|
|
<parameter name="PIN_TYPE" value="input" />
|
|
<parameter name="gui_io_reg_mode" value="ddr" />
|
|
<parameter name="gui_enable_phase_detector_for_ck_off_shadow" value="false" />
|
|
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ENABLE_PHASE_DETECTOR_FOR_CK" value="false" />
|
|
<parameter name="gui_use_ddio_reg_to_drive_oe" value="false" />
|
|
<parameter name="gui_invert_output_clock" value="false" />
|
|
<parameter name="gui_pseudo_diff_buf" value="false" />
|
|
<parameter name="gui_invert_output" value="false" />
|
|
<parameter name="gui_invert_oe_inclock" value="false" />
|
|
<parameter name="ASYNC_MODE" value="none" />
|
|
<parameter name="ENABLE_HR_CLOCK" value="false" />
|
|
<parameter name="ENABLE_PHASE_INVERT_CTRL_PORT" value="false" />
|
|
<parameter name="gui_invert_clkdiv_input_clock" value="false" />
|
|
<parameter name="gui_enable_oe_port_on_shadow" value="true" />
|
|
<parameter name="gui_use_register_to_drive_obuf_oe" value="false" />
|
|
<parameter name="gui_enable_aclr_port" value="false" />
|
|
<parameter name="gui_use_advanced_ddr_features" value="false" />
|
|
<parameter name="gui_enable_phase_detector_for_ck" value="false" />
|
|
<parameter name="INVERT_OUTPUT_CLOCK" value="false" />
|
|
<parameter name="gui_enable_oe_half_cycle_delay" value="true" />
|
|
<parameter name="INVERT_OUTPUT" value="false" />
|
|
<parameter name="gui_enable_oe_port" value="false" />
|
|
<parameter name="gui_clock_enable" value="false" />
|
|
<parameter name="gui_use_register_to_drive_obuf_oe_off_shadow" value="false" />
|
|
<parameter name="gui_enable_hr_clock" value="false" />
|
|
<parameter name="gui_enable_aset_port" value="false" />
|
|
<parameter name="gui_open_drain" value="false" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_gpio_lite/altera_gpio_lite_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_eth_tse"
|
|
as="rgmii_in4_0,rgmii_in1_0,rgmii_out4_0,rgmii_out1_0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 228 starting:altera_gpio_lite "submodules/altera_gpio_lite"</message>
|
|
<message level="Info" culprit="rgmii_in4_0"><![CDATA["<b>eth_tse</b>" instantiated <b>altera_gpio_lite</b> "<b>rgmii_in4_0</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_generic_quad_spi_controller:19.1:CS_WIDTH=1,IO_MODE=QUAD(soft_asmiblock:19.1:CS_WIDTH=1,IO_MODE=QUAD)"
|
|
instancePathKey="q_sys:.:ext_flash:.:soft_asmiblock_instance_name"
|
|
kind="altera_generic_quad_spi_controller"
|
|
version="19.1"
|
|
name="q_sys_ext_flash_soft_asmiblock_instance_name">
|
|
<parameter name="IO_MODE" value="QUAD" />
|
|
<parameter name="CS_WIDTH" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_soft_asmiblock_instance_name.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/soft_asmiblock.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles/>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/soft_asmiblock_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys_ext_flash" as="soft_asmiblock_instance_name" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_soft_asmiblock_instance_name"</message>
|
|
<message level="Debug" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" reuses <b>soft_asmiblock</b> "<b>submodules/soft_asmiblock</b>"]]></message>
|
|
<message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock"</message>
|
|
<message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" instantiated <b>soft_asmiblock</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_generic_quad_spi_controller:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_USED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_USED,PORT_ILLEGAL_ERASE=PORT_USED,PORT_ILLEGAL_WRITE=PORT_USED,PORT_RDID_OUT=PORT_USED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_USED,PORT_READ_RDID=PORT_USED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_USED,PORT_SECTOR_ERASE=PORT_USED,PORT_SECTOR_PROTECT=PORT_USED,PORT_SHIFT_BYTES=PORT_USED,PORT_WREN=PORT_USED,PORT_WRITE=PORT_USED,USE_ASMIBLOCK=OFF,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true(altera_asmi_parallel:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_USED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_USED,PORT_ILLEGAL_ERASE=PORT_USED,PORT_ILLEGAL_WRITE=PORT_USED,PORT_RDID_OUT=PORT_USED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_USED,PORT_READ_RDID=PORT_USED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_USED,PORT_SECTOR_ERASE=PORT_USED,PORT_SECTOR_PROTECT=PORT_USED,PORT_SHIFT_BYTES=PORT_USED,PORT_WREN=PORT_USED,PORT_WRITE=PORT_USED,USE_ASMIBLOCK=OFF,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true)"
|
|
instancePathKey="q_sys:.:ext_flash:.:asmi_parallel_instance_name"
|
|
kind="altera_generic_quad_spi_controller"
|
|
version="19.1"
|
|
name="q_sys_ext_flash_asmi_parallel_instance_name">
|
|
<parameter name="PORT_EN4B_ADDR" value="PORT_USED" />
|
|
<parameter name="USE_EAB" value="ON" />
|
|
<parameter name="PORT_READ_SID" value="PORT_UNUSED" />
|
|
<parameter name="gui_read_rdid" value="true" />
|
|
<parameter name="gui_page_write" value="true" />
|
|
<parameter name="DEVICE_FAMILY" value="Arria V" />
|
|
<parameter name="PORT_ILLEGAL_WRITE" value="PORT_USED" />
|
|
<parameter name="FLASH_RSTPIN" value="TRUE" />
|
|
<parameter name="EPCS_TYPE" value="EPCQL512" />
|
|
<parameter name="gui_sector_protect" value="true" />
|
|
<parameter name="PORT_WRITE" value="PORT_USED" />
|
|
<parameter name="gui_fast_read" value="true" />
|
|
<parameter name="PORT_SECTOR_ERASE" value="PORT_USED" />
|
|
<parameter name="DATA_WIDTH" value="QUAD" />
|
|
<parameter name="gui_read_address" value="false" />
|
|
<parameter name="gui_sector_erase" value="true" />
|
|
<parameter name="gui_use_asmiblock" value="true" />
|
|
<parameter name="PORT_DIE_ERASE" value="PORT_UNUSED" />
|
|
<parameter name="PORT_WREN" value="PORT_USED" />
|
|
<parameter name="WRITE_DUMMY_CLK" value="0" />
|
|
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
|
|
<parameter name="gui_read_dummyclk" value="true" />
|
|
<parameter name="gui_single_write" value="false" />
|
|
<parameter name="gui_die_erase" value="false" />
|
|
<parameter name="gui_ex4b_addr" value="false" />
|
|
<parameter name="gui_use_eab" value="false" />
|
|
<parameter name="PORT_READ_DUMMYCLK" value="PORT_USED" />
|
|
<parameter name="gui_write" value="true" />
|
|
<parameter name="PORT_SHIFT_BYTES" value="PORT_USED" />
|
|
<parameter name="PORT_SECTOR_PROTECT" value="PORT_USED" />
|
|
<parameter name="gui_bulk_erase" value="false" />
|
|
<parameter name="PORT_FAST_READ" value="PORT_USED" />
|
|
<parameter name="ENABLE_SIM" value="true" />
|
|
<parameter name="PORT_READ_STATUS" value="PORT_USED" />
|
|
<parameter name="PORT_BULK_ERASE" value="PORT_UNUSED" />
|
|
<parameter name="PORT_RDID_OUT" value="PORT_USED" />
|
|
<parameter name="PORT_READ_RDID" value="PORT_USED" />
|
|
<parameter name="gui_read_status" value="true" />
|
|
<parameter name="PORT_EX4B_ADDR" value="PORT_UNUSED" />
|
|
<parameter name="PAGE_SIZE" value="256" />
|
|
<parameter name="gui_wren" value="true" />
|
|
<parameter name="gui_read_sid" value="false" />
|
|
<parameter name="PORT_ILLEGAL_ERASE" value="PORT_USED" />
|
|
<parameter name="PORT_READ_ADDRESS" value="PORT_UNUSED" />
|
|
<parameter name="INTENDED_DEVICE_FAMILY" value="" />
|
|
<parameter name="USE_ASMIBLOCK" value="OFF" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles/>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_asmi_parallel/altera_asmi_parallel_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys_ext_flash" as="asmi_parallel_instance_name" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_asmi_parallel_instance_name"</message>
|
|
<message level="Debug" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" reuses <b>altera_asmi_parallel</b> "<b>submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</b>"]]></message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>asmi_parallel_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name"</message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name">generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" instantiated <b>altera_asmi_parallel</b> "<b>asmi_parallel_instance_name</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_generic_quad_spi_controller:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None(altera_epcq_controller_core:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None)"
|
|
instancePathKey="q_sys:.:ext_flash:.:epcq_controller_instance_name"
|
|
kind="altera_generic_quad_spi_controller"
|
|
version="19.1"
|
|
name="q_sys_ext_flash_epcq_controller_instance_name">
|
|
<parameter name="ASMI_ADDR_WIDTH" value="32" />
|
|
<parameter name="ADDR_WIDTH" value="24" />
|
|
<parameter name="CHIP_SELS" value="1" />
|
|
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="IO_MODE" value="QUAD" />
|
|
<parameter name="DDASI" value="1" />
|
|
<parameter name="CS_WIDTH" value="1" />
|
|
<parameter name="deviceFeaturesSystemInfo" value="None" />
|
|
<parameter name="ASI_WIDTH" value="4" />
|
|
<parameter name="ENABLE_4BYTE_ADDR" value="1" />
|
|
<parameter name="FLASH_TYPE" value="EPCQL512" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_epcq_controller_instance_name.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles/>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_epcq_controller/altera_epcq_controller_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys_ext_flash" as="epcq_controller_instance_name" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_epcq_controller_instance_name"</message>
|
|
<message level="Debug" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" reuses <b>altera_epcq_controller_core</b> "<b>submodules/altera_epcq_controller_arb</b>"]]></message>
|
|
<message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>ext_flash</b>" instantiated <b>altera_generic_quad_spi_controller</b> "<b>epcq_controller_instance_name</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb"</message>
|
|
<message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" instantiated <b>altera_epcq_controller_core</b> "<b>epcq_controller_instance_name</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="modular_sgdma_dispatcher:19.1:BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,CSR_ADDRESS_WIDTH=3,DATA_FIFO_DEPTH=32,DATA_WIDTH=32,DESCRIPTOR_BYTEENABLE_WIDTH=16,DESCRIPTOR_FIFO_DEPTH=8,DESCRIPTOR_INTERFACE=1,DESCRIPTOR_WIDTH=128,ENHANCED_FEATURES=0,GUI_RESPONSE_PORT=2,MAX_BURST_COUNT=2,MAX_BYTE=2048,MAX_STRIDE=1,MODE=2,PREFETCHER_USE_CASE=1,PROGRAMMABLE_BURST_ENABLE=0,RESPONSE_PORT=1,STRIDE_ENABLE=0,TRANSFER_TYPE=Aligned Accesses"
|
|
instancePathKey="q_sys:.:msgdma_rx:.:dispatcher_internal"
|
|
kind="modular_sgdma_dispatcher"
|
|
version="19.1"
|
|
name="dispatcher">
|
|
<parameter name="GUI_RESPONSE_PORT" value="2" />
|
|
<parameter name="MAX_STRIDE" value="1" />
|
|
<parameter name="PREFETCHER_USE_CASE" value="1" />
|
|
<parameter name="MODE" value="2" />
|
|
<parameter name="DATA_FIFO_DEPTH" value="32" />
|
|
<parameter name="STRIDE_ENABLE" value="0" />
|
|
<parameter name="DESCRIPTOR_WIDTH" value="128" />
|
|
<parameter name="DESCRIPTOR_INTERFACE" value="1" />
|
|
<parameter name="DESCRIPTOR_FIFO_DEPTH" value="8" />
|
|
<parameter name="RESPONSE_PORT" value="1" />
|
|
<parameter name="ENHANCED_FEATURES" value="0" />
|
|
<parameter name="CSR_ADDRESS_WIDTH" value="3" />
|
|
<parameter name="BURST_ENABLE" value="0" />
|
|
<parameter name="DATA_WIDTH" value="32" />
|
|
<parameter name="BURST_WRAPPING_SUPPORT" value="0" />
|
|
<parameter name="DESCRIPTOR_BYTEENABLE_WIDTH" value="16" />
|
|
<parameter name="MAX_BYTE" value="2048" />
|
|
<parameter name="TRANSFER_TYPE" value="Aligned Accesses" />
|
|
<parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
|
|
<parameter name="MAX_BURST_COUNT" value="2" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/dispatcher.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/descriptor_buffers.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/csr_block.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/response_block.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/fifo_with_byteenables.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_signal_breakout.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_signal_breakout.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/dispatcher/dispatcher_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_msgdma_rx" as="dispatcher_internal" />
|
|
<instantiator instantiator="q_sys_msgdma_tx" as="dispatcher_internal" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher"</message>
|
|
<message level="Info" culprit="dispatcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>modular_sgdma_dispatcher</b> "<b>dispatcher_internal</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_msgdma_prefetcher:19.1:ADDRESS_WIDTH=29,AUTO_ADDRESS_WIDTH=29,DATA_BYTEENABLE_WIDTH=4,DATA_WIDTH=32,DESCRIPTOR_WIDTH=128,ENABLE_READ_BURST=0,ENHANCED_FEATURES=0,FIX_ADDRESS_WIDTH=32,GUI_DESCRIPTOR_FIFO_DEPTH=8,GUI_MAX_READ_BURST_COUNT=2,MAX_READ_BURST_COUNT=1,MAX_READ_BURST_COUNT_WIDTH=1,RESPONSE_FIFO_DEPTH=16,RESPONSE_FIFO_DEPTH_LOG2=4,USE_FIX_ADDRESS_WIDTH=0"
|
|
instancePathKey="q_sys:.:msgdma_rx:.:prefetcher_internal"
|
|
kind="altera_msgdma_prefetcher"
|
|
version="19.1"
|
|
name="altera_msgdma_prefetcher">
|
|
<parameter name="FIX_ADDRESS_WIDTH" value="32" />
|
|
<parameter name="GUI_MAX_READ_BURST_COUNT" value="2" />
|
|
<parameter name="DATA_WIDTH" value="32" />
|
|
<parameter name="ENABLE_READ_BURST" value="0" />
|
|
<parameter name="AUTO_ADDRESS_WIDTH" value="29" />
|
|
<parameter name="GUI_DESCRIPTOR_FIFO_DEPTH" value="8" />
|
|
<parameter name="MAX_READ_BURST_COUNT_WIDTH" value="1" />
|
|
<parameter name="DESCRIPTOR_WIDTH" value="128" />
|
|
<parameter name="MAX_READ_BURST_COUNT" value="1" />
|
|
<parameter name="ENHANCED_FEATURES" value="0" />
|
|
<parameter name="DATA_BYTEENABLE_WIDTH" value="4" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_read.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_write_back.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_fifo.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_interrrupt.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_msgdma_prefetcher_csr.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/prefetcher/altera_msgdma_prefetcher_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_msgdma_rx" as="prefetcher_internal" />
|
|
<instantiator instantiator="q_sys_msgdma_tx" as="prefetcher_internal" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"</message>
|
|
<message level="Info" culprit="prefetcher_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>altera_msgdma_prefetcher</b> "<b>prefetcher_internal</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="dma_write_master:19.1:ACTUAL_BYTES_TRANSFERRED_WIDTH=13,ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=6,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0"
|
|
instancePathKey="q_sys:.:msgdma_rx:.:write_mstr_internal"
|
|
kind="dma_write_master"
|
|
version="19.1"
|
|
name="write_master">
|
|
<parameter name="FIX_ADDRESS_WIDTH" value="32" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_master.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/byte_enable_generator.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/ST_to_MM_Adapter.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/write_burst_control.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/write_master/write_master_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_msgdma_rx" as="write_mstr_internal" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 222 starting:dma_write_master "submodules/write_master"</message>
|
|
<message level="Info" culprit="write_mstr_internal"><![CDATA["<b>msgdma_rx</b>" instantiated <b>dma_write_master</b> "<b>write_mstr_internal</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="dma_read_master:19.1:ADDRESS_WIDTH=28,AUTO_ADDRESS_WIDTH=28,BURST_ENABLE=0,BURST_WRAPPING_SUPPORT=0,BYTE_ENABLE_WIDTH=4,BYTE_ENABLE_WIDTH_LOG2=2,CHANNEL_ENABLE=0,CHANNEL_WIDTH=8,DATA_WIDTH=32,ERROR_ENABLE=1,ERROR_WIDTH=1,FIFO_DEPTH=32,FIFO_DEPTH_LOG2=5,FIFO_SPEED_OPTIMIZATION=1,FIX_ADDRESS_WIDTH=32,GUI_BURST_WRAPPING_SUPPORT=0,GUI_MAX_BURST_COUNT=2,GUI_PROGRAMMABLE_BURST_ENABLE=0,GUI_STRIDE_WIDTH=1,LENGTH_WIDTH=12,MAX_BURST_COUNT=1,MAX_BURST_COUNT_WIDTH=1,NUMBER_OF_SYMBOLS=4,NUMBER_OF_SYMBOLS_LOG2=2,ONLY_FULL_ACCESS_ENABLE=0,PACKET_ENABLE=1,PROGRAMMABLE_BURST_ENABLE=0,STRIDE_ENABLE=0,STRIDE_WIDTH=1,SYMBOL_WIDTH=8,TRANSFER_TYPE=Aligned Accesses,UNALIGNED_ACCESSES_ENABLE=0,USE_FIX_ADDRESS_WIDTH=0"
|
|
instancePathKey="q_sys:.:msgdma_tx:.:read_mstr_internal"
|
|
kind="dma_read_master"
|
|
version="19.1"
|
|
name="read_master">
|
|
<parameter name="FIX_ADDRESS_WIDTH" value="32" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_master.v"
|
|
type="VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/MM_to_ST_Adapter.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/read_burst_control.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_msgdma/read_master/read_master_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_msgdma_tx" as="read_mstr_internal" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 219 starting:dma_read_master "submodules/read_master"</message>
|
|
<message level="Info" culprit="read_mstr_internal"><![CDATA["<b>msgdma_tx</b>" instantiated <b>dma_read_master</b> "<b>read_mstr_internal</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_master_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=2,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=64,AV_READLATENCY=0,AV_READ_WAIT=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_SETUP_WAIT=0,AV_SYMBOLS_PER_WORD=2,AV_WRITE_WAIT=0,SYNC_RESET=0,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=10,UAV_BURSTCOUNT_W=2,UAV_CONSTANT_BURST_BEHAVIOR=0,USE_ADDRESS=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=0,USE_CLKEN=0,USE_DEBUGACCESS=0,USE_LOCK=0,USE_READ=1,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_WAITREQUEST=1,USE_WRITE=0,USE_WRITEDATA=0,USE_WRITERESPONSE=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_0:.:sensor_interface_calibration_ram_interface_translator"
|
|
kind="altera_merlin_master_translator"
|
|
version="19.1"
|
|
name="altera_merlin_master_translator">
|
|
<parameter name="SYNC_RESET" value="0" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_0"
|
|
as="sensor_interface_calibration_ram_interface_translator" />
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="cpu_data_master_translator,cpu_instruction_master_translator,msgdma_tx_mm_read_translator,msgdma_rx_mm_write_translator,msgdma_tx_descriptor_read_master_translator,msgdma_rx_descriptor_read_master_translator,msgdma_tx_descriptor_write_master_translator,msgdma_rx_descriptor_write_master_translator" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"</message>
|
|
<message
|
|
level="Info"
|
|
culprit="sensor_interface_calibration_ram_interface_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>sensor_interface_calibration_ram_interface_translator</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_slave_translator:19.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=9,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=2,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=2,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=10,UAV_BURSTCOUNT_W=2,UAV_BYTEENABLE_W=2,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=16,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_0:.:calibration_ram_s2_translator"
|
|
kind="altera_merlin_slave_translator"
|
|
version="19.1"
|
|
name="altera_merlin_slave_translator">
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_0"
|
|
as="calibration_ram_s2_translator" />
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="ddr3_ram_avl_translator,ext_flash_avl_csr_translator,ext_flash_avl_mem_translator,eth_tse_control_port_translator,sysid_control_slave_translator,msgdma_tx_csr_translator,msgdma_rx_csr_translator,onchip_flash_csr_translator,udp_generator_csr_translator,sensor_interface_csr_translator,onchip_flash_data_translator,cpu_debug_mem_slave_translator,msgdma_tx_prefetcher_csr_translator,msgdma_rx_prefetcher_csr_translator,descriptor_memory_s1_translator,sys_clk_timer_s1_translator,output_pio_s1_translator,button_pio_s1_translator,debug_uart_s1_translator,frame_timer_s1_translator,calibration_ram_s1_translator" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
|
|
<message level="Info" culprit="calibration_ram_s2_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>calibration_ram_s2_translator</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_master_agent:19.1:ADDR_MAP=<?xml version="1.0" encoding="UTF-8"?>
|
|
<address_map>
|
|
<slave
|
|
id="3"
|
|
name="ddr3_ram_avl_translator.avalon_universal_slave_0"
|
|
start="0x0000000008000000"
|
|
end="0x00000000010000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="7"
|
|
name="ext_flash_avl_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d20"
|
|
end="0x00000000018403d40"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="8"
|
|
name="ext_flash_avl_mem_translator.avalon_universal_slave_0"
|
|
start="0x0000000014000000"
|
|
end="0x00000000018000000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="6"
|
|
name="eth_tse_control_port_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403000"
|
|
end="0x00000000018403400"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="19"
|
|
name="sysid_control_slave_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d68"
|
|
end="0x00000000018403d70"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="12"
|
|
name="msgdma_tx_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d00"
|
|
end="0x00000000018403d20"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="10"
|
|
name="msgdma_rx_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403ce0"
|
|
end="0x00000000018403d00"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="14"
|
|
name="onchip_flash_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d60"
|
|
end="0x00000000018403d68"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="20"
|
|
name="udp_generator_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403cc0"
|
|
end="0x00000000018403ce0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="17"
|
|
name="sensor_interface_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d50"
|
|
end="0x00000000018403d60"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="15"
|
|
name="onchip_flash_data_translator.avalon_universal_slave_0"
|
|
start="0x0000000018200000"
|
|
end="0x00000000018400000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="2"
|
|
name="cpu_debug_mem_slave_translator.avalon_universal_slave_0"
|
|
start="0x0000000018402800"
|
|
end="0x00000000018403000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="13"
|
|
name="msgdma_tx_prefetcher_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403ca0"
|
|
end="0x00000000018403cc0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="11"
|
|
name="msgdma_rx_prefetcher_csr_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c80"
|
|
end="0x00000000018403ca0"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="5"
|
|
name="descriptor_memory_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018400000"
|
|
end="0x00000000018402000"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="18"
|
|
name="sys_clk_timer_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c60"
|
|
end="0x00000000018403c80"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="16"
|
|
name="output_pio_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c40"
|
|
end="0x00000000018403c60"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="0"
|
|
name="button_pio_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403d40"
|
|
end="0x00000000018403d50"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="4"
|
|
name="debug_uart_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c20"
|
|
end="0x00000000018403c40"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="9"
|
|
name="frame_timer_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403c00"
|
|
end="0x00000000018403c20"
|
|
responds="1"
|
|
user_default="0" />
|
|
<slave
|
|
id="1"
|
|
name="calibration_ram_s1_translator.avalon_universal_slave_0"
|
|
start="0x0000000018403400"
|
|
end="0x00000000018403800"
|
|
responds="1"
|
|
user_default="0" />
|
|
</address_map>
|
|
,AV_BURSTBOUNDARIES=1,AV_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,BURSTWRAP_VALUE=511,CACHE_VALUE=0,ID=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=94,PKT_ADDR_SIDEBAND_L=94,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_CACHE_H=115,PKT_CACHE_L=112,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=95,PKT_DATA_SIDEBAND_L=95,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_QOS_H=97,PKT_QOS_L=97,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_EXCLUSIVE=70,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURE_ACCESS_BIT=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_RSP=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:cpu_data_master_agent"
|
|
kind="altera_merlin_master_agent"
|
|
version="19.1"
|
|
name="altera_merlin_master_agent">
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="cpu_data_master_agent,cpu_instruction_master_agent,msgdma_tx_mm_read_agent,msgdma_rx_mm_write_agent,msgdma_tx_descriptor_read_master_agent,msgdma_rx_descriptor_read_master_agent,msgdma_tx_descriptor_write_master_agent,msgdma_rx_descriptor_write_master_agent" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 187 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"</message>
|
|
<message level="Info" culprit="cpu_data_master_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_agent</b> "<b>cpu_data_master_agent</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_slave_agent:19.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=5,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=3,MAX_BURSTWRAP=511,MAX_BYTE_CNT=16,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_ORI_BURST_SIZE_H=120,PKT_ORI_BURST_SIZE_L=118,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_RESPONSE_STATUS_H=117,PKT_RESPONSE_STATUS_L=116,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_LOCK=69,PKT_TRANS_POSTED=66,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPRESS_0_BYTEEN_CMD=0,USE_READRESPONSE=0,USE_WRITERESPONSE=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:ddr3_ram_avl_agent"
|
|
kind="altera_merlin_slave_agent"
|
|
version="19.1"
|
|
name="altera_merlin_slave_agent">
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="ddr3_ram_avl_agent,ext_flash_avl_csr_agent,ext_flash_avl_mem_agent,eth_tse_control_port_agent,sysid_control_slave_agent,msgdma_tx_csr_agent,msgdma_rx_csr_agent,onchip_flash_csr_agent,udp_generator_csr_agent,sensor_interface_csr_agent,onchip_flash_data_agent,cpu_debug_mem_slave_agent,msgdma_tx_prefetcher_csr_agent,msgdma_rx_prefetcher_csr_agent,descriptor_memory_s1_agent,sys_clk_timer_s1_agent,output_pio_s1_agent,button_pio_s1_agent,debug_uart_s1_agent,frame_timer_s1_agent,calibration_ram_s1_agent" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 179 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
|
|
<message level="Info" culprit="ddr3_ram_avl_agent"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>ddr3_ram_avl_agent</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv</b>]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_sc_fifo:19.1:BITS_PER_SYMBOL=122,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=33,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:ddr3_ram_avl_agent_rsp_fifo"
|
|
kind="altera_avalon_sc_fifo"
|
|
version="19.1"
|
|
name="altera_avalon_sc_fifo">
|
|
<parameter name="EXPLICIT_MAXCHANNEL" value="0" />
|
|
<parameter name="ENABLE_EXPLICIT_MAXCHANNEL" value="false" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="ddr3_ram_avl_agent_rsp_fifo,ddr3_ram_avl_agent_rdata_fifo,ext_flash_avl_csr_agent_rsp_fifo,ext_flash_avl_csr_agent_rdata_fifo,ext_flash_avl_mem_agent_rsp_fifo,ext_flash_avl_mem_agent_rdata_fifo,eth_tse_control_port_agent_rsp_fifo,sysid_control_slave_agent_rsp_fifo,msgdma_tx_csr_agent_rsp_fifo,msgdma_rx_csr_agent_rsp_fifo,onchip_flash_csr_agent_rsp_fifo,udp_generator_csr_agent_rsp_fifo,sensor_interface_csr_agent_rsp_fifo,onchip_flash_data_agent_rsp_fifo,cpu_debug_mem_slave_agent_rsp_fifo,msgdma_tx_prefetcher_csr_agent_rsp_fifo,msgdma_rx_prefetcher_csr_agent_rsp_fifo,descriptor_memory_s1_agent_rsp_fifo,sys_clk_timer_s1_agent_rsp_fifo,output_pio_s1_agent_rsp_fifo,button_pio_s1_agent_rsp_fifo,debug_uart_s1_agent_rsp_fifo,frame_timer_s1_agent_rsp_fifo,calibration_ram_s1_agent_rsp_fifo" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 178 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
|
|
<message level="Info" culprit="ddr3_ram_avl_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>ddr3_ram_avl_agent_rsp_fifo</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=000000000000000000001,000000000000000000100,000000000010000000000,000000100000000000000,000000000100000000000,000000000000000001000,100000000000000000000,010000000000000000000,001000000000000000000,000010000000000000000,000001000000000000000,000000010000000000000,000000001000000000000,000000000000100000000,000000000000001000000,000000000000000100000,000000000000000000010,000100000000000000000,000000000001000000000,000000000000010000000,000000000000000010000,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,8,15,5,2,6,1,9,4,16,18,11,13,20,10,12,7,0,17,14,19,END_ADDRESS=0x10000000,0x18000000,0x18400000,0x18402000,0x18403000,0x18403400,0x18403800,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68,0x18403d70,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,SLAVES_INFO=3:000000000000000000001:0x8000000:0x10000000:both:1:0:0:1,8:000000000000000000100:0x14000000:0x18000000:both:1:0:0:1,15:000000000010000000000:0x18200000:0x18400000:both:1:0:0:1,5:000000100000000000000:0x18400000:0x18402000:both:1:0:0:1,2:000000000100000000000:0x18402800:0x18403000:both:1:0:0:1,6:000000000000000001000:0x18403000:0x18403400:both:1:0:0:1,1:100000000000000000000:0x18403400:0x18403800:both:1:0:0:1,9:010000000000000000000:0x18403c00:0x18403c20:both:1:0:0:1,4:001000000000000000000:0x18403c20:0x18403c40:both:1:0:0:1,16:000010000000000000000:0x18403c40:0x18403c60:both:1:0:0:1,18:000001000000000000000:0x18403c60:0x18403c80:both:1:0:0:1,11:000000010000000000000:0x18403c80:0x18403ca0:both:1:0:0:1,13:000000001000000000000:0x18403ca0:0x18403cc0:both:1:0:0:1,20:000000000000100000000:0x18403cc0:0x18403ce0:both:1:0:0:1,10:000000000000001000000:0x18403ce0:0x18403d00:both:1:0:0:1,12:000000000000000100000:0x18403d00:0x18403d20:both:1:0:0:1,7:000000000000000000010:0x18403d20:0x18403d40:both:1:0:0:1,0:000100000000000000000:0x18403d40:0x18403d50:read:1:0:0:1,17:000000000001000000000:0x18403d50:0x18403d60:both:1:0:0:1,14:000000000000010000000:0x18403d60:0x18403d68:both:1:0:0:1,19:000000000000000010000:0x18403d68:0x18403d70:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,0x14000000,0x18200000,0x18400000,0x18402800,0x18403000,0x18403400,0x18403c00,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,read,both,both,read"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:router"
|
|
kind="altera_merlin_router"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_router">
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
|
|
<parameter name="PKT_TRANS_READ" value="68" />
|
|
<parameter
|
|
name="START_ADDRESS"
|
|
value="0x8000000,0x14000000,0x18200000,0x18400000,0x18402800,0x18403000,0x18403400,0x18403c00,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68" />
|
|
<parameter name="DEFAULT_CHANNEL" value="0" />
|
|
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
|
|
<parameter
|
|
name="SLAVES_INFO"
|
|
value="3:000000000000000000001:0x8000000:0x10000000:both:1:0:0:1,8:000000000000000000100:0x14000000:0x18000000:both:1:0:0:1,15:000000000010000000000:0x18200000:0x18400000:both:1:0:0:1,5:000000100000000000000:0x18400000:0x18402000:both:1:0:0:1,2:000000000100000000000:0x18402800:0x18403000:both:1:0:0:1,6:000000000000000001000:0x18403000:0x18403400:both:1:0:0:1,1:100000000000000000000:0x18403400:0x18403800:both:1:0:0:1,9:010000000000000000000:0x18403c00:0x18403c20:both:1:0:0:1,4:001000000000000000000:0x18403c20:0x18403c40:both:1:0:0:1,16:000010000000000000000:0x18403c40:0x18403c60:both:1:0:0:1,18:000001000000000000000:0x18403c60:0x18403c80:both:1:0:0:1,11:000000010000000000000:0x18403c80:0x18403ca0:both:1:0:0:1,13:000000001000000000000:0x18403ca0:0x18403cc0:both:1:0:0:1,20:000000000000100000000:0x18403cc0:0x18403ce0:both:1:0:0:1,10:000000000000001000000:0x18403ce0:0x18403d00:both:1:0:0:1,12:000000000000000100000:0x18403d00:0x18403d20:both:1:0:0:1,7:000000000000000000010:0x18403d20:0x18403d40:both:1:0:0:1,0:000100000000000000000:0x18403d40:0x18403d50:read:1:0:0:1,17:000000000001000000000:0x18403d50:0x18403d60:both:1:0:0:1,14:000000000000010000000:0x18403d60:0x18403d68:both:1:0:0:1,19:000000000000000010000:0x18403d68:0x18403d70:read:1:0:0:1" />
|
|
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
|
|
<parameter name="PKT_ADDR_H" value="64" />
|
|
<parameter name="PKT_DEST_ID_H" value="107" />
|
|
<parameter name="PKT_ADDR_L" value="36" />
|
|
<parameter name="PKT_DEST_ID_L" value="103" />
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter
|
|
name="CHANNEL_ID"
|
|
value="000000000000000000001,000000000000000000100,000000000010000000000,000000100000000000000,000000000100000000000,000000000000000001000,100000000000000000000,010000000000000000000,001000000000000000000,000010000000000000000,000001000000000000000,000000010000000000000,000000001000000000000,000000000000100000000,000000000000001000000,000000000000000100000,000000000000000000010,000100000000000000000,000000000001000000000,000000000000010000000,000000000000000010000" />
|
|
<parameter
|
|
name="TYPE_OF_TRANSACTION"
|
|
value="both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,both,read,both,both,read" />
|
|
<parameter
|
|
name="SECURED_RANGE_PAIRS"
|
|
value="0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" />
|
|
<parameter name="SPAN_OFFSET" value="" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter
|
|
name="SECURED_RANGE_LIST"
|
|
value="0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" />
|
|
<parameter name="DECODER_TYPE" value="0" />
|
|
<parameter name="PKT_PROTECTION_H" value="111" />
|
|
<parameter
|
|
name="END_ADDRESS"
|
|
value="0x10000000,0x18000000,0x18400000,0x18402000,0x18403000,0x18403400,0x18403800,0x18403c20,0x18403c40,0x18403c60,0x18403c80,0x18403ca0,0x18403cc0,0x18403ce0,0x18403d00,0x18403d20,0x18403d40,0x18403d50,0x18403d60,0x18403d68,0x18403d70" />
|
|
<parameter name="PKT_PROTECTION_L" value="109" />
|
|
<parameter name="PKT_TRANS_WRITE" value="67" />
|
|
<parameter name="DEFAULT_DESTID" value="3" />
|
|
<parameter
|
|
name="DESTINATION_ID"
|
|
value="3,8,15,5,2,6,1,9,4,16,18,11,13,20,10,12,7,0,17,14,19" />
|
|
<parameter
|
|
name="NON_SECURED_TAG"
|
|
value="1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="router" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 134 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router"</message>
|
|
<message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=0001,0010,0100,1000,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,8,15,2,END_ADDRESS=0x10000000,0x18000000,0x18400000,0x18403000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,SLAVES_INFO=3:0001:0x8000000:0x10000000:both:1:0:0:1,8:0010:0x14000000:0x18000000:both:1:0:0:1,15:0100:0x18200000:0x18400000:both:1:0:0:1,2:1000:0x18402800:0x18403000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,0x14000000,0x18200000,0x18402800,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,both,both,both"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:router_001"
|
|
kind="altera_merlin_router"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_router_001">
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
|
|
<parameter name="PKT_TRANS_READ" value="68" />
|
|
<parameter
|
|
name="START_ADDRESS"
|
|
value="0x8000000,0x14000000,0x18200000,0x18402800" />
|
|
<parameter name="DEFAULT_CHANNEL" value="0" />
|
|
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
|
|
<parameter
|
|
name="SLAVES_INFO"
|
|
value="3:0001:0x8000000:0x10000000:both:1:0:0:1,8:0010:0x14000000:0x18000000:both:1:0:0:1,15:0100:0x18200000:0x18400000:both:1:0:0:1,2:1000:0x18402800:0x18403000:both:1:0:0:1" />
|
|
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
|
|
<parameter name="PKT_ADDR_H" value="64" />
|
|
<parameter name="PKT_DEST_ID_H" value="107" />
|
|
<parameter name="PKT_ADDR_L" value="36" />
|
|
<parameter name="PKT_DEST_ID_L" value="103" />
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="CHANNEL_ID" value="0001,0010,0100,1000" />
|
|
<parameter name="TYPE_OF_TRANSACTION" value="both,both,both,both" />
|
|
<parameter name="SECURED_RANGE_PAIRS" value="0,0,0,0" />
|
|
<parameter name="SPAN_OFFSET" value="" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="SECURED_RANGE_LIST" value="0,0,0,0" />
|
|
<parameter name="DECODER_TYPE" value="0" />
|
|
<parameter name="PKT_PROTECTION_H" value="111" />
|
|
<parameter
|
|
name="END_ADDRESS"
|
|
value="0x10000000,0x18000000,0x18400000,0x18403000" />
|
|
<parameter name="PKT_PROTECTION_L" value="109" />
|
|
<parameter name="PKT_TRANS_WRITE" value="67" />
|
|
<parameter name="DEFAULT_DESTID" value="3" />
|
|
<parameter name="DESTINATION_ID" value="3,8,15,2" />
|
|
<parameter name="NON_SECURED_TAG" value="1,1,1,1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_001.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="router_001" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 133 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_001"</message>
|
|
<message level="Info" culprit="router_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_001</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=3,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=3,END_ADDRESS=0x10000000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=3:1:0x8000000:0x10000000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x8000000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:router_002"
|
|
kind="altera_merlin_router"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_router_002">
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
|
|
<parameter name="PKT_TRANS_READ" value="68" />
|
|
<parameter name="START_ADDRESS" value="0x8000000" />
|
|
<parameter name="DEFAULT_CHANNEL" value="0" />
|
|
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
|
|
<parameter name="SLAVES_INFO" value="3:1:0x8000000:0x10000000:both:1:0:0:1" />
|
|
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
|
|
<parameter name="PKT_ADDR_H" value="64" />
|
|
<parameter name="PKT_DEST_ID_H" value="107" />
|
|
<parameter name="PKT_ADDR_L" value="36" />
|
|
<parameter name="PKT_DEST_ID_L" value="103" />
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="CHANNEL_ID" value="1" />
|
|
<parameter name="TYPE_OF_TRANSACTION" value="both" />
|
|
<parameter name="SECURED_RANGE_PAIRS" value="0" />
|
|
<parameter name="SPAN_OFFSET" value="" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="SECURED_RANGE_LIST" value="0" />
|
|
<parameter name="DECODER_TYPE" value="0" />
|
|
<parameter name="PKT_PROTECTION_H" value="111" />
|
|
<parameter name="END_ADDRESS" value="0x10000000" />
|
|
<parameter name="PKT_PROTECTION_L" value="109" />
|
|
<parameter name="PKT_TRANS_WRITE" value="67" />
|
|
<parameter name="DEFAULT_DESTID" value="3" />
|
|
<parameter name="DESTINATION_ID" value="3" />
|
|
<parameter name="NON_SECURED_TAG" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_002.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="router_002,router_003" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 132 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002"</message>
|
|
<message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=0,DEFAULT_CHANNEL=0,DEFAULT_DESTID=5,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=5,END_ADDRESS=0x18402000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=5:1:0x18400000:0x18402000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x18400000,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:router_004"
|
|
kind="altera_merlin_router"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_router_004">
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
|
|
<parameter name="PKT_TRANS_READ" value="68" />
|
|
<parameter name="START_ADDRESS" value="0x18400000" />
|
|
<parameter name="DEFAULT_CHANNEL" value="0" />
|
|
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
|
|
<parameter name="SLAVES_INFO" value="5:1:0x18400000:0x18402000:both:1:0:0:1" />
|
|
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
|
|
<parameter name="PKT_ADDR_H" value="64" />
|
|
<parameter name="PKT_DEST_ID_H" value="107" />
|
|
<parameter name="PKT_ADDR_L" value="36" />
|
|
<parameter name="PKT_DEST_ID_L" value="103" />
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="CHANNEL_ID" value="1" />
|
|
<parameter name="TYPE_OF_TRANSACTION" value="both" />
|
|
<parameter name="SECURED_RANGE_PAIRS" value="0" />
|
|
<parameter name="SPAN_OFFSET" value="" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="SECURED_RANGE_LIST" value="0" />
|
|
<parameter name="DECODER_TYPE" value="0" />
|
|
<parameter name="PKT_PROTECTION_H" value="111" />
|
|
<parameter name="END_ADDRESS" value="0x18402000" />
|
|
<parameter name="PKT_PROTECTION_L" value="109" />
|
|
<parameter name="PKT_TRANS_WRITE" value="67" />
|
|
<parameter name="DEFAULT_DESTID" value="5" />
|
|
<parameter name="DESTINATION_ID" value="5" />
|
|
<parameter name="NON_SECURED_TAG" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_004.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="router_004,router_005,router_006,router_007" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 130 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"</message>
|
|
<message level="Info" culprit="router_004"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_004</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=0001,0010,0100,1000,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,7,4,END_ADDRESS=0x0,0x0,0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,SLAVES_INFO=0:0001:0x0:0x0:both:1:0:0:1,1:0010:0x0:0x0:read:1:0:0:1,7:0100:0x0:0x0:read:1:0:0:1,4:1000:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read,read,write"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:router_008"
|
|
kind="altera_merlin_router"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_router_008">
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
|
|
<parameter name="PKT_TRANS_READ" value="68" />
|
|
<parameter name="START_ADDRESS" value="0x0,0x0,0x0,0x0" />
|
|
<parameter name="DEFAULT_CHANNEL" value="0" />
|
|
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
|
|
<parameter
|
|
name="SLAVES_INFO"
|
|
value="0:0001:0x0:0x0:both:1:0:0:1,1:0010:0x0:0x0:read:1:0:0:1,7:0100:0x0:0x0:read:1:0:0:1,4:1000:0x0:0x0:write:1:0:0:1" />
|
|
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
|
|
<parameter name="PKT_ADDR_H" value="64" />
|
|
<parameter name="PKT_DEST_ID_H" value="107" />
|
|
<parameter name="PKT_ADDR_L" value="36" />
|
|
<parameter name="PKT_DEST_ID_L" value="103" />
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="CHANNEL_ID" value="0001,0010,0100,1000" />
|
|
<parameter name="TYPE_OF_TRANSACTION" value="both,read,read,write" />
|
|
<parameter name="SECURED_RANGE_PAIRS" value="0,0,0,0" />
|
|
<parameter name="SPAN_OFFSET" value="" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="SECURED_RANGE_LIST" value="0,0,0,0" />
|
|
<parameter name="DECODER_TYPE" value="1" />
|
|
<parameter name="PKT_PROTECTION_H" value="111" />
|
|
<parameter name="END_ADDRESS" value="0x0,0x0,0x0,0x0" />
|
|
<parameter name="PKT_PROTECTION_L" value="109" />
|
|
<parameter name="PKT_TRANS_WRITE" value="67" />
|
|
<parameter name="DEFAULT_DESTID" value="0" />
|
|
<parameter name="DESTINATION_ID" value="0,1,7,4" />
|
|
<parameter name="NON_SECURED_TAG" value="1,1,1,1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_008.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="router_008" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 126 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_008"</message>
|
|
<message level="Info" culprit="router_008"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_008</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:router_009"
|
|
kind="altera_merlin_router"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_router_009">
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
|
|
<parameter name="PKT_TRANS_READ" value="68" />
|
|
<parameter name="START_ADDRESS" value="0x0" />
|
|
<parameter name="DEFAULT_CHANNEL" value="0" />
|
|
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
|
|
<parameter name="SLAVES_INFO" value="0:1:0x0:0x0:both:1:0:0:1" />
|
|
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
|
|
<parameter name="PKT_ADDR_H" value="64" />
|
|
<parameter name="PKT_DEST_ID_H" value="107" />
|
|
<parameter name="PKT_ADDR_L" value="36" />
|
|
<parameter name="PKT_DEST_ID_L" value="103" />
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="CHANNEL_ID" value="1" />
|
|
<parameter name="TYPE_OF_TRANSACTION" value="both" />
|
|
<parameter name="SECURED_RANGE_PAIRS" value="0" />
|
|
<parameter name="SPAN_OFFSET" value="" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="SECURED_RANGE_LIST" value="0" />
|
|
<parameter name="DECODER_TYPE" value="1" />
|
|
<parameter name="PKT_PROTECTION_H" value="111" />
|
|
<parameter name="END_ADDRESS" value="0x0" />
|
|
<parameter name="PKT_PROTECTION_L" value="109" />
|
|
<parameter name="PKT_TRANS_WRITE" value="67" />
|
|
<parameter name="DEFAULT_DESTID" value="0" />
|
|
<parameter name="DESTINATION_ID" value="0" />
|
|
<parameter name="NON_SECURED_TAG" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_009.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="router_009,router_011,router_012,router_013,router_014,router_015,router_016,router_017,router_020,router_021,router_023,router_024,router_025,router_026,router_027" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 125 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"</message>
|
|
<message level="Info" culprit="router_009"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_009</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,1,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:router_010"
|
|
kind="altera_merlin_router"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_router_010">
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
|
|
<parameter name="PKT_TRANS_READ" value="68" />
|
|
<parameter name="START_ADDRESS" value="0x0,0x0" />
|
|
<parameter name="DEFAULT_CHANNEL" value="0" />
|
|
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
|
|
<parameter
|
|
name="SLAVES_INFO"
|
|
value="0:01:0x0:0x0:both:1:0:0:1,1:10:0x0:0x0:read:1:0:0:1" />
|
|
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
|
|
<parameter name="PKT_ADDR_H" value="64" />
|
|
<parameter name="PKT_DEST_ID_H" value="107" />
|
|
<parameter name="PKT_ADDR_L" value="36" />
|
|
<parameter name="PKT_DEST_ID_L" value="103" />
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="CHANNEL_ID" value="01,10" />
|
|
<parameter name="TYPE_OF_TRANSACTION" value="both,read" />
|
|
<parameter name="SECURED_RANGE_PAIRS" value="0,0" />
|
|
<parameter name="SPAN_OFFSET" value="" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="SECURED_RANGE_LIST" value="0,0" />
|
|
<parameter name="DECODER_TYPE" value="1" />
|
|
<parameter name="PKT_PROTECTION_H" value="111" />
|
|
<parameter name="END_ADDRESS" value="0x0,0x0" />
|
|
<parameter name="PKT_PROTECTION_L" value="109" />
|
|
<parameter name="PKT_TRANS_WRITE" value="67" />
|
|
<parameter name="DEFAULT_DESTID" value="0" />
|
|
<parameter name="DESTINATION_ID" value="0,1" />
|
|
<parameter name="NON_SECURED_TAG" value="1,1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_010.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="router_010,router_018,router_019" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 124 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"</message>
|
|
<message level="Info" culprit="router_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_010</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=00001,00010,00100,01000,10000,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,5,2,6,3,END_ADDRESS=0x0,0x0,0x0,0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,1,1,1,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_PROTECTION_H=111,PKT_PROTECTION_L=109,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,SECURED_RANGE_LIST=0,0,0,0,0,SECURED_RANGE_PAIRS=0,0,0,0,0,SLAVES_INFO=0:00001:0x0:0x0:both:1:0:0:1,5:00010:0x0:0x0:read:1:0:0:1,2:00100:0x0:0x0:read:1:0:0:1,6:01000:0x0:0x0:write:1:0:0:1,3:10000:0x0:0x0:write:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,0x0,0x0,0x0,ST_CHANNEL_W=21,ST_DATA_W=121,TYPE_OF_TRANSACTION=both,read,read,write,write"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:router_022"
|
|
kind="altera_merlin_router"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_router_022">
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
|
|
<parameter name="PKT_TRANS_READ" value="68" />
|
|
<parameter name="START_ADDRESS" value="0x0,0x0,0x0,0x0,0x0" />
|
|
<parameter name="DEFAULT_CHANNEL" value="0" />
|
|
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
|
|
<parameter
|
|
name="SLAVES_INFO"
|
|
value="0:00001:0x0:0x0:both:1:0:0:1,5:00010:0x0:0x0:read:1:0:0:1,2:00100:0x0:0x0:read:1:0:0:1,6:01000:0x0:0x0:write:1:0:0:1,3:10000:0x0:0x0:write:1:0:0:1" />
|
|
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
|
|
<parameter name="PKT_ADDR_H" value="64" />
|
|
<parameter name="PKT_DEST_ID_H" value="107" />
|
|
<parameter name="PKT_ADDR_L" value="36" />
|
|
<parameter name="PKT_DEST_ID_L" value="103" />
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="CHANNEL_ID" value="00001,00010,00100,01000,10000" />
|
|
<parameter name="TYPE_OF_TRANSACTION" value="both,read,read,write,write" />
|
|
<parameter name="SECURED_RANGE_PAIRS" value="0,0,0,0,0" />
|
|
<parameter name="SPAN_OFFSET" value="" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="SECURED_RANGE_LIST" value="0,0,0,0,0" />
|
|
<parameter name="DECODER_TYPE" value="1" />
|
|
<parameter name="PKT_PROTECTION_H" value="111" />
|
|
<parameter name="END_ADDRESS" value="0x0,0x0,0x0,0x0,0x0" />
|
|
<parameter name="PKT_PROTECTION_L" value="109" />
|
|
<parameter name="PKT_TRANS_WRITE" value="67" />
|
|
<parameter name="DEFAULT_DESTID" value="0" />
|
|
<parameter name="DESTINATION_ID" value="0,5,2,6,3" />
|
|
<parameter name="NON_SECURED_TAG" value="1,1,1,1,1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_022.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="router_022" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 112 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_022"</message>
|
|
<message level="Info" culprit="router_022"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_022</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_router:19.1:CHANNEL_ID=1,DECODER_TYPE=1,DEFAULT_CHANNEL=0,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=0,END_ADDRESS=0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),NON_SECURED_TAG=1,PKT_ADDR_H=46,PKT_ADDR_L=18,PKT_DEST_ID_H=89,PKT_DEST_ID_L=85,PKT_PROTECTION_H=93,PKT_PROTECTION_L=91,PKT_TRANS_READ=50,PKT_TRANS_WRITE=49,SECURED_RANGE_LIST=0,SECURED_RANGE_PAIRS=0,SLAVES_INFO=0:1:0x0:0x0:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,ST_CHANNEL_W=21,ST_DATA_W=103,TYPE_OF_TRANSACTION=both"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:router_028"
|
|
kind="altera_merlin_router"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_router_028">
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="DEFAULT_WR_CHANNEL" value="-1" />
|
|
<parameter name="PKT_TRANS_READ" value="50" />
|
|
<parameter name="START_ADDRESS" value="0x0" />
|
|
<parameter name="DEFAULT_CHANNEL" value="0" />
|
|
<parameter name="MEMORY_ALIASING_DECODE" value="0" />
|
|
<parameter name="SLAVES_INFO" value="0:1:0x0:0x0:both:1:0:0:1" />
|
|
<parameter name="DEFAULT_RD_CHANNEL" value="-1" />
|
|
<parameter name="PKT_ADDR_H" value="46" />
|
|
<parameter name="PKT_DEST_ID_H" value="89" />
|
|
<parameter name="PKT_ADDR_L" value="18" />
|
|
<parameter name="PKT_DEST_ID_L" value="85" />
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)" />
|
|
<parameter name="CHANNEL_ID" value="1" />
|
|
<parameter name="TYPE_OF_TRANSACTION" value="both" />
|
|
<parameter name="SECURED_RANGE_PAIRS" value="0" />
|
|
<parameter name="SPAN_OFFSET" value="" />
|
|
<parameter name="ST_DATA_W" value="103" />
|
|
<parameter name="SECURED_RANGE_LIST" value="0" />
|
|
<parameter name="DECODER_TYPE" value="1" />
|
|
<parameter name="PKT_PROTECTION_H" value="93" />
|
|
<parameter name="END_ADDRESS" value="0x0" />
|
|
<parameter name="PKT_PROTECTION_L" value="91" />
|
|
<parameter name="PKT_TRANS_WRITE" value="49" />
|
|
<parameter name="DEFAULT_DESTID" value="0" />
|
|
<parameter name="DESTINATION_ID" value="0" />
|
|
<parameter name="NON_SECURED_TAG" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_router_028.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="router_028" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 106 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_028"</message>
|
|
<message level="Info" culprit="router_028"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_router</b> "<b>router_028</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_traffic_limiter:19.1:ENFORCE_ORDER=1,MAX_BURST_LENGTH=1,MAX_OUTSTANDING_RESPONSES=36,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),PIPELINED=0,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_DEST_ID_H=107,PKT_DEST_ID_L=103,PKT_SRC_ID_H=102,PKT_SRC_ID_L=98,PKT_THREAD_ID_H=108,PKT_THREAD_ID_L=108,PKT_TRANS_POSTED=66,PKT_TRANS_WRITE=67,PREVENT_HAZARDS=0,REORDER=0,ST_CHANNEL_W=21,ST_DATA_W=121,SUPPORTS_NONPOSTED_WRITES=0,SUPPORTS_POSTED_WRITES=1,VALID_WIDTH=21"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:cpu_data_master_limiter"
|
|
kind="altera_merlin_traffic_limiter"
|
|
version="19.1"
|
|
name="altera_merlin_traffic_limiter">
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_traffic_limiter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_reorder_memory.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="cpu_data_master_limiter,cpu_instruction_master_limiter" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 105 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"</message>
|
|
<message level="Info" culprit="cpu_data_master_limiter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>cpu_data_master_limiter</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_burst_adapter:19.1:ADAPTER_VERSION=13.1,BURSTWRAP_CONST_MASK=3,BURSTWRAP_CONST_VALUE=3,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=0,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=0,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=87,OUT_BYTE_CNT_H=79,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=64,PKT_ADDR_L=36,PKT_BEGIN_BURST=96,PKT_BURSTWRAP_H=88,PKT_BURSTWRAP_L=80,PKT_BURST_SIZE_H=91,PKT_BURST_SIZE_L=89,PKT_BURST_TYPE_H=93,PKT_BURST_TYPE_L=92,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=79,PKT_BYTE_CNT_L=71,PKT_TRANS_COMPRESSED_READ=65,PKT_TRANS_READ=68,PKT_TRANS_WRITE=67,ST_CHANNEL_W=21,ST_DATA_W=121"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:ext_flash_avl_mem_burst_adapter"
|
|
kind="altera_merlin_burst_adapter"
|
|
version="19.1"
|
|
name="altera_merlin_burst_adapter">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="PKT_TRANS_COMPRESSED_READ" value="65" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_adapter_new.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_incr_burst_converter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_wrap_burst_converter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_default_burst_converter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="ext_flash_avl_mem_burst_adapter,calibration_ram_s1_burst_adapter" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 103 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
|
|
<message level="Info" culprit="ext_flash_avl_mem_burst_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>ext_flash_avl_mem_burst_adapter</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=21,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=21"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_demux"
|
|
kind="altera_merlin_demultiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_cmd_demux">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
|
|
<parameter name="VALID_WIDTH" value="21" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="NUM_OUTPUTS" value="21" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="cmd_demux" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 101 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux"</message>
|
|
<message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=4,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=21"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_demux_001"
|
|
kind="altera_merlin_demultiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_cmd_demux_001">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
|
|
<parameter name="VALID_WIDTH" value="21" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="NUM_OUTPUTS" value="4" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_001.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="cmd_demux_001" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 100 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_001"</message>
|
|
<message level="Info" culprit="cmd_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_001</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_demux_002"
|
|
kind="altera_merlin_demultiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_cmd_demux_002">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
|
|
<parameter name="VALID_WIDTH" value="1" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="NUM_OUTPUTS" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_demux_002.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="cmd_demux_002,cmd_demux_003,cmd_demux_004,cmd_demux_005,cmd_demux_006,cmd_demux_007,rsp_demux_003,rsp_demux_004,rsp_demux_005,rsp_demux_006,rsp_demux_007,rsp_demux_008,rsp_demux_009,rsp_demux_012,rsp_demux_013,rsp_demux_015,rsp_demux_016,rsp_demux_017,rsp_demux_018,rsp_demux_019,rsp_demux_020" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 99 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"</message>
|
|
<message level="Info" culprit="cmd_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux_002</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=4,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_mux"
|
|
kind="altera_merlin_multiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_cmd_mux">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="ARBITRATION_SHARES" value="1,1,1,1" />
|
|
<parameter name="NUM_INPUTS" value="4" />
|
|
<parameter name="PIPELINE_ARB" value="0" />
|
|
<parameter name="ARBITRATION_SCHEME" value="round-robin" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="USE_EXTERNAL_ARB" value="0" />
|
|
<parameter name="PKT_TRANS_LOCK" value="69" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="cmd_mux" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 93 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux"</message>
|
|
<message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_mux_001"
|
|
kind="altera_merlin_multiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_cmd_mux_001">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="ARBITRATION_SHARES" value="1" />
|
|
<parameter name="NUM_INPUTS" value="1" />
|
|
<parameter name="PIPELINE_ARB" value="0" />
|
|
<parameter name="ARBITRATION_SCHEME" value="round-robin" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="USE_EXTERNAL_ARB" value="0" />
|
|
<parameter name="PKT_TRANS_LOCK" value="69" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_001.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="cmd_mux_001,cmd_mux_003,cmd_mux_004,cmd_mux_005,cmd_mux_006,cmd_mux_007,cmd_mux_008,cmd_mux_009,cmd_mux_012,cmd_mux_013,cmd_mux_015,cmd_mux_016,cmd_mux_017,cmd_mux_018,cmd_mux_019,cmd_mux_020" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 92 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"</message>
|
|
<message level="Info" culprit="cmd_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_001</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_mux_002"
|
|
kind="altera_merlin_multiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_cmd_mux_002">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="ARBITRATION_SHARES" value="1,1" />
|
|
<parameter name="NUM_INPUTS" value="2" />
|
|
<parameter name="PIPELINE_ARB" value="0" />
|
|
<parameter name="ARBITRATION_SCHEME" value="round-robin" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="USE_EXTERNAL_ARB" value="0" />
|
|
<parameter name="PKT_TRANS_LOCK" value="69" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_002.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="cmd_mux_002,cmd_mux_010,cmd_mux_011" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 91 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"</message>
|
|
<message level="Info" culprit="cmd_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_002</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=5,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:cmd_mux_014"
|
|
kind="altera_merlin_multiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_cmd_mux_014">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="ARBITRATION_SHARES" value="1,1,1,1,1" />
|
|
<parameter name="NUM_INPUTS" value="5" />
|
|
<parameter name="PIPELINE_ARB" value="0" />
|
|
<parameter name="ARBITRATION_SCHEME" value="round-robin" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="USE_EXTERNAL_ARB" value="0" />
|
|
<parameter name="PKT_TRANS_LOCK" value="69" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_cmd_mux_014.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="cmd_mux_014" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 79 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_014"</message>
|
|
<message level="Info" culprit="cmd_mux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux_014</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=150000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=4,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_demux"
|
|
kind="altera_merlin_demultiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_rsp_demux">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="150000000" />
|
|
<parameter name="VALID_WIDTH" value="1" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="NUM_OUTPUTS" value="4" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_demux" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 72 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux"</message>
|
|
<message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=1,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_demux_001"
|
|
kind="altera_merlin_demultiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_rsp_demux_001">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
|
|
<parameter name="VALID_WIDTH" value="1" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="NUM_OUTPUTS" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_001.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_demux_001" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 71 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_001"</message>
|
|
<message level="Info" culprit="rsp_demux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_001</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_demux_002"
|
|
kind="altera_merlin_demultiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_rsp_demux_002">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
|
|
<parameter name="VALID_WIDTH" value="1" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="NUM_OUTPUTS" value="2" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_002.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_demux_002" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 70 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_002"</message>
|
|
<message level="Info" culprit="rsp_demux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_002</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_demux_010"
|
|
kind="altera_merlin_demultiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_rsp_demux_010">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
|
|
<parameter name="VALID_WIDTH" value="1" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="NUM_OUTPUTS" value="2" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_010.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="rsp_demux_010,rsp_demux_011" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 62 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010"</message>
|
|
<message level="Info" culprit="rsp_demux_010"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_010</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_demultiplexer:19.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=MAX 10,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_OUTPUTS=5,ST_CHANNEL_W=21,ST_DATA_W=121,VALID_WIDTH=1"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_demux_014"
|
|
kind="altera_merlin_demultiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_rsp_demux_014">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
|
|
<parameter name="VALID_WIDTH" value="1" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="NUM_OUTPUTS" value="5" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_demux_014.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_demux_014" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 58 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_014"</message>
|
|
<message level="Info" culprit="rsp_demux_014"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux_014</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=21,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_mux"
|
|
kind="altera_merlin_multiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_rsp_mux">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter
|
|
name="ARBITRATION_SHARES"
|
|
value="1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" />
|
|
<parameter name="NUM_INPUTS" value="21" />
|
|
<parameter name="PIPELINE_ARB" value="0" />
|
|
<parameter name="ARBITRATION_SCHEME" value="no-arb" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="USE_EXTERNAL_ARB" value="0" />
|
|
<parameter name="PKT_TRANS_LOCK" value="69" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_mux" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 51 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux"</message>
|
|
<message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,1,1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=4,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_mux_001"
|
|
kind="altera_merlin_multiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_rsp_mux_001">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="ARBITRATION_SHARES" value="1,1,1,1" />
|
|
<parameter name="NUM_INPUTS" value="4" />
|
|
<parameter name="PIPELINE_ARB" value="0" />
|
|
<parameter name="ARBITRATION_SCHEME" value="no-arb" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="USE_EXTERNAL_ARB" value="0" />
|
|
<parameter name="PKT_TRANS_LOCK" value="69" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_001.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="rsp_mux_001" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 50 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_001"</message>
|
|
<message level="Info" culprit="rsp_mux_001"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_001</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_multiplexer:19.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),NUM_INPUTS=1,PIPELINE_ARB=0,PKT_TRANS_LOCK=69,ST_CHANNEL_W=21,ST_DATA_W=121,USE_EXTERNAL_ARB=0"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:rsp_mux_002"
|
|
kind="altera_merlin_multiplexer"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_rsp_mux_002">
|
|
<parameter
|
|
name="MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter name="ST_CHANNEL_W" value="21" />
|
|
<parameter name="ARBITRATION_SHARES" value="1" />
|
|
<parameter name="NUM_INPUTS" value="1" />
|
|
<parameter name="PIPELINE_ARB" value="0" />
|
|
<parameter name="ARBITRATION_SCHEME" value="no-arb" />
|
|
<parameter name="ST_DATA_W" value="121" />
|
|
<parameter name="USE_EXTERNAL_ARB" value="0" />
|
|
<parameter name="PKT_TRANS_LOCK" value="69" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_rsp_mux_002.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="rsp_mux_002,rsp_mux_003,rsp_mux_004,rsp_mux_005,rsp_mux_006,rsp_mux_007" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 49 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"</message>
|
|
<message level="Info" culprit="rsp_mux_002"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux_002</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_merlin_width_adapter:19.1:COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=1,ENABLE_ADDRESS_ALIGNMENT=0,IN_MERLIN_PACKET_FORMAT=ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0),IN_PKT_ADDR_H=46,IN_PKT_ADDR_L=18,IN_PKT_BURSTWRAP_H=70,IN_PKT_BURSTWRAP_L=62,IN_PKT_BURST_SIZE_H=73,IN_PKT_BURST_SIZE_L=71,IN_PKT_BURST_TYPE_H=75,IN_PKT_BURST_TYPE_L=74,IN_PKT_BYTEEN_H=17,IN_PKT_BYTEEN_L=16,IN_PKT_BYTE_CNT_H=61,IN_PKT_BYTE_CNT_L=53,IN_PKT_DATA_H=15,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=102,IN_PKT_ORI_BURST_SIZE_L=100,IN_PKT_RESPONSE_STATUS_H=99,IN_PKT_RESPONSE_STATUS_L=98,IN_PKT_TRANS_COMPRESSED_READ=47,IN_PKT_TRANS_EXCLUSIVE=52,IN_PKT_TRANS_WRITE=49,IN_ST_DATA_W=103,OPTIMIZE_FOR_RSP=1,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0),OUT_PKT_ADDR_H=64,OUT_PKT_ADDR_L=36,OUT_PKT_BURST_SIZE_H=91,OUT_PKT_BURST_SIZE_L=89,OUT_PKT_BURST_TYPE_H=93,OUT_PKT_BURST_TYPE_L=92,OUT_PKT_BYTEEN_H=35,OUT_PKT_BYTEEN_L=32,OUT_PKT_BYTE_CNT_H=79,OUT_PKT_BYTE_CNT_L=71,OUT_PKT_DATA_H=31,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=120,OUT_PKT_ORI_BURST_SIZE_L=118,OUT_PKT_RESPONSE_STATUS_H=117,OUT_PKT_RESPONSE_STATUS_L=116,OUT_PKT_TRANS_COMPRESSED_READ=65,OUT_PKT_TRANS_EXCLUSIVE=70,OUT_ST_DATA_W=121,PACKING=1,RESPONSE_PATH=1,ST_CHANNEL_W=21"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:calibration_ram_s1_rsp_width_adapter"
|
|
kind="altera_merlin_width_adapter"
|
|
version="19.1"
|
|
name="altera_merlin_width_adapter">
|
|
<parameter name="OUT_PKT_ORI_BURST_SIZE_H" value="120" />
|
|
<parameter name="OUT_PKT_ORI_BURST_SIZE_L" value="118" />
|
|
<parameter name="IN_PKT_ORI_BURST_SIZE_H" value="102" />
|
|
<parameter
|
|
name="OUT_MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(120:118) response_status(117:116) cache(115:112) protection(111:109) thread_id(108) dest_id(107:103) src_id(102:98) qos(97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:80) byte_cnt(79:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
|
|
<parameter
|
|
name="IN_MERLIN_PACKET_FORMAT"
|
|
value="ori_burst_size(102:100) response_status(99:98) cache(97:94) protection(93:91) thread_id(90) dest_id(89:85) src_id(84:80) qos(79) begin_burst(78) data_sideband(77) addr_sideband(76) burst_type(75:74) burst_size(73:71) burstwrap(70:62) byte_cnt(61:53) trans_exclusive(52) trans_lock(51) trans_read(50) trans_write(49) trans_posted(48) trans_compressed_read(47) addr(46:18) byteen(17:16) data(15:0)" />
|
|
<parameter name="IN_PKT_ORI_BURST_SIZE_L" value="100" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_width_adapter.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="calibration_ram_s1_rsp_width_adapter,calibration_ram_s1_cmd_width_adapter" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 43 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
|
|
<message level="Info" culprit="calibration_ram_s1_rsp_width_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>calibration_ram_s1_rsp_width_adapter</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_st_handshake_clock_crosser:19.1:AUTO_IN_CLK_CLOCK_RATE=50000000,AUTO_OUT_CLK_CLOCK_RATE=150000000,BITS_PER_SYMBOL=121,CHANNEL_WIDTH=21,DATA_WIDTH=121,ERROR_WIDTH=1,MAX_CHANNEL=0,READY_SYNC_DEPTH=2,USE_CHANNEL=1,USE_ERROR=0,USE_OUTPUT_PIPELINE=0,USE_PACKETS=1,VALID_SYNC_DEPTH=2"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:crosser"
|
|
kind="altera_avalon_st_handshake_clock_crosser"
|
|
version="19.1"
|
|
name="altera_avalon_st_handshake_clock_crosser">
|
|
<parameter name="AUTO_OUT_CLK_CLOCK_RATE" value="150000000" />
|
|
<parameter name="USE_PACKETS" value="1" />
|
|
<parameter name="BITS_PER_SYMBOL" value="121" />
|
|
<parameter name="MAX_CHANNEL" value="0" />
|
|
<parameter name="ERROR_WIDTH" value="1" />
|
|
<parameter name="AUTO_IN_CLK_CLOCK_RATE" value="50000000" />
|
|
<parameter name="USE_ERROR" value="0" />
|
|
<parameter name="CHANNEL_WIDTH" value="21" />
|
|
<parameter name="USE_CHANNEL" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_clock_crosser.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc"
|
|
type="SDC"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser_hw.tcl" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="crosser,crosser_001,crosser_002,crosser_003,crosser_004,crosser_005,crosser_006,crosser_007,crosser_008,crosser_009,crosser_010,crosser_011,crosser_012,crosser_013" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 41 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"</message>
|
|
<message level="Info" culprit="crosser"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_handshake_clock_crosser</b> "<b>crosser</b>"]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
|
|
<message level="Info"><![CDATA[Reusing file <b>/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v</b>]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_st_adapter:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,inBitsPerSymbol=34,inChannelWidth=0,inDataWidth=34,inEmptyWidth=1,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inUseEmptyPort=0,inUsePackets=0,inUseReady=1,inUseValid=1,outChannelWidth=0,outDataWidth=34,outEmptyWidth=1,outErrorDescriptor=,outErrorWidth=1,outMaxChannel=0,outReadyLatency=0,outUseEmptyPort=0,outUseReady=1,outUseValid=1(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(error_adapter:19.1:inBitsPerSymbol=34,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1)(clock:19.1:)(clock:19.1:)(reset:19.1:)"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:avalon_st_adapter"
|
|
kind="altera_avalon_st_adapter"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_avalon_st_adapter">
|
|
<parameter name="inUseValid" value="1" />
|
|
<parameter name="inBitsPerSymbol" value="34" />
|
|
<parameter name="outUseEmptyPort" value="0" />
|
|
<parameter name="inChannelWidth" value="0" />
|
|
<parameter name="outErrorWidth" value="1" />
|
|
<parameter name="outUseValid" value="1" />
|
|
<parameter name="outMaxChannel" value="0" />
|
|
<parameter name="inErrorDescriptor" value="" />
|
|
<parameter name="inUsePackets" value="0" />
|
|
<parameter name="inErrorWidth" value="0" />
|
|
<parameter name="inEmptyWidth" value="1" />
|
|
<parameter name="inUseReady" value="1" />
|
|
<parameter name="outReadyLatency" value="0" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="outDataWidth" value="34" />
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
|
|
<parameter name="inUseEmptyPort" value="0" />
|
|
<parameter name="outChannelWidth" value="0" />
|
|
<parameter name="inMaxChannel" value="0" />
|
|
<parameter name="outUseReady" value="1" />
|
|
<parameter name="inReadyLatency" value="0" />
|
|
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
|
|
<parameter name="inDataWidth" value="34" />
|
|
<parameter name="outErrorDescriptor" value="" />
|
|
<parameter name="outEmptyWidth" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1"
|
|
as="avalon_st_adapter,avalon_st_adapter_001,avalon_st_adapter_002,avalon_st_adapter_003,avalon_st_adapter_004,avalon_st_adapter_005,avalon_st_adapter_006,avalon_st_adapter_007,avalon_st_adapter_008,avalon_st_adapter_009,avalon_st_adapter_010,avalon_st_adapter_011,avalon_st_adapter_012,avalon_st_adapter_013,avalon_st_adapter_014,avalon_st_adapter_015,avalon_st_adapter_016,avalon_st_adapter_017,avalon_st_adapter_018,avalon_st_adapter_019" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 27 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0</b>"]]></message>
|
|
<message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"</message>
|
|
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_avalon_st_adapter:19.1:AUTO_DEVICE=10M50DAF484C6GES,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=,inBitsPerSymbol=18,inChannelWidth=0,inDataWidth=18,inEmptyWidth=1,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inUseEmptyPort=0,inUsePackets=0,inUseReady=1,inUseValid=1,outChannelWidth=0,outDataWidth=18,outEmptyWidth=1,outErrorDescriptor=,outErrorWidth=1,outMaxChannel=0,outReadyLatency=0,outUseEmptyPort=0,outUseReady=1,outUseValid=1(altera_clock_bridge:19.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:19.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(error_adapter:19.1:inBitsPerSymbol=18,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1)(clock:19.1:)(clock:19.1:)(reset:19.1:)"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:avalon_st_adapter_020"
|
|
kind="altera_avalon_st_adapter"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_avalon_st_adapter_020">
|
|
<parameter name="inUseValid" value="1" />
|
|
<parameter name="inBitsPerSymbol" value="18" />
|
|
<parameter name="outUseEmptyPort" value="0" />
|
|
<parameter name="inChannelWidth" value="0" />
|
|
<parameter name="outErrorWidth" value="1" />
|
|
<parameter name="outUseValid" value="1" />
|
|
<parameter name="outMaxChannel" value="0" />
|
|
<parameter name="inErrorDescriptor" value="" />
|
|
<parameter name="inUsePackets" value="0" />
|
|
<parameter name="inErrorWidth" value="0" />
|
|
<parameter name="inEmptyWidth" value="1" />
|
|
<parameter name="inUseReady" value="1" />
|
|
<parameter name="outReadyLatency" value="0" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="outDataWidth" value="18" />
|
|
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
|
|
<parameter name="inUseEmptyPort" value="0" />
|
|
<parameter name="outChannelWidth" value="0" />
|
|
<parameter name="inMaxChannel" value="0" />
|
|
<parameter name="outUseReady" value="1" />
|
|
<parameter name="inReadyLatency" value="0" />
|
|
<parameter name="AUTO_DEVICE" value="10M50DAF484C6GES" />
|
|
<parameter name="inDataWidth" value="18" />
|
|
<parameter name="outErrorDescriptor" value="" />
|
|
<parameter name="outEmptyWidth" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020.v"
|
|
type="VERILOG" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</childGeneratedFiles>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
|
|
</childSourceFiles>
|
|
<instantiator instantiator="q_sys_mm_interconnect_1" as="avalon_st_adapter_020" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 8 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020"</message>
|
|
<message level="Progress" culprit="min"></message>
|
|
<message level="Progress" culprit="max"></message>
|
|
<message level="Progress" culprit="current"></message>
|
|
<message level="Debug">Transform: CustomInstructionTransform</message>
|
|
<message level="Debug">No custom instruction connections, skipping transform </message>
|
|
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
|
|
<message level="Debug">Transform: MMTransform</message>
|
|
<message level="Debug">Transform: InterruptMapperTransform</message>
|
|
<message level="Debug">Transform: InterruptSyncTransform</message>
|
|
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
|
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
|
<message level="Debug">Transform: ResetAdaptation</message>
|
|
<message level="Debug" culprit="avalon_st_adapter_020"><![CDATA["<b>avalon_st_adapter_020</b>" reuses <b>error_adapter</b> "<b>submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0</b>"]]></message>
|
|
<message level="Info" culprit="avalon_st_adapter_020"><![CDATA["<b>mm_interconnect_1</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_020</b>"]]></message>
|
|
<message level="Debug" culprit="q_sys">queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0"</message>
|
|
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_020</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="error_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,outErrorDescriptor=,outErrorWidth=1"
|
|
instancePathKey="q_sys:.:avalon_st_adapter:.:error_adapter_0"
|
|
kind="error_adapter"
|
|
version="19.1"
|
|
name="q_sys_avalon_st_adapter_error_adapter_0">
|
|
<parameter name="inErrorWidth" value="0" />
|
|
<parameter name="inUseReady" value="true" />
|
|
<parameter name="inBitsPerSymbol" value="8" />
|
|
<parameter name="inChannelWidth" value="0" />
|
|
<parameter name="inSymbolsPerBeat" value="4" />
|
|
<parameter name="inUseEmptyPort" value="YES" />
|
|
<parameter name="outErrorWidth" value="1" />
|
|
<parameter name="inMaxChannel" value="0" />
|
|
<parameter name="inReadyLatency" value="0" />
|
|
<parameter name="outErrorDescriptor" value="" />
|
|
<parameter name="inUseEmpty" value="false" />
|
|
<parameter name="inErrorDescriptor" value="" />
|
|
<parameter name="inUsePackets" value="true" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_error_adapter_0.sv"
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type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_avalon_st_adapter" as="error_adapter_0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 8 starting:error_adapter "submodules/q_sys_avalon_st_adapter_error_adapter_0"</message>
|
|
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
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|
parameterizationKey="timing_adapter:19.1:inBitsPerSymbol=8,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=6,inMaxChannel=0,inReadyLatency=2,inSymbolsPerBeat=4,inUseEmpty=false,inUseEmptyPort=YES,inUsePackets=true,inUseReady=true,inUseValid=true,outReadyLatency=0,outUseReady=true,outUseValid=true"
|
|
instancePathKey="q_sys:.:avalon_st_adapter_001:.:timing_adapter_0"
|
|
kind="timing_adapter"
|
|
version="19.1"
|
|
name="q_sys_avalon_st_adapter_001_timing_adapter_0">
|
|
<parameter name="inErrorWidth" value="6" />
|
|
<parameter name="inUseValid" value="true" />
|
|
<parameter name="inUseReady" value="true" />
|
|
<parameter name="inBitsPerSymbol" value="8" />
|
|
<parameter name="outReadyLatency" value="0" />
|
|
<parameter name="inChannelWidth" value="0" />
|
|
<parameter name="inSymbolsPerBeat" value="4" />
|
|
<parameter name="inUseEmptyPort" value="YES" />
|
|
<parameter name="inMaxChannel" value="0" />
|
|
<parameter name="outUseReady" value="true" />
|
|
<parameter name="outUseValid" value="true" />
|
|
<parameter name="inReadyLatency" value="2" />
|
|
<parameter name="inUseEmpty" value="false" />
|
|
<parameter name="inErrorDescriptor" value="" />
|
|
<parameter name="inUsePackets" value="true" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_avalon_st_adapter_001_timing_adapter_0_fifo.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_avalon_st_adapter_001" as="timing_adapter_0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 7 starting:timing_adapter "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0"</message>
|
|
<message level="Info" culprit="timing_adapter_0"><![CDATA["<b>avalon_st_adapter_001</b>" instantiated <b>timing_adapter</b> "<b>timing_adapter_0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_mem_if_nextgen_ddr3_controller_core:19.1:AC_PARITY=false,AC_ROM_MR0=0001000010001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0001100010000,AC_ROM_MR0_DLL_RESET_MIRR=0001010001000,AC_ROM_MR0_MIRR=0001000001001,AC_ROM_MR1=0000000000000,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000000,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0000000000000,AC_ROM_MR2_MIRR=0000000000000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=1,AFI_ADDR_WIDTH=28,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=2,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=2,AFI_DM_WIDTH=4,AFI_DQ_WIDTH=32,AFI_ODT_WIDTH=2,AFI_RATE_RATIO=2,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=2,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=2,AFI_WRITE_DQS_WIDTH=2,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=25,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=4,AVL_DATA_WIDTH=32,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=4,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=8,CFG_MEM_CLK_ENTRY_CYCLES=20,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=1,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DEVICE_DEPTH=1,DEVICE_FAMILY=MAX 10,DEVICE_FAMILY_PARAM=MAX 10,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=true,DISCRETE_FLY_BY=true,DQ_DDR=1,DUPLICATE_AC=false,DWIDTH_RATIO=4,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_CSR_PORT=false,FLY_BY=true,FORCE_DQS_TRACKING=AUTO,FORCE_SHADOW_REGS=AUTO,HARD_EMIF=false,HARD_PHY=false,HCX_COMPAT_MODE=false,HHP_HPS=false,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DEFAULT,HR_DDIO_OUT_HAS_THREE_REGS=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IS_ES_DEVICE=false,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAX10_CFG=true,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=300.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=100,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=8,MEM_DRV_STR=RZQ/6,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=14,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=1,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=1,MEM_IF_DQ_WIDTH=8,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=1,MEM_IF_ROW_ADDR_WIDTH=14,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=1,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=14,MEM_RTT_NOM=ODT Disabled,MEM_RTT_WR=Dynamic ODT off,MEM_SRT=Normal,MEM_TCL=5,MEM_TDQSCK=1,MEM_TFAW=10,MEM_TFAW_NS=30.0,MEM_TINIT_CK=150000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=11,MEM_TRAS_NS=35.0,MEM_TRC=15,MEM_TRCD=5,MEM_TRCD_NS=13.75,MEM_TREFI=2341,MEM_TREFI_US=7.8,MEM_TRFC=34,MEM_TRFC_NS=110.0,MEM_TRP=5,MEM_TRP_NS=13.75,MEM_TRRD=2,MEM_TRRD_NS=6.0,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=5,MEM_TWR_NS=15.0,MEM_TWTR=6,MEM_TYPE=DDR3,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_WTCL=5,MEM_WTCL_INT=5,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=1,MR0_DLL=1,MR0_PD=0,MR0_WR=1,MR1_AL=0,MR1_DLL=0,MR1_DQS=0,MR1_ODS=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=0,MR1_TDQS=0,MR1_WL=0,MR2_ASR=0,MR2_CWL=0,MR2_RTT_WR=0,MR2_SRF=0,MR2_SRT=0,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEXTGEN=true,NUM_OF_PORTS=1,PARSE_FRIENDLY_DEVICE_FAMILY=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=MAX10,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=true,PINGPONGPHY_EN=false,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,RATE=Half,RDBUFFER_ADDR_WIDTH=7,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,REFRESH_BURST_VALIDATION=false,SCC_DATA_WIDTH=1,SOPC_COMPAT_RESET=false,SPEED_GRADE=6,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=MAX 10,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_TDH=45,TIMING_TDQSCK=225,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSQ=100,TIMING_TDQSS=0.27,TIMING_TDS=10,TIMING_TDSH=0.18,TIMING_TDSS=0.18,TIMING_TIH=120,TIMING_TIS=170,TIMING_TQH=0.38,TIMING_TQSH=0.4,TRK_PARALLEL_SCC_LOAD=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_HPS_DQS_TRACKING=false,USE_MEM_CLK_FREQ=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SHADOW_REGS=false,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6"
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instancePathKey="q_sys:.:ddr3_ram:.:c0:.:ng0"
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kind="altera_mem_if_nextgen_ddr3_controller_core"
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version="19.1"
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name="alt_mem_if_nextgen_ddr3_controller_core">
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<parameter name="VECT_ATTR_COUNTER_ZERO_MATCH" value="0" />
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<parameter name="ENUM_GANGED_ARF" value="DISABLED" />
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<parameter name="LRDIMM_INT" value="0" />
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<parameter name="ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
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<parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
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<parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="100" />
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<parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
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<parameter name="MEM_LEVELING" value="true" />
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<parameter name="CV_ENUM_PRIORITY_1_0" value="WEIGHT_0" />
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<parameter name="ENUM_MEM_IF_TRRD" value="TRRD_4" />
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<parameter name="CV_ENUM_PRIORITY_1_2" value="WEIGHT_0" />
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<parameter name="ENUM_ATTR_COUNTER_ZERO_RESET" value="DISABLED" />
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<parameter name="CV_ENUM_PRIORITY_1_1" value="WEIGHT_0" />
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<parameter name="MEM_ADD_LAT" value="0" />
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<parameter name="CV_ENUM_PRIORITY_1_4" value="WEIGHT_0" />
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<parameter name="CV_ENUM_PRIORITY_1_3" value="WEIGHT_0" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR" value="0" />
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<parameter name="CV_ENUM_PRIORITY_1_5" value="WEIGHT_0" />
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<parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT" value="0" />
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<parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
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<parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
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<parameter name="ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
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<parameter name="INTG_MEM_IF_TRFC" value="34" />
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<parameter name="MEM_REGDIMM_ENABLED" value="false" />
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<parameter name="AFI_DQ_WIDTH" value="32" />
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<parameter name="AP_MODE_EN" value="0" />
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<parameter name="ENUM_CPORT5_RDY_ALMOST_FULL" value="NOT_FULL" />
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<parameter name="INTG_SUM_WT_PRIORITY_4" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_5" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_6" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_7" value="0" />
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<parameter name="ENUM_CPORT2_RDY_ALMOST_FULL" value="NOT_FULL" />
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<parameter name="VECT_ATTR_COUNTER_ZERO_MASK" value="0" />
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<parameter name="ALLOCATED_WFIFO_PORT" value="0,None,None,None,None,None" />
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<parameter name="MEM_TRAS_NS" value="35.0" />
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<parameter name="INTG_SUM_WT_PRIORITY_0" value="0" />
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<parameter name="CV_ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
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<parameter name="INTG_SUM_WT_PRIORITY_1" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_2" value="0" />
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<parameter name="INTG_SUM_WT_PRIORITY_3" value="0" />
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<parameter name="ENABLE_BONDING" value="false" />
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<parameter name="HHP_HPS_VERIFICATION" value="false" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC" value="0" />
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<parameter name="CV_ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
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<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP" value="0" />
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<parameter name="ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
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<parameter name="RDIMM_CONFIG" value="0000000000000000" />
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<parameter name="CV_ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
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<parameter name="ENUM_ENABLE_INTR" value="DISABLED" />
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<parameter name="INTG_MEM_AUTO_PD_CYCLES" value="0" />
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<parameter name="AVL_DATA_WIDTH" value="32" />
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<parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
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<parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
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<parameter name="MR1_RDQS" value="0" />
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<parameter name="ENUM_MEM_IF_ROWADDR_WIDTH" value="ADDR_WIDTH_16" />
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<parameter name="MR0_PD" value="0" />
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<parameter name="MEM_VENDOR" value="JEDEC" />
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<parameter name="MEM_IF_CS_PER_RANK" value="1" />
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<parameter name="CV_PORT_1_CONNECT_TO_AV_PORT" value="1" />
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<parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
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<parameter name="CV_ENUM_CPORT1_TYPE" value="DISABLE" />
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<parameter name="USE_MEM_CLK_FREQ" value="false" />
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<parameter name="CV_MSB_WFIFO_PORT_5" value="5" />
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<parameter name="CFG_READ_ODT_CHIP" value="0" />
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<parameter name="CV_MSB_WFIFO_PORT_4" value="5" />
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<parameter name="CV_MSB_WFIFO_PORT_3" value="5" />
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<parameter name="RDIMM" value="false" />
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<parameter name="ENUM_MEM_IF_COLADDR_WIDTH" value="ADDR_WIDTH_12" />
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<parameter name="ENABLE_USER_ECC" value="false" />
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<parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD" value="0" />
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<parameter name="MEM_TRC" value="15" />
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<parameter name="AVL_ADDR_WIDTH_PORT_2" value="0" />
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<parameter name="ENUM_PRIORITY_6_4" value="WEIGHT_0" />
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<parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID" value="0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_3" value="USE_NO" />
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<parameter name="AVL_ADDR_WIDTH_PORT_1" value="0" />
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<parameter name="ENUM_PRIORITY_6_5" value="WEIGHT_0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_2" value="USE_NO" />
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<parameter name="AVL_ADDR_WIDTH_PORT_0" value="0" />
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<parameter name="ENUM_PRIORITY_6_2" value="WEIGHT_0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_5" value="USE_NO" />
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<parameter name="ENUM_PRIORITY_6_3" value="WEIGHT_0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_4" value="USE_NO" />
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<parameter name="ENUM_PRIORITY_6_0" value="WEIGHT_0" />
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<parameter name="AFI_CS_WIDTH" value="2" />
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<parameter name="AVL_ADDR_WIDTH_PORT_5" value="0" />
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<parameter name="ENUM_PRIORITY_6_1" value="WEIGHT_0" />
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<parameter name="AVL_ADDR_WIDTH_PORT_4" value="0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_1" value="USE_NO" />
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<parameter name="AVL_ADDR_WIDTH_PORT_3" value="0" />
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<parameter name="CV_ENUM_RD_PORT_INFO_0" value="USE_NO" />
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<parameter name="CV_MSB_WFIFO_PORT_2" value="5" />
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<parameter name="CV_MSB_WFIFO_PORT_1" value="5" />
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<parameter name="ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
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<parameter name="CV_MSB_WFIFO_PORT_0" value="5" />
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<parameter name="TG_TEMP_PORT_5" value="0" />
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<parameter name="TG_TEMP_PORT_3" value="0" />
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<parameter name="TG_TEMP_PORT_4" value="0" />
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<parameter name="TG_TEMP_PORT_1" value="0" />
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<parameter name="TG_TEMP_PORT_2" value="0" />
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<parameter name="TG_TEMP_PORT_0" value="0" />
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<parameter name="ENUM_MEM_IF_BURSTLENGTH" value="MEM_IF_BURSTLENGTH_8" />
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<parameter name="CFG_ENABLE_NO_DM" value="0" />
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<parameter name="MR1_TDQS" value="0" />
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<parameter name="INTG_MEM_CLK_ENTRY_CYCLES" value="10" />
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<parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
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<parameter name="CTL_ECC_MULTIPLES_16_24_40_72" value="1" />
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<parameter name="CV_ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
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<parameter name="ENUM_MEM_IF_TCWL" value="TCWL_5" />
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<parameter name="DEVICE_FAMILY" value="MAX 10" />
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<parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
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<parameter name="REFRESH_BURST_VALIDATION" value="false" />
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<parameter name="DEVICE_FAMILY_PARAM" value="MAX 10" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID" value="0" />
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<parameter name="ENUM_MEM_IF_TRTP" value="TRTP_4" />
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<parameter name="INTG_POWER_SAVING_EXIT_CYCLES" value="5" />
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<parameter name="MEM_IF_ADDR_WIDTH" value="14" />
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<parameter name="CSR_ADDR_WIDTH" value="8" />
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<parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID" value="0" />
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<parameter name="CV_ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
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<parameter name="CV_ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
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<parameter name="RDIMM_INT" value="0" />
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<parameter name="CV_ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
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<parameter name="CTL_CSR_READ_ONLY" value="1" />
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<parameter name="ENUM_MASK_DBE_INTR" value="DISABLED" />
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<parameter name="CV_ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
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<parameter name="CV_ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
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<parameter name="CV_ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
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<parameter name="AC_ROM_MR0_MIRR" value="0001000001001" />
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<parameter name="MEM_TWTR" value="6" />
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<parameter name="ENUM_ENABLE_BURST_INTERRUPT" value="DISABLED" />
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<parameter name="CV_ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
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<parameter name="WEIGHT_PORT_2" value="0" />
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<parameter name="WEIGHT_PORT_1" value="0" />
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<parameter name="WEIGHT_PORT_0" value="0" />
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<parameter name="WEIGHT_PORT_5" value="0" />
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<parameter name="WEIGHT_PORT_4" value="0" />
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<parameter name="WEIGHT_PORT_3" value="0" />
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<parameter name="ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
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<parameter name="CV_ENUM_ENABLE_BONDING_2" value="DISABLED" />
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<parameter name="CV_ENUM_ENABLE_BONDING_3" value="DISABLED" />
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<parameter name="MEM_TRFC_NS" value="110.0" />
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<parameter name="CV_ENUM_ENABLE_BONDING_4" value="DISABLED" />
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<parameter name="CV_ENUM_ENABLE_BONDING_5" value="DISABLED" />
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<parameter name="MR2_RTT_WR" value="0" />
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<parameter name="ENUM_MEM_IF_TFAW" value="TFAW_16" />
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<parameter name="AFI_ODT_WIDTH" value="2" />
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<parameter name="CV_ENUM_ENABLE_BONDING_0" value="DISABLED" />
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<parameter name="CV_ENUM_ENABLE_BONDING_1" value="DISABLED" />
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<parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL" value="NOT_FULL" />
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<parameter name="DISCRETE_FLY_BY" value="true" />
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<parameter name="AVL_SYMBOL_WIDTH" value="8" />
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<parameter name="MEM_IF_DM_WIDTH" value="1" />
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<parameter name="LOCAL_CS_WIDTH" value="0" />
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<parameter name="CTL_ECC_ENABLED" value="false" />
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<parameter name="AUTO_POWERDN_EN" value="false" />
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<parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL" value="NOT_FULL" />
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<parameter name="MAX_PENDING_WR_CMD" value="16" />
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<parameter name="ENUM_ATTR_COUNTER_ONE_RESET" value="DISABLED" />
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<parameter name="ENUM_WRITE_ODT_CHIP" value="ODT_DISABLED" />
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<parameter name="MEM_IF_CHIP_BITS" value="1" />
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<parameter name="ENUM_MEM_IF_CS_PER_RANK" value="MEM_IF_CS_PER_RANK_1" />
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<parameter name="MEM_IF_CK_WIDTH" value="1" />
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<parameter name="MEM_TCL" value="5" />
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<parameter name="ENUM_LOCAL_IF_CS_WIDTH" value="ADDR_WIDTH_2" />
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<parameter name="TIMING_TDQSCK" value="225" />
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<parameter name="CTL_USR_REFRESH_EN" value="false" />
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<parameter name="ENUM_WR_FIFO_IN_USE_3" value="FALSE" />
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<parameter name="ENUM_WR_FIFO_IN_USE_2" value="FALSE" />
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<parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP" value="1" />
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<parameter name="ENUM_WR_FIFO_IN_USE_1" value="FALSE" />
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<parameter name="ENUM_WR_FIFO_IN_USE_0" value="FALSE" />
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<parameter name="ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
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<parameter name="AFI_RATE_RATIO" value="2" />
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<parameter name="ENUM_THLD_JAR2_3" value="THRESHOLD_16" />
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<parameter name="ENUM_THLD_JAR2_4" value="THRESHOLD_16" />
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<parameter name="ENUM_THLD_JAR2_5" value="THRESHOLD_16" />
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<parameter name="AV_PORT_0_CONNECT_TO_CV_PORT" value="0" />
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<parameter name="ENUM_CTL_ECC_RMW_ENABLED" value="CTL_ECC_RMW_DISABLED" />
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<parameter name="CFG_TCCD_NS" value="2.5" />
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<parameter name="AVL_NUM_SYMBOLS" value="4" />
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<parameter name="CTL_OUTPUT_REGD" value="false" />
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<parameter name="CV_PORT_0_CONNECT_TO_AV_PORT" value="0" />
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<parameter name="CTL_CSR_ENABLED" value="false" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH" value="0" />
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<parameter name="DQ_DDR" value="1" />
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<parameter name="MEM_INIT_FILE" value="" />
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<parameter name="AVL_PORT" value="" />
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<parameter name="ALLOCATED_RFIFO_PORT" value="0,None,None,None,None,None" />
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<parameter name="MEM_CK_WIDTH" value="1" />
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<parameter name="MEM_ATCL" value="Disabled" />
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<parameter name="DISABLE_CHILD_MESSAGING" value="true" />
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<parameter name="AC_ROM_MR0_DLL_RESET" value="0001100010000" />
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<parameter name="MEM_TDQSCK" value="1" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD" value="0" />
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<parameter name="MEM_WTCL" value="5" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP" value="0" />
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<parameter name="CV_ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
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<parameter name="MEM_IF_CS_PER_DIMM" value="1" />
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<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="MAX10" />
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<parameter name="CTL_ECC_CSR_ENABLED" value="false" />
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<parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP" value="0" />
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<parameter name="MEM_AUTO_PD_CYCLES" value="0" />
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<parameter name="CV_ENUM_CPORT3_TYPE" value="DISABLE" />
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<parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
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<parameter name="CTL_ECC_MULTIPLES_40_72" value="1" />
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<parameter name="MSB_RFIFO_PORT_2" value="5" />
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<parameter name="MSB_RFIFO_PORT_3" value="5" />
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<parameter name="MSB_RFIFO_PORT_4" value="5" />
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<parameter name="MSB_RFIFO_PORT_5" value="5" />
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<parameter name="CV_ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
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<parameter name="MEM_DRV_STR" value="RZQ/6" />
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<parameter name="MEM_TREFI" value="2341" />
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<parameter name="MSB_RFIFO_PORT_0" value="5" />
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<parameter name="MEM_TRP_NS" value="13.75" />
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<parameter name="MSB_RFIFO_PORT_1" value="5" />
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<parameter name="CTL_HRB_ENABLED" value="false" />
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<parameter name="ENUM_MMR_CFG_MEM_BL" value="MP_BL_8" />
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<parameter name="MEM_IF_CS_WIDTH" value="1" />
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<parameter name="CV_ENUM_WR_PORT_INFO_1" value="USE_NO" />
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<parameter name="STARVE_LIMIT" value="10" />
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<parameter name="CV_ENUM_WR_PORT_INFO_2" value="USE_NO" />
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|
<parameter name="CV_ENUM_WR_PORT_INFO_3" value="USE_NO" />
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|
<parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP" value="1" />
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|
<parameter name="CV_ENUM_WR_PORT_INFO_4" value="USE_NO" />
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|
<parameter name="CV_ENUM_WR_PORT_INFO_0" value="USE_NO" />
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|
<parameter name="CTL_USR_REFRESH" value="0" />
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|
<parameter name="AV_PORT_2_CONNECT_TO_CV_PORT" value="2" />
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|
<parameter name="CV_ENUM_WR_PORT_INFO_5" value="USE_NO" />
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|
<parameter name="MR0_BT" value="0" />
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|
<parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL" value="0" />
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|
<parameter name="MR1_AL" value="0" />
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|
<parameter name="MR0_BL" value="1" />
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|
<parameter name="MEM_TRCD" value="5" />
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|
<parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
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|
<parameter name="MAX_PENDING_RD_CMD" value="32" />
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|
<parameter name="MEM_WTCL_INT" value="5" />
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|
<parameter name="MEM_IF_ROW_ADDR_WIDTH" value="14" />
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|
<parameter name="ENUM_CPORT1_TYPE" value="DISABLE" />
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|
<parameter name="AV_PORT_5_CONNECT_TO_CV_PORT" value="5" />
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|
<parameter name="MR0_DLL" value="1" />
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|
<parameter name="FORCE_SHADOW_REGS" value="AUTO" />
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|
<parameter name="PINGPONGPHY_EN" value="false" />
|
|
<parameter name="CFG_WRITE_ODT_CHIP" value="1" />
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|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_5" value="2" />
|
|
<parameter name="MR2_ASR" value="0" />
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|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_3" value="2" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_4" value="2" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_1" value="2" />
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|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_2" value="2" />
|
|
<parameter name="MR2_CWL" value="0" />
|
|
<parameter name="CV_AVL_NUM_SYMBOLS_PORT_0" value="2" />
|
|
<parameter name="HPS_PROTOCOL" value="DEFAULT" />
|
|
<parameter name="MEM_IF_LRDIMM_RM" value="0" />
|
|
<parameter name="VECT_ATTR_COUNTER_ONE_MATCH" value="0" />
|
|
<parameter name="ENUM_PRIORITY_1_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_1_1" value="WEIGHT_0" />
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|
<parameter name="ENUM_PRIORITY_1_2" value="WEIGHT_0" />
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|
<parameter name="ENUM_PRIORITY_1_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="DUPLICATE_AC" value="false" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_5" value="2" />
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|
<parameter name="AVL_NUM_SYMBOLS_PORT_1" value="2" />
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|
<parameter name="AVL_NUM_SYMBOLS_PORT_2" value="2" />
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|
<parameter name="AC_ROM_MR1_MIRR" value="0000000000000" />
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|
<parameter name="AVL_NUM_SYMBOLS_PORT_3" value="2" />
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|
<parameter name="AVL_NUM_SYMBOLS_PORT_4" value="2" />
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|
<parameter name="CFG_POWER_SAVING_EXIT_CYCLES" value="5" />
|
|
<parameter name="AVL_NUM_SYMBOLS_PORT_0" value="2" />
|
|
<parameter name="CV_PORT_2_CONNECT_TO_AV_PORT" value="2" />
|
|
<parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
|
|
<parameter name="AUTO_PD_CYCLES" value="0" />
|
|
<parameter name="ENUM_CPORT5_TYPE" value="DISABLE" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD" value="0" />
|
|
<parameter name="AFI_BANKADDR_WIDTH" value="6" />
|
|
<parameter name="CV_ENUM_CPORT0_TYPE" value="DISABLE" />
|
|
<parameter name="ENUM_THLD_JAR2_0" value="THRESHOLD_16" />
|
|
<parameter name="CTL_DEEP_POWERDN_EN" value="false" />
|
|
<parameter name="CTL_TBP_NUM" value="4" />
|
|
<parameter name="ENUM_THLD_JAR2_1" value="THRESHOLD_16" />
|
|
<parameter name="MEM_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="ENUM_THLD_JAR2_2" value="THRESHOLD_16" />
|
|
<parameter name="CTL_ENABLE_BURST_TERMINATE_INT" value="false" />
|
|
<parameter name="CFG_ECC_DECODER_REG" value="0" />
|
|
<parameter name="CTL_ENABLE_BURST_INTERRUPT_INT" value="false" />
|
|
<parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
|
|
<parameter name="MR1_RTT" value="0" />
|
|
<parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0001010001000" />
|
|
<parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
|
|
<parameter name="CSR_DATA_WIDTH" value="32" />
|
|
<parameter name="MEM_DLL_EN" value="true" />
|
|
<parameter name="IS_ES_DEVICE" value="false" />
|
|
<parameter name="PRE_V_SERIES_FAMILY" value="false" />
|
|
<parameter name="USE_MM_ADAPTOR" value="true" />
|
|
<parameter name="HHP_HPS_SIMULATION" value="false" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_1" value="WEIGHT_0" />
|
|
<parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_0" value="WEIGHT_0" />
|
|
<parameter name="HCX_COMPAT_MODE" value="false" />
|
|
<parameter name="MEM_IF_DQSN_EN" value="true" />
|
|
<parameter name="ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="AC_ROM_MR0" value="0001000010001" />
|
|
<parameter name="MEM_TRAS" value="11" />
|
|
<parameter name="ENUM_ECC_DQ_WIDTH" value="ECC_DQ_WIDTH_0" />
|
|
<parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP" value="0" />
|
|
<parameter name="MEM_TINIT_US" value="500" />
|
|
<parameter name="CTL_SELF_REFRESH" value="0" />
|
|
<parameter name="ENUM_MEM_IF_TWTR" value="TWTR_4" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
|
|
<parameter name="ENUM_USER_ECC_EN" value="DISABLE" />
|
|
<parameter name="AC_ROM_MR2" value="0000000000000" />
|
|
<parameter name="AC_ROM_MR1" value="0000000000000" />
|
|
<parameter name="AC_ROM_MR3" value="0000000000000" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH" value="0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID" value="0" />
|
|
<parameter name="ENUM_CFG_BURST_LENGTH" value="BL_8" />
|
|
<parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_2" value="WEIGHT_0" />
|
|
<parameter name="MEM_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_6_4" value="WEIGHT_0" />
|
|
<parameter name="MEM_SRT" value="Normal" />
|
|
<parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
|
|
<parameter name="MEM_IF_READ_DQS_WIDTH" value="1" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
|
|
<parameter name="CV_ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
|
|
<parameter name="CFG_TYPE" value="2" />
|
|
<parameter name="ENUM_CLR_INTR" value="NO_CLR_INTR" />
|
|
<parameter name="ENUM_CPORT3_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_1" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_2" value="WEIGHT_0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID" value="0" />
|
|
<parameter name="ENUM_PRIORITY_5_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_5_0" value="WEIGHT_0" />
|
|
<parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="AV_PORT_1_CONNECT_TO_CV_PORT" value="1" />
|
|
<parameter name="CV_PORT_5_CONNECT_TO_AV_PORT" value="5" />
|
|
<parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="1" />
|
|
<parameter name="MEM_TMRD_CK" value="4" />
|
|
<parameter name="CFG_INTERFACE_WIDTH" value="8" />
|
|
<parameter name="DEVICE_DEPTH" value="1" />
|
|
<parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
|
|
<parameter name="CV_ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_MASK_CORR_DROPPED_INTR" value="DISABLED" />
|
|
<parameter name="ENUM_ATTR_STATIC_CONFIG_VALID" value="DISABLED" />
|
|
<parameter name="CTL_ENABLE_WDATA_PATH_LATENCY" value="false" />
|
|
<parameter name="ENUM_CLOCK_OFF_2" value="DISABLED" />
|
|
<parameter name="ENUM_CLOCK_OFF_1" value="DISABLED" />
|
|
<parameter name="ENUM_CLOCK_OFF_0" value="DISABLED" />
|
|
<parameter name="CFG_BURST_LENGTH" value="8" />
|
|
<parameter name="ENUM_CLOCK_OFF_5" value="DISABLED" />
|
|
<parameter name="ENUM_CLOCK_OFF_4" value="DISABLED" />
|
|
<parameter name="ENUM_CLOCK_OFF_3" value="DISABLED" />
|
|
<parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_4_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="CFG_MEM_CLK_ENTRY_CYCLES" value="20" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
|
|
<parameter name="ENUM_CFG_INTERFACE_WIDTH" value="DWIDTH_32" />
|
|
<parameter name="ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="MEM_ATCL_INT" value="0" />
|
|
<parameter name="ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="CV_ENUM_CPORT4_TYPE" value="DISABLE" />
|
|
<parameter name="TIMING_TDSS" value="0.18" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_1" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_0" value="WEIGHT_0" />
|
|
<parameter name="CSR_BE_WIDTH" value="4" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_2" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_2_4" value="WEIGHT_0" />
|
|
<parameter name="MEM_TRTP_NS" value="7.5" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_2" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_3" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_0" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_1" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_4" value="0" />
|
|
<parameter name="CV_CPORT_TYPE_PORT_5" value="0" />
|
|
<parameter name="ENUM_PRIORITY_3_5" value="WEIGHT_0" />
|
|
<parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
|
|
<parameter name="AP_MODE" value="false" />
|
|
<parameter name="ENUM_PRIORITY_3_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_3_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_3_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_3_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_3_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_MEM_IF_MEMTYPE" value="DDR3_SDRAM" />
|
|
<parameter name="MEM_PD" value="DLL off" />
|
|
<parameter name="TIMING_TDSH" value="0.18" />
|
|
<parameter name="CTL_AUTOPCH_EN" value="false" />
|
|
<parameter name="ENUM_PDN_EXIT_CYCLES" value="SLOW_EXIT" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID" value="0" />
|
|
<parameter name="MEM_DQ_WIDTH" value="8" />
|
|
<parameter name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES" value="" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="FLY_BY" value="true" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="TIMING_TQSH" value="0.4" />
|
|
<parameter name="CV_ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="LSB_RFIFO_PORT_0" value="5" />
|
|
<parameter name="AFI_CLK_PAIR_COUNT" value="1" />
|
|
<parameter name="HARD_EMIF" value="false" />
|
|
<parameter name="LSB_RFIFO_PORT_5" value="5" />
|
|
<parameter name="LSB_RFIFO_PORT_3" value="5" />
|
|
<parameter name="LSB_RFIFO_PORT_4" value="5" />
|
|
<parameter name="LSB_RFIFO_PORT_1" value="5" />
|
|
<parameter name="CV_ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="LSB_RFIFO_PORT_2" value="5" />
|
|
<parameter name="MEM_CLK_MAX_NS" value="1.25" />
|
|
<parameter name="DWIDTH_RATIO" value="4" />
|
|
<parameter name="INTG_MEM_IF_TREFI" value="3120" />
|
|
<parameter name="CFG_CLR_INTR" value="0" />
|
|
<parameter name="ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_ENABLE_NO_DM" value="DISABLED" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="MEM_TINIT_CK" value="150000" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
|
|
<parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
|
|
<parameter name="MEM_BL" value="OTF" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="true" />
|
|
<parameter name="ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
|
|
<parameter name="MEM_BT" value="Sequential" />
|
|
<parameter name="ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
|
|
<parameter name="CONTROLLER_LATENCY" value="5" />
|
|
<parameter name="MEM_TRTP" value="3" />
|
|
<parameter name="ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
|
|
<parameter name="ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
|
|
<parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
|
|
<parameter name="MEM_DQ_PER_DQS" value="8" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CTL_REGDIMM_ENABLED" value="REGDIMM_DISABLED" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_2" value="WEIGHT_0" />
|
|
<parameter name="ENABLE_BURST_MERGE" value="false" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_0_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_CPORT5_TYPE" value="DISABLE" />
|
|
<parameter name="ENUM_ENABLE_BURST_TERMINATE" value="DISABLED" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
|
|
<parameter name="VECT_ATTR_DEBUG_SELECT_BYTE" value="0" />
|
|
<parameter name="CV_PORT_4_CONNECT_TO_AV_PORT" value="4" />
|
|
<parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
|
|
<parameter name="DEVICE_WIDTH" value="1" />
|
|
<parameter name="SOPC_COMPAT_RESET" value="false" />
|
|
<parameter name="ENUM_ENABLE_PIPELINEGLOBAL" value="DISABLED" />
|
|
<parameter name="AFI_CONTROL_WIDTH" value="2" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_6" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_7" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_4" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_5" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_2" value="0" />
|
|
<parameter name="MEM_IF_DM_PINS_EN" value="true" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_3" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_0" value="0" />
|
|
<parameter name="CV_INTG_SUM_WT_PRIORITY_1" value="0" />
|
|
<parameter name="ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
|
|
<parameter name="ENUM_SINGLE_READY_3" value="CONCATENATE_RDY" />
|
|
<parameter name="ENUM_SINGLE_READY_1" value="CONCATENATE_RDY" />
|
|
<parameter name="ENUM_SINGLE_READY_2" value="CONCATENATE_RDY" />
|
|
<parameter name="ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_GEN_DBE" value="GEN_DBE_DISABLED" />
|
|
<parameter name="ENUM_SINGLE_READY_0" value="CONCATENATE_RDY" />
|
|
<parameter name="DATA_RATE_RATIO" value="2" />
|
|
<parameter name="ENUM_ENABLE_DQS_TRACKING" value="DISABLED" />
|
|
<parameter name="ENUM_ENABLE_BONDING_3" value="DISABLED" />
|
|
<parameter name="ENUM_ENABLE_BONDING_2" value="DISABLED" />
|
|
<parameter name="ENUM_ENABLE_BONDING_5" value="DISABLED" />
|
|
<parameter name="ENUM_MEM_IF_TCL" value="TCL_6" />
|
|
<parameter name="ENUM_ENABLE_BONDING_4" value="DISABLED" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="LOW_LATENCY" value="false" />
|
|
<parameter name="ENUM_ENABLE_BONDING_1" value="DISABLED" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
|
|
<parameter name="ENUM_ENABLE_BONDING_0" value="DISABLED" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="CV_ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="ENUM_MEM_IF_DQ_PER_CHIP" value="MEM_IF_DQ_PER_CHIP_8" />
|
|
<parameter name="ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="RATE" value="Half" />
|
|
<parameter name="MR1_WL" value="0" />
|
|
<parameter name="POWER_OF_TWO_BUS" value="false" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="MR3_MPR_RF" value="0" />
|
|
<parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
|
|
<parameter name="DEBUG_MODE" value="false" />
|
|
<parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
|
|
<parameter name="CFG_STARVE_LIMIT" value="10" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT" value="0" />
|
|
<parameter name="ENUM_PRIORITY_7_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_7_4" value="WEIGHT_0" />
|
|
<parameter name="MEM_CLK_MAX_PS" value="1250.0" />
|
|
<parameter name="ENUM_PRIORITY_7_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_7_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_7_0" value="WEIGHT_0" />
|
|
<parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
|
|
<parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
|
|
<parameter name="ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
|
|
<parameter name="MEM_BURST_LENGTH" value="8" />
|
|
<parameter name="ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
|
|
<parameter name="ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
|
|
<parameter name="ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
|
|
<parameter name="MEM_TRRD" value="2" />
|
|
<parameter name="ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
|
|
<parameter name="ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
|
|
<parameter name="ENUM_PRIORITY_7_5" value="WEIGHT_0" />
|
|
<parameter name="MEM_INIT_EN" value="false" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH" value="0" />
|
|
<parameter name="ADDR_RATE_RATIO" value="1" />
|
|
<parameter name="CFG_SELF_RFSH_EXIT_CYCLES" value="512" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
|
|
<parameter name="CTL_REGDIMM_ENABLED" value="false" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_1" value="5" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_0" value="5" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_0" value="0" />
|
|
<parameter name="CV_ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_GEN_SBE" value="GEN_SBE_DISABLED" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
|
|
<parameter name="ENUM_ENABLE_BONDING_WRAPBACK" value="DISABLED" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_2" value="0" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_1" value="0" />
|
|
<parameter name="INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
|
|
<parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
|
|
<parameter name="ENUM_THLD_JAR1_4" value="THRESHOLD_32" />
|
|
<parameter name="MEM_RTT_NOM" value="ODT Disabled" />
|
|
<parameter name="ENUM_THLD_JAR1_5" value="THRESHOLD_32" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_4" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_3" value="0" />
|
|
<parameter name="CV_AVL_ADDR_WIDTH_PORT_5" value="0" />
|
|
<parameter name="AFI_WRANK_WIDTH" value="2" />
|
|
<parameter name="LRDIMM" value="false" />
|
|
<parameter name="MR1_DLL" value="0" />
|
|
<parameter name="CFG_ADDR_ORDER" value="0" />
|
|
<parameter name="ENUM_WR_PORT_INFO_0" value="USE_NO" />
|
|
<parameter name="CTL_ODT_ENABLED" value="false" />
|
|
<parameter name="ENUM_WR_PORT_INFO_5" value="USE_NO" />
|
|
<parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="SYS_INFO_DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="ENUM_WR_PORT_INFO_1" value="USE_NO" />
|
|
<parameter name="ENUM_WR_PORT_INFO_2" value="USE_NO" />
|
|
<parameter name="ENUM_WR_PORT_INFO_3" value="USE_NO" />
|
|
<parameter name="ENUM_WR_PORT_INFO_4" value="USE_NO" />
|
|
<parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
|
|
<parameter name="ENUM_THLD_JAR1_0" value="THRESHOLD_32" />
|
|
<parameter name="ENUM_THLD_JAR1_1" value="THRESHOLD_32" />
|
|
<parameter name="ENUM_THLD_JAR1_2" value="THRESHOLD_32" />
|
|
<parameter name="ENUM_THLD_JAR1_3" value="THRESHOLD_32" />
|
|
<parameter name="ENUM_CPORT2_TYPE" value="DISABLE" />
|
|
<parameter name="ENUM_ENABLE_ATPG" value="DISABLED" />
|
|
<parameter name="MEM_FORMAT" value="DISCRETE" />
|
|
<parameter name="CONTROLLER_TYPE" value="nextgen_v110" />
|
|
<parameter name="AFI_WLAT_WIDTH" value="6" />
|
|
<parameter name="MEM_IF_WRITE_DQS_WIDTH" value="1" />
|
|
<parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
|
|
<parameter name="CTL_CS_WIDTH" value="1" />
|
|
<parameter name="ENUM_OUTPUT_REGD" value="DISABLED" />
|
|
<parameter name="MR1_ODS" value="0" />
|
|
<parameter name="MEM_TRFC" value="34" />
|
|
<parameter name="AV_PORT_4_CONNECT_TO_CV_PORT" value="4" />
|
|
<parameter name="ENUM_SYNC_MODE_1" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_SYNC_MODE_0" value="ASYNCHRONOUS" />
|
|
<parameter name="ENUM_SYNC_MODE_3" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_SYNC_MODE_2" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CPORT1_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="ENUM_SYNC_MODE_5" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CPORT4_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="ENUM_SYNC_MODE_4" value="ASYNCHRONOUS" />
|
|
<parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
|
|
<parameter name="FORCE_DQS_TRACKING" value="AUTO" />
|
|
<parameter name="ENUM_CFG_TYPE" value="DDR3" />
|
|
<parameter name="CV_ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="ADDR_ORDER" value="0" />
|
|
<parameter name="MEM_VERBOSE" value="true" />
|
|
<parameter name="HARD_PHY" value="false" />
|
|
<parameter name="MR2_SRF" value="0" />
|
|
<parameter name="ENUM_CPORT4_TYPE" value="DISABLE" />
|
|
<parameter name="ENUM_MEM_IF_BANKADDR_WIDTH" value="ADDR_WIDTH_3" />
|
|
<parameter name="ENUM_MASK_SBE_INTR" value="DISABLED" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK" value="0" />
|
|
<parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
|
|
<parameter name="ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_READ_ODT_CHIP" value="ODT_DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
|
|
<parameter name="ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
|
|
<parameter name="VECT_ATTR_COUNTER_ONE_MASK" value="0" />
|
|
<parameter name="MULTICAST_EN" value="false" />
|
|
<parameter name="CV_ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
|
|
<parameter name="ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="AC_PARITY" value="false" />
|
|
<parameter name="AC_ROM_MR2_MIRR" value="0000000000000" />
|
|
<parameter name="MR1_DQS" value="0" />
|
|
<parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES" value="DISABLED" />
|
|
<parameter name="MR2_SRT" value="0" />
|
|
<parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
|
|
<parameter name="ENUM_MEM_IF_TMRD" value="" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_3" value="5" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_2" value="5" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_5" value="5" />
|
|
<parameter name="CV_LSB_WFIFO_PORT_4" value="5" />
|
|
<parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
|
|
<parameter name="MR1_QOFF" value="0" />
|
|
<parameter name="MEM_CLK_FREQ" value="300.0" />
|
|
<parameter name="MEM_CLK_EN_WIDTH" value="1" />
|
|
<parameter name="CV_ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_MEM_IF_TWR" value="TWR_6" />
|
|
<parameter name="ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="MEM_TYPE" value="DDR3" />
|
|
<parameter name="ENUM_MEM_IF_TRAS" value="TRAS_16" />
|
|
<parameter name="ENUM_INC_SYNC" value="FIFO_SET_2" />
|
|
<parameter name="ENUM_MEM_IF_TRCD" value="TRCD_6" />
|
|
<parameter name="TIMING_TIS" value="170" />
|
|
<parameter name="ENUM_PRIORITY_0_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_0_5" value="WEIGHT_0" />
|
|
<parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
|
|
<parameter name="ENUM_PRIORITY_0_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_0_3" value="WEIGHT_0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID" value="0" />
|
|
<parameter name="ENUM_PRIORITY_0_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_0_1" value="WEIGHT_0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR" value="0" />
|
|
<parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
|
|
<parameter name="AVL_ADDR_WIDTH" value="25" />
|
|
<parameter name="CV_ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="MAX10_CFG" value="true" />
|
|
<parameter name="CFG_REORDER_DATA" value="true" />
|
|
<parameter name="ENUM_ENABLE_FAST_EXIT_PPD" value="DISABLED" />
|
|
<parameter name="ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="CONTINUE_AFTER_CAL_FAIL" value="false" />
|
|
<parameter name="AFI_RRANK_WIDTH" value="2" />
|
|
<parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="MR3_MPR" value="0" />
|
|
<parameter name="ENUM_CFG_STARVE_LIMIT" value="STARVE_LIMIT_32" />
|
|
<parameter name="MEM_IF_ODT_WIDTH" value="1" />
|
|
<parameter name="TIMING_TDQSCKDL" value="1200" />
|
|
<parameter name="TIMING_TDQSCKDS" value="450" />
|
|
<parameter name="TIMING_TDQSCKDM" value="900" />
|
|
<parameter name="ENUM_MEM_IF_TCCD" value="TCCD_4" />
|
|
<parameter name="CV_ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="AVL_BE_WIDTH" value="4" />
|
|
<parameter name="AVL_MAX_SIZE" value="4" />
|
|
<parameter name="ENUM_CTL_USR_REFRESH" value="CTL_USR_REFRESH_DISABLED" />
|
|
<parameter name="CV_ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CFG_ERRCMD_FIFO_REG" value="0" />
|
|
<parameter name="ENUM_DISABLE_MERGING" value="MERGING_ENABLED" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_0" value="WEIGHT_0" />
|
|
<parameter name="ENUM_CTL_ADDR_ORDER" value="CHIP_BANK_ROW_COL" />
|
|
<parameter name="AFI_DM_WIDTH" value="4" />
|
|
<parameter name="ENUM_CTL_ECC_ENABLED" value="CTL_ECC_DISABLED" />
|
|
<parameter name="BYTE_ENABLE" value="true" />
|
|
<parameter name="USE_SHADOW_REGS" value="false" />
|
|
<parameter name="ENUM_MEM_IF_CS_WIDTH" value="MEM_IF_CS_WIDTH_1" />
|
|
<parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
|
|
<parameter name="CV_ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="ENUM_CAL_REQ" value="DISABLED" />
|
|
<parameter name="ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="MEM_IF_DQ_WIDTH" value="8" />
|
|
<parameter name="ADDR_CMD_DDR" value="0" />
|
|
<parameter name="MR3_MPR_AA" value="0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_1" value="0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_0" value="0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_3" value="0" />
|
|
<parameter name="MEM_TFAW_NS" value="30.0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_2" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_5" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_4" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_3" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_2" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_1" value="0" />
|
|
<parameter name="AVL_DATA_WIDTH_PORT_0" value="0" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_5" value="0" />
|
|
<parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
|
|
<parameter name="CV_AVL_DATA_WIDTH_PORT_4" value="0" />
|
|
<parameter name="AFI_CLK_EN_WIDTH" value="2" />
|
|
<parameter name="TIMING_TQH" value="0.38" />
|
|
<parameter name="ENUM_MEM_IF_DWIDTH" value="MEM_IF_DWIDTH_32" />
|
|
<parameter name="ENUM_RD_PORT_INFO_2" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_PORT_INFO_3" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_PORT_INFO_4" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
|
|
<parameter name="ENUM_MEM_IF_SPEEDBIN" value="DDR3_1066_6_6_6" />
|
|
<parameter name="ENUM_RD_PORT_INFO_5" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
|
|
<parameter name="ENUM_CPORT0_TYPE" value="DISABLE" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_MEM_IF_TRP" value="TRP_6" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_1" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_3" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_7_5" value="WEIGHT_0" />
|
|
<parameter name="HHP_HPS" value="false" />
|
|
<parameter name="CV_ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
|
|
<parameter name="ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="AVL_SIZE_WIDTH" value="3" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING" value="0" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
|
|
<parameter name="RDBUFFER_ADDR_WIDTH" value="7" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
|
|
<parameter name="ENUM_MEM_IF_TRC" value="TRC_22" />
|
|
<parameter name="ENUM_RD_PORT_INFO_0" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
|
|
<parameter name="ENUM_RD_PORT_INFO_1" value="USE_NO" />
|
|
<parameter name="CV_ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
|
|
<parameter name="CV_ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
|
|
<parameter name="DAT_DATA_WIDTH" value="32" />
|
|
<parameter
|
|
name="CPORT_TYPE_PORT"
|
|
value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
|
|
<parameter name="AC_ROM_MR1_CALIB" value="" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_5" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_4" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_3" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_2" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_1" value="1" />
|
|
<parameter name="INTG_CYC_TO_RLD_JARS_0" value="1" />
|
|
<parameter name="SPEED_GRADE" value="6" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_0" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_1" value="WEIGHT_0" />
|
|
<parameter name="MEM_TRCD_NS" value="13.75" />
|
|
<parameter name="ENUM_PRIORITY_4_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_5" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_4_0" value="WEIGHT_0" />
|
|
<parameter name="AFI_ADDR_WIDTH" value="28" />
|
|
<parameter name="ENUM_PRIORITY_4_1" value="WEIGHT_0" />
|
|
<parameter name="USE_HPS_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="EXPORT_CSR_PORT" value="false" />
|
|
<parameter name="CTL_SELF_REFRESH_EN" value="false" />
|
|
<parameter name="MSB_WFIFO_PORT_0" value="5" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_5" value="5" />
|
|
<parameter name="MSB_WFIFO_PORT_1" value="5" />
|
|
<parameter name="TIMING_TDS" value="10" />
|
|
<parameter name="MSB_WFIFO_PORT_2" value="5" />
|
|
<parameter name="MSB_WFIFO_PORT_3" value="5" />
|
|
<parameter name="MSB_WFIFO_PORT_4" value="5" />
|
|
<parameter name="MSB_WFIFO_PORT_5" value="5" />
|
|
<parameter name="CFG_TCCD" value="1" />
|
|
<parameter name="ENUM_MEM_IF_AL" value="AL_0" />
|
|
<parameter name="ENUM_TEST_MODE" value="NORMAL_MODE" />
|
|
<parameter name="MEM_CS_WIDTH" value="1" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_0" value="5" />
|
|
<parameter name="ENUM_CPORT0_RDY_ALMOST_FULL" value="NOT_FULL" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_2" value="5" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_1" value="5" />
|
|
<parameter name="TIMING_TDH" value="45" />
|
|
<parameter name="AV_PORT_3_CONNECT_TO_CV_PORT" value="3" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_4" value="5" />
|
|
<parameter name="SCC_DATA_WIDTH" value="1" />
|
|
<parameter name="CV_LSB_RFIFO_PORT_3" value="5" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC" value="0" />
|
|
<parameter name="CV_ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="MEM_TREFI_US" value="7.8" />
|
|
<parameter name="USE_DQS_TRACKING" value="false" />
|
|
<parameter name="MEM_LRDIMM_ENABLED" value="false" />
|
|
<parameter name="ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_MEM_IF_DQS_WIDTH" value="DQS_WIDTH_4" />
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|
<parameter name="CTL_ZQCAL_EN" value="false" />
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<parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
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<parameter name="ENUM_DFX_BYPASS_ENABLE" value="DFX_BYPASS_DISABLED" />
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|
<parameter name="AC_ROM_MR0_CALIB" value="" />
|
|
<parameter name="MEM_TWR_NS" value="15.0" />
|
|
<parameter name="ENUM_CTRL_WIDTH" value="DATA_WIDTH_64_BIT" />
|
|
<parameter name="CV_ENUM_PRIORITY_5_4" value="WEIGHT_0" />
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|
<parameter name="AFI_WRITE_DQS_WIDTH" value="2" />
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|
<parameter name="CV_ENUM_PRIORITY_5_3" value="WEIGHT_0" />
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|
<parameter name="CV_ENUM_PRIORITY_5_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_CPORT2_TYPE" value="DISABLE" />
|
|
<parameter name="AFI_RLAT_WIDTH" value="6" />
|
|
<parameter name="ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
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|
<parameter name="MEM_TRP" value="5" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR" value="0" />
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|
<parameter name="ENUM_USE_ALMOST_EMPTY_1" value="EMPTY" />
|
|
<parameter name="ENUM_USE_ALMOST_EMPTY_2" value="EMPTY" />
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|
<parameter name="ENUM_USE_ALMOST_EMPTY_3" value="EMPTY" />
|
|
<parameter name="MEM_TRRD_NS" value="6.0" />
|
|
<parameter name="CV_PORT_3_CONNECT_TO_AV_PORT" value="3" />
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|
<parameter name="ENUM_DELAY_BONDING" value="BONDING_LATENCY_0" />
|
|
<parameter name="ENUM_USE_ALMOST_EMPTY_0" value="EMPTY" />
|
|
<parameter name="LSB_WFIFO_PORT_4" value="5" />
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|
<parameter name="LSB_WFIFO_PORT_5" value="5" />
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|
<parameter name="LSB_WFIFO_PORT_2" value="5" />
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|
<parameter name="LSB_WFIFO_PORT_3" value="5" />
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|
<parameter name="MR0_CAS_LATENCY" value="1" />
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|
<parameter name="LSB_WFIFO_PORT_0" value="5" />
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|
<parameter name="LSB_WFIFO_PORT_1" value="5" />
|
|
<parameter name="CFG_PDN_EXIT_CYCLES" value="10" />
|
|
<parameter name="MR0_WR" value="1" />
|
|
<parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL" value="NOT_FULL" />
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|
<parameter name="CV_ENUM_PRIORITY_3_0" value="WEIGHT_0" />
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<parameter name="CV_ENUM_PRIORITY_3_2" value="WEIGHT_0" />
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<parameter name="CV_ENUM_PRIORITY_3_1" value="WEIGHT_0" />
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|
<parameter name="CV_ENUM_PRIORITY_3_4" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_3" value="WEIGHT_0" />
|
|
<parameter name="LOCAL_ID_WIDTH" value="8" />
|
|
<parameter name="TIMING_TDQSS" value="0.27" />
|
|
<parameter name="TIMING_TDQSQ" value="100" />
|
|
<parameter name="ENUM_PRIORITY_2_4" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_2_5" value="WEIGHT_0" />
|
|
<parameter name="CV_ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_PRIORITY_2_2" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_2_3" value="WEIGHT_0" />
|
|
<parameter name="ENUM_PRIORITY_2_0" value="WEIGHT_0" />
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|
<parameter name="ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
|
|
<parameter name="ENUM_PRIORITY_2_1" value="WEIGHT_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
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|
<parameter name="ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
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|
<parameter name="ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
|
|
<parameter name="ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
|
|
<parameter name="MEM_ASR" value="Manual" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_2" value="FALSE" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_3" value="FALSE" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_0" value="FALSE" />
|
|
<parameter name="ENUM_RD_FIFO_IN_USE_1" value="FALSE" />
|
|
<parameter name="ENUM_REORDER_DATA" value="DATA_REORDERING" />
|
|
<parameter name="NEXTGEN" value="true" />
|
|
<parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
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|
<parameter name="PRIORITY_PORT_0" value="0" />
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|
<parameter name="MEM_TWR" value="5" />
|
|
<parameter name="PRIORITY_PORT_2" value="0" />
|
|
<parameter name="PRIORITY_PORT_1" value="0" />
|
|
<parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
|
|
<parameter name="CPORT_TYPE_PORT_3" value="0" />
|
|
<parameter name="MEM_IF_DQS_WIDTH" value="1" />
|
|
<parameter name="CPORT_TYPE_PORT_2" value="0" />
|
|
<parameter name="CPORT_TYPE_PORT_1" value="0" />
|
|
<parameter name="TIMING_TIH" value="120" />
|
|
<parameter name="CPORT_TYPE_PORT_0" value="0" />
|
|
<parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD" value="0" />
|
|
<parameter name="USE_AXI_ADAPTOR" value="false" />
|
|
<parameter name="PRIORITY_PORT_4" value="0" />
|
|
<parameter name="PRIORITY_PORT_3" value="0" />
|
|
<parameter name="PRIORITY_PORT_5" value="0" />
|
|
<parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
|
|
<parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
|
|
<parameter name="ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
|
|
<parameter name="ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
|
|
<parameter name="NUM_OF_PORTS" value="1" />
|
|
<parameter name="CV_ENUM_PRIORITY_3_5" value="WEIGHT_0" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
|
|
<parameter name="ENUM_CPORT3_TYPE" value="DISABLE" />
|
|
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="MAX10" />
|
|
<parameter name="CPORT_TYPE_PORT_5" value="0" />
|
|
<parameter name="CPORT_TYPE_PORT_4" value="0" />
|
|
<parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_1" value="5" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_0" value="5" />
|
|
<parameter name="ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_5" value="5" />
|
|
<parameter name="MEM_TFAW" value="10" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_4" value="5" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_3" value="5" />
|
|
<parameter name="CV_ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
|
|
<parameter name="CV_MSB_RFIFO_PORT_2" value="5" />
|
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_addr_cmd.v"
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type="VERILOG"
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attributes="" />
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type="VERILOG"
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attributes="" />
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attributes="" />
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type="VERILOG"
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attributes="" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v"
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type="VERILOG"
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attributes="" />
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type="VERILOG"
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attributes="" />
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<file
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path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v"
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type="VERILOG"
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attributes="" />
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<file
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attributes="" />
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attributes="" />
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attributes="" />
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attributes="" />
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<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_ddr3_ram_c0" as="ng0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 6 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core"</message>
|
|
<message level="Info" culprit="ng0"><![CDATA["<b>c0</b>" instantiated <b>altera_mem_if_nextgen_ddr3_controller_core</b> "<b>ng0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="alt_mem_ddrx_mm_st_converter:19.1:AVL_ADDR_WIDTH=25,AVL_BYTE_ENABLE=true,AVL_DATA_WIDTH=32,AVL_NUM_SYMBOLS=4,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,CFG_DWIDTH_RATIO=4,CTL_AUTOPCH_EN=false,CTL_ECC_ENABLED=false,ENABLE_CTRL_AVALON_INTERFACE=true,LOCAL_ID_WIDTH=8,MAX_PENDING_READ_TRANSACTION=32,MULTICAST_EN=false"
|
|
instancePathKey="q_sys:.:ddr3_ram:.:c0:.:a0"
|
|
kind="alt_mem_ddrx_mm_st_converter"
|
|
version="19.1"
|
|
name="alt_mem_ddrx_mm_st_converter">
|
|
<parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
|
|
<parameter name="MAX_PENDING_READ_TRANSACTION" value="32" />
|
|
<parameter name="AVL_DATA_WIDTH" value="32" />
|
|
<parameter name="MULTICAST_EN" value="false" />
|
|
<parameter name="AVL_SYMBOL_WIDTH" value="8" />
|
|
<parameter name="CTL_AUTOPCH_EN" value="false" />
|
|
<parameter name="AVL_SIZE_WIDTH" value="3" />
|
|
<parameter name="AVL_BYTE_ENABLE" value="true" />
|
|
<parameter name="CTL_ECC_ENABLED" value="false" />
|
|
<parameter name="LOCAL_ID_WIDTH" value="8" />
|
|
<parameter name="AVL_ADDR_WIDTH" value="25" />
|
|
<parameter name="AVL_NUM_SYMBOLS" value="4" />
|
|
<parameter name="CFG_DWIDTH_RATIO" value="4" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr_controller_110/rtl/alt_mem_ddrx_mm_st_converter/alt_mem_ddrx_mm_st_converter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator instantiator="q_sys_ddr3_ram_c0" as="a0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 5 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter"</message>
|
|
<message level="Info" culprit="a0"><![CDATA["<b>c0</b>" instantiated <b>alt_mem_ddrx_mm_st_converter</b> "<b>a0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="soft_asmiblock:19.1:CS_WIDTH=1,IO_MODE=QUAD"
|
|
instancePathKey="q_sys:.:ext_flash:.:soft_asmiblock_instance_name:.:soft_asmiblock_instance_name"
|
|
kind="soft_asmiblock"
|
|
version="19.1"
|
|
name="soft_asmiblock">
|
|
<parameter name="IO_MODE" value="QUAD" />
|
|
<parameter name="CS_WIDTH" value="1" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/soft_asmiblock.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/generic_qspi_controller/soft_asmiblock_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_ext_flash_soft_asmiblock_instance_name"
|
|
as="soft_asmiblock_instance_name" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock"</message>
|
|
<message level="Info" culprit="soft_asmiblock_instance_name"><![CDATA["<b>soft_asmiblock_instance_name</b>" instantiated <b>soft_asmiblock</b> "<b>soft_asmiblock_instance_name</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_asmi_parallel:19.1:CBX_AUTO_BLACKBOX=ALL,DATA_WIDTH=QUAD,DEVICE_FAMILY=Arria V,ENABLE_SIM=true,EPCS_TYPE=EPCQL512,FLASH_RSTPIN=TRUE,INTENDED_DEVICE_FAMILY=,PAGE_SIZE=256,PORT_BULK_ERASE=PORT_UNUSED,PORT_DIE_ERASE=PORT_UNUSED,PORT_EN4B_ADDR=PORT_USED,PORT_EX4B_ADDR=PORT_UNUSED,PORT_FAST_READ=PORT_USED,PORT_ILLEGAL_ERASE=PORT_USED,PORT_ILLEGAL_WRITE=PORT_USED,PORT_RDID_OUT=PORT_USED,PORT_READ_ADDRESS=PORT_UNUSED,PORT_READ_DUMMYCLK=PORT_USED,PORT_READ_RDID=PORT_USED,PORT_READ_SID=PORT_UNUSED,PORT_READ_STATUS=PORT_USED,PORT_SECTOR_ERASE=PORT_USED,PORT_SECTOR_PROTECT=PORT_USED,PORT_SHIFT_BYTES=PORT_USED,PORT_WREN=PORT_USED,PORT_WRITE=PORT_USED,USE_ASMIBLOCK=OFF,USE_EAB=ON,WRITE_DUMMY_CLK=0,gui_bulk_erase=false,gui_die_erase=false,gui_ex4b_addr=false,gui_fast_read=true,gui_page_write=true,gui_read_address=false,gui_read_dummyclk=true,gui_read_rdid=true,gui_read_sid=false,gui_read_status=true,gui_sector_erase=true,gui_sector_protect=true,gui_single_write=false,gui_use_asmiblock=true,gui_use_eab=false,gui_wren=true,gui_write=true"
|
|
instancePathKey="q_sys:.:ext_flash:.:asmi_parallel_instance_name:.:asmi_parallel_instance_name"
|
|
kind="altera_asmi_parallel"
|
|
version="19.1"
|
|
name="q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name">
|
|
<parameter name="PORT_EN4B_ADDR" value="PORT_USED" />
|
|
<parameter name="USE_EAB" value="ON" />
|
|
<parameter name="PORT_READ_SID" value="PORT_UNUSED" />
|
|
<parameter name="gui_read_rdid" value="true" />
|
|
<parameter name="gui_page_write" value="true" />
|
|
<parameter name="DEVICE_FAMILY" value="Arria V" />
|
|
<parameter name="PORT_ILLEGAL_WRITE" value="PORT_USED" />
|
|
<parameter name="FLASH_RSTPIN" value="TRUE" />
|
|
<parameter name="EPCS_TYPE" value="EPCQL512" />
|
|
<parameter name="gui_sector_protect" value="true" />
|
|
<parameter name="PORT_WRITE" value="PORT_USED" />
|
|
<parameter name="gui_fast_read" value="true" />
|
|
<parameter name="PORT_SECTOR_ERASE" value="PORT_USED" />
|
|
<parameter name="DATA_WIDTH" value="QUAD" />
|
|
<parameter name="gui_read_address" value="false" />
|
|
<parameter name="gui_sector_erase" value="true" />
|
|
<parameter name="gui_use_asmiblock" value="true" />
|
|
<parameter name="PORT_DIE_ERASE" value="PORT_UNUSED" />
|
|
<parameter name="PORT_WREN" value="PORT_USED" />
|
|
<parameter name="WRITE_DUMMY_CLK" value="0" />
|
|
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
|
|
<parameter name="gui_read_dummyclk" value="true" />
|
|
<parameter name="gui_single_write" value="false" />
|
|
<parameter name="gui_die_erase" value="false" />
|
|
<parameter name="gui_ex4b_addr" value="false" />
|
|
<parameter name="gui_use_eab" value="false" />
|
|
<parameter name="PORT_READ_DUMMYCLK" value="PORT_USED" />
|
|
<parameter name="gui_write" value="true" />
|
|
<parameter name="PORT_SHIFT_BYTES" value="PORT_USED" />
|
|
<parameter name="PORT_SECTOR_PROTECT" value="PORT_USED" />
|
|
<parameter name="gui_bulk_erase" value="false" />
|
|
<parameter name="PORT_FAST_READ" value="PORT_USED" />
|
|
<parameter name="ENABLE_SIM" value="true" />
|
|
<parameter name="PORT_READ_STATUS" value="PORT_USED" />
|
|
<parameter name="PORT_BULK_ERASE" value="PORT_UNUSED" />
|
|
<parameter name="PORT_RDID_OUT" value="PORT_USED" />
|
|
<parameter name="PORT_READ_RDID" value="PORT_USED" />
|
|
<parameter name="gui_read_status" value="true" />
|
|
<parameter name="PORT_EX4B_ADDR" value="PORT_UNUSED" />
|
|
<parameter name="PAGE_SIZE" value="256" />
|
|
<parameter name="gui_wren" value="true" />
|
|
<parameter name="gui_read_sid" value="false" />
|
|
<parameter name="PORT_ILLEGAL_ERASE" value="PORT_USED" />
|
|
<parameter name="PORT_READ_ADDRESS" value="PORT_UNUSED" />
|
|
<parameter name="INTENDED_DEVICE_FAMILY" value="" />
|
|
<parameter name="USE_ASMIBLOCK" value="OFF" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name.v"
|
|
type="VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_asmi_parallel/altera_asmi_parallel_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_ext_flash_asmi_parallel_instance_name"
|
|
as="asmi_parallel_instance_name" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name"</message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name">generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name</message>
|
|
<message level="Info" culprit="asmi_parallel_instance_name"><![CDATA["<b>asmi_parallel_instance_name</b>" instantiated <b>altera_asmi_parallel</b> "<b>asmi_parallel_instance_name</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="altera_epcq_controller_core:19.1:ADDR_WIDTH=24,ASI_WIDTH=4,ASMI_ADDR_WIDTH=32,CHIP_SELS=1,CS_WIDTH=1,DDASI=1,DEVICE_FAMILY=MAX 10,ENABLE_4BYTE_ADDR=1,FLASH_TYPE=EPCQL512,IO_MODE=QUAD,deviceFeaturesSystemInfo=None"
|
|
instancePathKey="q_sys:.:ext_flash:.:epcq_controller_instance_name:.:epcq_controller_instance_name"
|
|
kind="altera_epcq_controller_core"
|
|
version="19.1"
|
|
name="altera_epcq_controller_arb">
|
|
<parameter name="ASMI_ADDR_WIDTH" value="32" />
|
|
<parameter name="ADDR_WIDTH" value="24" />
|
|
<parameter name="CHIP_SELS" value="1" />
|
|
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
|
<parameter name="IO_MODE" value="QUAD" />
|
|
<parameter name="DDASI" value="1" />
|
|
<parameter name="CS_WIDTH" value="1" />
|
|
<parameter name="deviceFeaturesSystemInfo" value="None" />
|
|
<parameter name="ASI_WIDTH" value="4" />
|
|
<parameter name="ENABLE_4BYTE_ADDR" value="1" />
|
|
<parameter name="FLASH_TYPE" value="EPCQL512" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller_arb.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="TOP_LEVEL_FILE" />
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_epcq_controller.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/altera_epcq_controller/altera_epcq_controller_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_ext_flash_epcq_controller_instance_name"
|
|
as="epcq_controller_instance_name" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb"</message>
|
|
<message level="Info" culprit="epcq_controller_instance_name"><![CDATA["<b>epcq_controller_instance_name</b>" instantiated <b>altera_epcq_controller_core</b> "<b>epcq_controller_instance_name</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="error_adapter:19.1:inBitsPerSymbol=34,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:avalon_st_adapter:.:error_adapter_0"
|
|
kind="error_adapter"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0">
|
|
<parameter name="inErrorWidth" value="0" />
|
|
<parameter name="inUseReady" value="true" />
|
|
<parameter name="inBitsPerSymbol" value="34" />
|
|
<parameter name="inChannelWidth" value="0" />
|
|
<parameter name="inSymbolsPerBeat" value="1" />
|
|
<parameter name="inUseEmptyPort" value="NO" />
|
|
<parameter name="outErrorWidth" value="1" />
|
|
<parameter name="inMaxChannel" value="0" />
|
|
<parameter name="inReadyLatency" value="0" />
|
|
<parameter name="outErrorDescriptor" value="" />
|
|
<parameter name="inUseEmpty" value="false" />
|
|
<parameter name="inErrorDescriptor" value="" />
|
|
<parameter name="inUsePackets" value="false" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1_avalon_st_adapter"
|
|
as="error_adapter_0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"</message>
|
|
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
<entity
|
|
path="submodules/"
|
|
parameterizationKey="error_adapter:19.1:inBitsPerSymbol=18,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1"
|
|
instancePathKey="q_sys:.:mm_interconnect_1:.:avalon_st_adapter_020:.:error_adapter_0"
|
|
kind="error_adapter"
|
|
version="19.1"
|
|
name="q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0">
|
|
<parameter name="inErrorWidth" value="0" />
|
|
<parameter name="inUseReady" value="true" />
|
|
<parameter name="inBitsPerSymbol" value="18" />
|
|
<parameter name="inChannelWidth" value="0" />
|
|
<parameter name="inSymbolsPerBeat" value="1" />
|
|
<parameter name="inUseEmptyPort" value="NO" />
|
|
<parameter name="outErrorWidth" value="1" />
|
|
<parameter name="inMaxChannel" value="0" />
|
|
<parameter name="inReadyLatency" value="0" />
|
|
<parameter name="outErrorDescriptor" value="" />
|
|
<parameter name="inUseEmpty" value="false" />
|
|
<parameter name="inErrorDescriptor" value="" />
|
|
<parameter name="inUsePackets" value="false" />
|
|
<generatedFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0.sv"
|
|
type="SYSTEM_VERILOG"
|
|
attributes="" />
|
|
</generatedFiles>
|
|
<childGeneratedFiles/>
|
|
<sourceFiles>
|
|
<file
|
|
path="/auto/work/qinliqing/intelFPGA_lite/19.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
|
|
</sourceFiles>
|
|
<childSourceFiles/>
|
|
<instantiator
|
|
instantiator="q_sys_mm_interconnect_1_avalon_st_adapter_020"
|
|
as="error_adapter_0" />
|
|
<messages>
|
|
<message level="Debug" culprit="q_sys">queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0"</message>
|
|
<message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_020</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
|
|
</messages>
|
|
</entity>
|
|
</deploy>
|