queue size: 0 starting:q_sys "q_sys" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 24 modules, 97 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform Interconnect is inserted between master sensor_interface.calibration_ram_interface and slave calibration_ram.s2 because the master has read signal 1 bit wide, but the slave is 0 bit wide. Interconnect is inserted between master sensor_interface.calibration_ram_interface and slave calibration_ram.s2 because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide. 3 modules, 5 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform 5 modules, 11 connections]]> Transform: IDPadTransform Transform: DomainTransform Transform merlin_domain_transform not run on matched interfaces sensor_interface.calibration_ram_interface and sensor_interface_calibration_ram_interface_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces sensor_interface_calibration_ram_interface_translator.avalon_universal_master_0 and calibration_ram_s2_translator.avalon_universal_slave_0 Transform merlin_domain_transform not run on matched interfaces calibration_ram_s2_translator.avalon_anti_slave_0 and calibration_ram.s2 Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform 7 modules, 17 connections]]> Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 25 modules, 100 connections]]> Transform: InitialInterconnectTransform 20 modules, 71 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform 49 modules, 166 connections]]> Transform: IDPadTransform Transform: DomainTransform Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces cpu.instruction_master and cpu_instruction_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces msgdma_tx.mm_read and msgdma_tx_mm_read_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces msgdma_rx.mm_write and msgdma_rx_mm_write_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces msgdma_tx.descriptor_read_master and msgdma_tx_descriptor_read_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces msgdma_rx.descriptor_read_master and msgdma_rx_descriptor_read_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces msgdma_tx.descriptor_write_master and msgdma_tx_descriptor_write_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces msgdma_rx.descriptor_write_master and msgdma_rx_descriptor_write_master_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces ddr3_ram_avl_translator.avalon_anti_slave_0 and ddr3_ram.avl Transform merlin_domain_transform not run on matched interfaces ext_flash_avl_csr_translator.avalon_anti_slave_0 and ext_flash.avl_csr Transform merlin_domain_transform not run on matched interfaces ext_flash_avl_mem_translator.avalon_anti_slave_0 and ext_flash.avl_mem Transform merlin_domain_transform not run on matched interfaces eth_tse_control_port_translator.avalon_anti_slave_0 and eth_tse.control_port Transform merlin_domain_transform not run on matched interfaces sysid_control_slave_translator.avalon_anti_slave_0 and sysid.control_slave Transform merlin_domain_transform not run on matched interfaces msgdma_tx_csr_translator.avalon_anti_slave_0 and msgdma_tx.csr Transform merlin_domain_transform not run on matched interfaces msgdma_rx_csr_translator.avalon_anti_slave_0 and msgdma_rx.csr Transform merlin_domain_transform not run on matched interfaces onchip_flash_csr_translator.avalon_anti_slave_0 and onchip_flash.csr Transform merlin_domain_transform not run on matched interfaces udp_generator_csr_translator.avalon_anti_slave_0 and udp_generator.csr Transform merlin_domain_transform not run on matched interfaces sensor_interface_csr_translator.avalon_anti_slave_0 and sensor_interface.csr Transform merlin_domain_transform not run on matched interfaces onchip_flash_data_translator.avalon_anti_slave_0 and onchip_flash.data Transform merlin_domain_transform not run on matched interfaces cpu_debug_mem_slave_translator.avalon_anti_slave_0 and cpu.debug_mem_slave Transform merlin_domain_transform not run on matched interfaces msgdma_tx_prefetcher_csr_translator.avalon_anti_slave_0 and msgdma_tx.prefetcher_csr Transform merlin_domain_transform not run on matched interfaces msgdma_rx_prefetcher_csr_translator.avalon_anti_slave_0 and msgdma_rx.prefetcher_csr Transform merlin_domain_transform not run on matched interfaces descriptor_memory_s1_translator.avalon_anti_slave_0 and descriptor_memory.s1 Transform merlin_domain_transform not run on matched interfaces sys_clk_timer_s1_translator.avalon_anti_slave_0 and sys_clk_timer.s1 Transform merlin_domain_transform not run on matched interfaces output_pio_s1_translator.avalon_anti_slave_0 and output_pio.s1 Transform merlin_domain_transform not run on matched interfaces button_pio_s1_translator.avalon_anti_slave_0 and button_pio.s1 Transform merlin_domain_transform not run on matched interfaces debug_uart_s1_translator.avalon_anti_slave_0 and debug_uart.s1 Transform merlin_domain_transform not run on matched interfaces frame_timer_s1_translator.avalon_anti_slave_0 and frame_timer.s1 Transform merlin_domain_transform not run on matched interfaces calibration_ram_s1_translator.avalon_anti_slave_0 and calibration_ram.s1 103 modules, 479 connections]]> Transform: RouterTransform 132 modules, 574 connections]]> Transform: TrafficLimiterTransform 134 modules, 582 connections]]> Transform: BurstTransform 136 modules, 589 connections]]> Transform: TreeTransform Transform: NetworkToSwitchTransform 193 modules, 717 connections]]> Transform: WidthTransform 195 modules, 723 connections]]> Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0 Inserting clock-crossing logic between cmd_demux.src1 and cmd_mux_001.sink0 Inserting clock-crossing logic between cmd_demux.src2 and cmd_mux_002.sink0 Inserting clock-crossing logic between cmd_demux_001.src0 and cmd_mux.sink1 Inserting clock-crossing logic between cmd_demux_001.src1 and cmd_mux_002.sink1 Inserting clock-crossing logic between cmd_demux_002.src0 and cmd_mux.sink2 Inserting clock-crossing logic between cmd_demux_003.src0 and cmd_mux.sink3 Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0 Inserting clock-crossing logic between rsp_demux.src1 and rsp_mux_001.sink0 Inserting clock-crossing logic between rsp_demux.src2 and rsp_mux_002.sink0 Inserting clock-crossing logic between rsp_demux.src3 and rsp_mux_003.sink0 Inserting clock-crossing logic between rsp_demux_001.src0 and rsp_mux.sink1 Inserting clock-crossing logic between rsp_demux_002.src0 and rsp_mux.sink2 Inserting clock-crossing logic between rsp_demux_002.src1 and rsp_mux_001.sink1 209 modules, 807 connections]]> Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform 209 modules, 809 connections]]> Transform: InsertClockAndResetBridgesTransform 217 modules, 1037 connections]]> Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 26 modules, 110 connections]]> 26 modules, 110 connections]]> Transform: InterruptMapperTransform 27 modules, 113 connections]]> Transform: InterruptSyncTransform 28 modules, 119 connections]]> Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.004s Timing: COM:3/0.017s/0.022s Inserting timing_adapter: timing_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.004s Timing: COM:3/0.012s/0.021s 30 modules, 126 connections]]> Transform: ResetAdaptation 39 modules, 154 connections]]> q_sys" reuses altpll "submodules/q_sys_altpll_shift"]]> q_sys" reuses altera_avalon_pio "submodules/q_sys_button_pio"]]> q_sys" reuses altera_avalon_onchip_memory2 "submodules/q_sys_calibration_ram"]]> q_sys" reuses channel_adapter "submodules/q_sys_channel_adapter_0"]]> q_sys" reuses altera_nios2_gen2 "submodules/q_sys_cpu"]]> q_sys" reuses altera_mem_if_ddr3_emif "submodules/q_sys_ddr3_ram"]]> q_sys" reuses altera_avalon_uart "submodules/q_sys_debug_uart"]]> q_sys" reuses altera_avalon_onchip_memory2 "submodules/q_sys_descriptor_memory"]]> q_sys" reuses altpll "submodules/q_sys_enet_pll"]]> q_sys" reuses altera_eth_tse "submodules/q_sys_eth_tse"]]> q_sys" reuses altera_generic_quad_spi_controller "submodules/q_sys_ext_flash"]]> q_sys" reuses altera_avalon_timer "submodules/q_sys_frame_timer"]]> q_sys" reuses altera_msgdma "submodules/q_sys_msgdma_rx"]]> q_sys" reuses altera_msgdma "submodules/q_sys_msgdma_tx"]]> q_sys" reuses altera_onchip_flash "submodules/altera_onchip_flash"]]> q_sys" reuses altera_avalon_pio "submodules/q_sys_output_pio"]]> q_sys" reuses sensor_recon "submodules/sensor_algo"]]> q_sys" reuses altera_avalon_timer "submodules/q_sys_sys_clk_timer"]]> q_sys" reuses altera_avalon_sysid_qsys "submodules/q_sys_sysid"]]> q_sys" reuses multiplexer "submodules/q_sys_tx_multiplexer"]]> q_sys" reuses udp_generator "submodules/udp_generator"]]> q_sys" reuses altera_mm_interconnect "submodules/q_sys_mm_interconnect_0"]]> q_sys" reuses altera_mm_interconnect "submodules/q_sys_mm_interconnect_1"]]> q_sys" reuses altera_irq_mapper "submodules/q_sys_irq_mapper"]]> q_sys" reuses altera_irq_clock_crosser "submodules/altera_irq_clock_crosser"]]> q_sys" reuses altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter"]]> q_sys" reuses altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter_001"]]> q_sys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> q_sys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> q_sys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> q_sys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> q_sys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> q_sys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> q_sys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> queue size: 33 starting:altpll "submodules/q_sys_altpll_shift" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --source=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0003_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on Command took 1.307s q_sys" instantiated altpll "altpll_shift"]]> queue size: 32 starting:altera_avalon_pio "submodules/q_sys_button_pio" Starting RTL generation for module 'q_sys_button_pio' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_button_pio --dir=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen//q_sys_button_pio_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_button_pio' q_sys" instantiated altera_avalon_pio "button_pio"]]> queue size: 31 starting:altera_avalon_onchip_memory2 "submodules/q_sys_calibration_ram" Starting RTL generation for module 'q_sys_calibration_ram' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_calibration_ram --dir=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen//q_sys_calibration_ram_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_calibration_ram' q_sys" instantiated altera_avalon_onchip_memory2 "calibration_ram"]]> queue size: 30 starting:channel_adapter "submodules/q_sys_channel_adapter_0" q_sys" instantiated channel_adapter "channel_adapter_0"]]> queue size: 29 starting:altera_nios2_gen2 "submodules/q_sys_cpu" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation cpu" reuses altera_nios2_gen2_unit "submodules/q_sys_cpu_cpu"]]> q_sys" instantiated altera_nios2_gen2 "cpu"]]> queue size: 233 starting:altera_nios2_gen2_unit "submodules/q_sys_cpu_cpu" Starting RTL generation for module 'q_sys_cpu_cpu' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=q_sys_cpu_cpu --dir=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen/ --quartus_bindir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/ --verilog --config=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen//q_sys_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] # 2024.10.11 10:10:22 (*) Starting Nios II generation # 2024.10.11 10:10:22 (*) Elaborating CPU configuration settings # 2024.10.11 10:10:22 (*) Creating all objects for CPU # 2024.10.11 10:10:22 (*) Testbench # 2024.10.11 10:10:22 (*) Instruction decoding # 2024.10.11 10:10:22 (*) Instruction fields # 2024.10.11 10:10:22 (*) Instruction decodes # 2024.10.11 10:10:23 (*) Signals for RTL simulation waveforms # 2024.10.11 10:10:23 (*) Instruction controls # 2024.10.11 10:10:23 (*) Pipeline frontend # 2024.10.11 10:10:23 (*) Pipeline backend # 2024.10.11 10:10:24 (*) Generating RTL from CPU objects # 2024.10.11 10:10:24 (*) Creating plain-text RTL # 2024.10.11 10:10:24 (*) Done Nios II generation Done RTL generation for module 'q_sys_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 29 starting:altera_mem_if_ddr3_emif "submodules/q_sys_ddr3_ram" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 14 modules, 31 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation ddr3_ram" reuses altera_mem_if_ddr3_pll "submodules/q_sys_ddr3_ram_pll0"]]> ddr3_ram" reuses altera_mem_if_ddr3_phy_core "submodules/q_sys_ddr3_ram_p0"]]> ddr3_ram" reuses altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx"]]> ddr3_ram" reuses altera_mem_if_ddr3_qseq "submodules/q_sys_ddr3_ram_s0"]]> ddr3_ram" reuses altera_mem_if_nextgen_ddr3_controller "submodules/q_sys_ddr3_ram_c0"]]> q_sys" instantiated altera_mem_if_ddr3_emif "ddr3_ram"]]> queue size: 232 starting:altera_mem_if_ddr3_pll "submodules/q_sys_ddr3_ram_pll0" ddr3_ram" instantiated altera_mem_if_ddr3_pll "pll0"]]> queue size: 231 starting:altera_mem_if_ddr3_phy_core "submodules/q_sys_ddr3_ram_p0" Generating clock pair generator Generating altgpio ***************************** Remember to run the q_sys_ddr3_ram_p0_pin_assignments.tcl script after running Synthesis and before Fitting. ***************************** ddr3_ram" instantiated altera_mem_if_ddr3_phy_core "p0"]]> queue size: 230 starting:altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx" ddr3_ram" instantiated altera_mem_if_ddr3_afi_mux "m0"]]> queue size: 229 starting:altera_mem_if_ddr3_qseq "submodules/q_sys_ddr3_ram_s0" Generating Qsys sequencer system QSYS sequencer system generated successfully ddr3_ram" instantiated altera_mem_if_ddr3_qseq "s0"]]> queue size: 228 starting:altera_mem_if_nextgen_ddr3_controller "submodules/q_sys_ddr3_ram_c0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 5 modules, 8 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation c0" reuses altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core"]]> c0" reuses alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter"]]> ddr3_ram" instantiated altera_mem_if_nextgen_ddr3_controller "c0"]]> queue size: 6 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core" c0" instantiated altera_mem_if_nextgen_ddr3_controller_core "ng0"]]> queue size: 5 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" c0" instantiated alt_mem_ddrx_mm_st_converter "a0"]]> queue size: 33 starting:altera_avalon_uart "submodules/q_sys_debug_uart" Starting RTL generation for module 'q_sys_debug_uart' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=q_sys_debug_uart --dir=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen//q_sys_debug_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_debug_uart' q_sys" instantiated altera_avalon_uart "debug_uart"]]> queue size: 32 starting:altera_avalon_onchip_memory2 "submodules/q_sys_descriptor_memory" Starting RTL generation for module 'q_sys_descriptor_memory' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_descriptor_memory --dir=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen//q_sys_descriptor_memory_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_descriptor_memory' q_sys" instantiated altera_avalon_onchip_memory2 "descriptor_memory"]]> queue size: 31 starting:altpll "submodules/q_sys_enet_pll" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --source=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0010_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on Command took 1.135s q_sys" instantiated altpll "enet_pll"]]> queue size: 30 starting:altera_eth_tse "submodules/q_sys_eth_tse" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 5 modules, 14 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation eth_tse" reuses altera_eth_tse_mac "submodules/altera_eth_tse_mac"]]> eth_tse" reuses altera_gpio_lite "submodules/altera_gpio_lite"]]> eth_tse" reuses altera_gpio_lite "submodules/altera_gpio_lite"]]> eth_tse" reuses altera_gpio_lite "submodules/altera_gpio_lite"]]> eth_tse" reuses altera_gpio_lite "submodules/altera_gpio_lite"]]> q_sys" instantiated altera_eth_tse "eth_tse"]]> queue size: 229 starting:altera_eth_tse_mac "submodules/altera_eth_tse_mac" eth_tse" instantiated altera_eth_tse_mac "i_tse_mac"]]> queue size: 228 starting:altera_gpio_lite "submodules/altera_gpio_lite" eth_tse" instantiated altera_gpio_lite "rgmii_in4_0"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv]]> queue size: 34 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash" "Generating: soft_asmiblock_instance_name" ext_flash" reuses altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_soft_asmiblock_instance_name"]]> "Generating: asmi_parallel_instance_name" ext_flash" reuses altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_asmi_parallel_instance_name"]]> "Generating: epcq_controller_instance_name" ext_flash" reuses altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_epcq_controller_instance_name"]]> q_sys" instantiated altera_generic_quad_spi_controller "ext_flash"]]> queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_soft_asmiblock_instance_name" soft_asmiblock_instance_name" reuses soft_asmiblock "submodules/soft_asmiblock"]]> ext_flash" instantiated altera_generic_quad_spi_controller "soft_asmiblock_instance_name"]]> queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock" soft_asmiblock_instance_name" instantiated soft_asmiblock "soft_asmiblock_instance_name"]]> queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_asmi_parallel_instance_name" asmi_parallel_instance_name" reuses altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name"]]> ext_flash" instantiated altera_generic_quad_spi_controller "asmi_parallel_instance_name"]]> queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name asmi_parallel_instance_name" instantiated altera_asmi_parallel "asmi_parallel_instance_name"]]> queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_epcq_controller_instance_name" epcq_controller_instance_name" reuses altera_epcq_controller_core "submodules/altera_epcq_controller_arb"]]> ext_flash" instantiated altera_generic_quad_spi_controller "epcq_controller_instance_name"]]> queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb" epcq_controller_instance_name" instantiated altera_epcq_controller_core "epcq_controller_instance_name"]]> queue size: 36 starting:altera_avalon_timer "submodules/q_sys_frame_timer" Starting RTL generation for module 'q_sys_frame_timer' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_frame_timer --dir=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen//q_sys_frame_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_frame_timer' q_sys" instantiated altera_avalon_timer "frame_timer"]]> queue size: 35 starting:altera_msgdma "submodules/q_sys_msgdma_rx" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 5 modules, 11 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation msgdma_rx" reuses modular_sgdma_dispatcher "submodules/dispatcher"]]> msgdma_rx" reuses altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"]]> msgdma_rx" reuses dma_write_master "submodules/write_master"]]> q_sys" instantiated altera_msgdma "msgdma_rx"]]> queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher" msgdma_rx" instantiated modular_sgdma_dispatcher "dispatcher_internal"]]> queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher" msgdma_rx" instantiated altera_msgdma_prefetcher "prefetcher_internal"]]> queue size: 222 starting:dma_write_master "submodules/write_master" msgdma_rx" instantiated dma_write_master "write_mstr_internal"]]> queue size: 37 starting:altera_msgdma "submodules/q_sys_msgdma_tx" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 5 modules, 11 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation msgdma_tx" reuses modular_sgdma_dispatcher "submodules/dispatcher"]]> msgdma_tx" reuses altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"]]> msgdma_tx" reuses dma_read_master "submodules/read_master"]]> q_sys" instantiated altera_msgdma "msgdma_tx"]]> queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher" msgdma_rx" instantiated modular_sgdma_dispatcher "dispatcher_internal"]]> queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher" msgdma_rx" instantiated altera_msgdma_prefetcher "prefetcher_internal"]]> queue size: 219 starting:dma_read_master "submodules/read_master" msgdma_tx" instantiated dma_read_master "read_mstr_internal"]]> queue size: 39 starting:altera_onchip_flash "submodules/altera_onchip_flash" Generating top-level entity altera_onchip_flash q_sys" instantiated altera_onchip_flash "onchip_flash"]]> queue size: 38 starting:altera_avalon_pio "submodules/q_sys_output_pio" Starting RTL generation for module 'q_sys_output_pio' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_output_pio --dir=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen//q_sys_output_pio_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_output_pio' q_sys" instantiated altera_avalon_pio "output_pio"]]> queue size: 37 starting:sensor_recon "submodules/sensor_algo" q_sys" instantiated sensor_recon "sensor_interface"]]> queue size: 36 starting:altera_avalon_timer "submodules/q_sys_sys_clk_timer" Starting RTL generation for module 'q_sys_sys_clk_timer' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_sys_clk_timer --dir=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen//q_sys_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_sys_clk_timer' q_sys" instantiated altera_avalon_timer "sys_clk_timer"]]> queue size: 35 starting:altera_avalon_sysid_qsys "submodules/q_sys_sysid" q_sys" instantiated altera_avalon_sysid_qsys "sysid"]]> queue size: 34 starting:multiplexer "submodules/q_sys_tx_multiplexer" q_sys" instantiated multiplexer "tx_multiplexer"]]> queue size: 33 starting:udp_generator "submodules/udp_generator" q_sys" instantiated udp_generator "udp_generator"]]> queue size: 32 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 4 modules, 6 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 4 modules, 6 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> q_sys" instantiated altera_mm_interconnect "mm_interconnect_0"]]> queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "sensor_interface_calibration_ram_interface_translator"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv]]> queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "calibration_ram_s2_translator"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv]]> queue size: 33 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_1" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 197 modules, 679 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.007s/0.008s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.005s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.007s/0.009s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.005s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.005s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.004s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.004s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.020s/0.048s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.005s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.004s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.002s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.005s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.006s 218 modules, 742 connections]]> Transform: ResetAdaptation mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_001"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_008"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_022"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_028"]]> mm_interconnect_1" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> mm_interconnect_1" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> mm_interconnect_1" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"]]> mm_interconnect_1" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_001"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_014"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_001"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_014"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020"]]> q_sys" instantiated altera_mm_interconnect "mm_interconnect_1"]]> queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "sensor_interface_calibration_ram_interface_translator"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv]]> queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "calibration_ram_s2_translator"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv]]> queue size: 187 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_1" instantiated altera_merlin_master_agent "cpu_data_master_agent"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv]]> queue size: 179 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_1" instantiated altera_merlin_slave_agent "ddr3_ram_avl_agent"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 178 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_1" instantiated altera_avalon_sc_fifo "ddr3_ram_avl_agent_rsp_fifo"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 134 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router" mm_interconnect_1" instantiated altera_merlin_router "router"]]> queue size: 133 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_001" mm_interconnect_1" instantiated altera_merlin_router "router_001"]]> queue size: 132 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002" mm_interconnect_1" instantiated altera_merlin_router "router_002"]]> queue size: 130 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004" mm_interconnect_1" instantiated altera_merlin_router "router_004"]]> queue size: 126 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_008" mm_interconnect_1" instantiated altera_merlin_router "router_008"]]> queue size: 125 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009" mm_interconnect_1" instantiated altera_merlin_router "router_009"]]> queue size: 124 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010" mm_interconnect_1" instantiated altera_merlin_router "router_010"]]> queue size: 112 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_022" mm_interconnect_1" instantiated altera_merlin_router "router_022"]]> queue size: 106 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_028" mm_interconnect_1" instantiated altera_merlin_router "router_028"]]> queue size: 105 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" mm_interconnect_1" instantiated altera_merlin_traffic_limiter "cpu_data_master_limiter"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 103 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" mm_interconnect_1" instantiated altera_merlin_burst_adapter "ext_flash_avl_mem_burst_adapter"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> queue size: 101 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 100 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_001" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> queue size: 99 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux_002"]]> queue size: 93 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 92 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_001"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 91 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_002"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 79 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_014" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_014"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 72 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 71 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_001" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_001"]]> queue size: 70 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_002" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_002"]]> queue size: 62 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_010"]]> queue size: 58 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_014" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_014"]]> queue size: 51 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 50 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_001" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 49 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux_002"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 43 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" mm_interconnect_1" instantiated altera_merlin_width_adapter "calibration_ram_s1_rsp_width_adapter"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 41 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" mm_interconnect_1" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v]]> queue size: 27 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 8 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter_020" reuses error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0"]]> mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter_020"]]> queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" avalon_st_adapter_020" instantiated error_adapter "error_adapter_0"]]> queue size: 242 starting:altera_irq_mapper "submodules/q_sys_irq_mapper" q_sys" instantiated altera_irq_mapper "irq_mapper"]]> queue size: 241 starting:altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" q_sys" instantiated altera_irq_clock_crosser "irq_synchronizer"]]> queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/q_sys_avalon_st_adapter_error_adapter_0"]]> q_sys" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 8 starting:error_adapter "submodules/q_sys_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter_001" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter_001" reuses timing_adapter "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0"]]> q_sys" instantiated altera_avalon_st_adapter "avalon_st_adapter_001"]]> queue size: 7 starting:timing_adapter "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0" avalon_st_adapter_001" instantiated timing_adapter "timing_adapter_0"]]> queue size: 240 starting:altera_reset_controller "submodules/altera_reset_controller" q_sys" instantiated altera_reset_controller "rst_controller"]]> queue size: 33 starting:altpll "submodules/q_sys_altpll_shift" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --source=/tmp/alt0007_504881647740679586.dir/0002_sopcgen/q_sys_altpll_shift.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0003_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on Command took 1.307s q_sys" instantiated altpll "altpll_shift"]]> queue size: 32 starting:altera_avalon_pio "submodules/q_sys_button_pio" Starting RTL generation for module 'q_sys_button_pio' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_button_pio --dir=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0004_button_pio_gen//q_sys_button_pio_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_button_pio' q_sys" instantiated altera_avalon_pio "button_pio"]]> queue size: 31 starting:altera_avalon_onchip_memory2 "submodules/q_sys_calibration_ram" Starting RTL generation for module 'q_sys_calibration_ram' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_calibration_ram --dir=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0005_calibration_ram_gen//q_sys_calibration_ram_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_calibration_ram' q_sys" instantiated altera_avalon_onchip_memory2 "calibration_ram"]]> queue size: 30 starting:channel_adapter "submodules/q_sys_channel_adapter_0" q_sys" instantiated channel_adapter "channel_adapter_0"]]> queue size: 29 starting:altera_nios2_gen2 "submodules/q_sys_cpu" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation cpu" reuses altera_nios2_gen2_unit "submodules/q_sys_cpu_cpu"]]> q_sys" instantiated altera_nios2_gen2 "cpu"]]> queue size: 233 starting:altera_nios2_gen2_unit "submodules/q_sys_cpu_cpu" Starting RTL generation for module 'q_sys_cpu_cpu' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=q_sys_cpu_cpu --dir=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen/ --quartus_bindir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/ --verilog --config=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen//q_sys_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] # 2024.10.11 10:10:22 (*) Starting Nios II generation # 2024.10.11 10:10:22 (*) Elaborating CPU configuration settings # 2024.10.11 10:10:22 (*) Creating all objects for CPU # 2024.10.11 10:10:22 (*) Testbench # 2024.10.11 10:10:22 (*) Instruction decoding # 2024.10.11 10:10:22 (*) Instruction fields # 2024.10.11 10:10:22 (*) Instruction decodes # 2024.10.11 10:10:23 (*) Signals for RTL simulation waveforms # 2024.10.11 10:10:23 (*) Instruction controls # 2024.10.11 10:10:23 (*) Pipeline frontend # 2024.10.11 10:10:23 (*) Pipeline backend # 2024.10.11 10:10:24 (*) Generating RTL from CPU objects # 2024.10.11 10:10:24 (*) Creating plain-text RTL # 2024.10.11 10:10:24 (*) Done Nios II generation Done RTL generation for module 'q_sys_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 33 starting:altera_avalon_uart "submodules/q_sys_debug_uart" Starting RTL generation for module 'q_sys_debug_uart' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=q_sys_debug_uart --dir=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0007_debug_uart_gen//q_sys_debug_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_debug_uart' q_sys" instantiated altera_avalon_uart "debug_uart"]]> queue size: 32 starting:altera_avalon_onchip_memory2 "submodules/q_sys_descriptor_memory" Starting RTL generation for module 'q_sys_descriptor_memory' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_descriptor_memory --dir=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0008_descriptor_memory_gen//q_sys_descriptor_memory_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_descriptor_memory' q_sys" instantiated altera_avalon_onchip_memory2 "descriptor_memory"]]> queue size: 31 starting:altpll "submodules/q_sys_enet_pll" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files Command: /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --source=/tmp/alt0007_504881647740679586.dir/0009_sopcgen/q_sys_enet_pll.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt0007_504881647740679586.dir/0010_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on Command took 1.135s q_sys" instantiated altpll "enet_pll"]]> queue size: 30 starting:altera_eth_tse "submodules/q_sys_eth_tse" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 5 modules, 14 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation eth_tse" reuses altera_eth_tse_mac "submodules/altera_eth_tse_mac"]]> eth_tse" reuses altera_gpio_lite "submodules/altera_gpio_lite"]]> eth_tse" reuses altera_gpio_lite "submodules/altera_gpio_lite"]]> eth_tse" reuses altera_gpio_lite "submodules/altera_gpio_lite"]]> eth_tse" reuses altera_gpio_lite "submodules/altera_gpio_lite"]]> q_sys" instantiated altera_eth_tse "eth_tse"]]> queue size: 229 starting:altera_eth_tse_mac "submodules/altera_eth_tse_mac" eth_tse" instantiated altera_eth_tse_mac "i_tse_mac"]]> queue size: 228 starting:altera_gpio_lite "submodules/altera_gpio_lite" eth_tse" instantiated altera_gpio_lite "rgmii_in4_0"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv]]> queue size: 34 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash" "Generating: soft_asmiblock_instance_name" ext_flash" reuses altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_soft_asmiblock_instance_name"]]> "Generating: asmi_parallel_instance_name" ext_flash" reuses altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_asmi_parallel_instance_name"]]> "Generating: epcq_controller_instance_name" ext_flash" reuses altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_epcq_controller_instance_name"]]> q_sys" instantiated altera_generic_quad_spi_controller "ext_flash"]]> queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_soft_asmiblock_instance_name" soft_asmiblock_instance_name" reuses soft_asmiblock "submodules/soft_asmiblock"]]> ext_flash" instantiated altera_generic_quad_spi_controller "soft_asmiblock_instance_name"]]> queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock" soft_asmiblock_instance_name" instantiated soft_asmiblock "soft_asmiblock_instance_name"]]> queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_asmi_parallel_instance_name" asmi_parallel_instance_name" reuses altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name"]]> ext_flash" instantiated altera_generic_quad_spi_controller "asmi_parallel_instance_name"]]> queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name asmi_parallel_instance_name" instantiated altera_asmi_parallel "asmi_parallel_instance_name"]]> queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_epcq_controller_instance_name" epcq_controller_instance_name" reuses altera_epcq_controller_core "submodules/altera_epcq_controller_arb"]]> ext_flash" instantiated altera_generic_quad_spi_controller "epcq_controller_instance_name"]]> queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb" epcq_controller_instance_name" instantiated altera_epcq_controller_core "epcq_controller_instance_name"]]> queue size: 36 starting:altera_avalon_timer "submodules/q_sys_frame_timer" Starting RTL generation for module 'q_sys_frame_timer' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_frame_timer --dir=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0012_frame_timer_gen//q_sys_frame_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_frame_timer' q_sys" instantiated altera_avalon_timer "frame_timer"]]> queue size: 35 starting:altera_msgdma "submodules/q_sys_msgdma_rx" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 5 modules, 11 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation msgdma_rx" reuses modular_sgdma_dispatcher "submodules/dispatcher"]]> msgdma_rx" reuses altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"]]> msgdma_rx" reuses dma_write_master "submodules/write_master"]]> q_sys" instantiated altera_msgdma "msgdma_rx"]]> queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher" msgdma_rx" instantiated modular_sgdma_dispatcher "dispatcher_internal"]]> queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher" msgdma_rx" instantiated altera_msgdma_prefetcher "prefetcher_internal"]]> queue size: 222 starting:dma_write_master "submodules/write_master" msgdma_rx" instantiated dma_write_master "write_mstr_internal"]]> queue size: 37 starting:altera_msgdma "submodules/q_sys_msgdma_tx" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 5 modules, 11 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation msgdma_tx" reuses modular_sgdma_dispatcher "submodules/dispatcher"]]> msgdma_tx" reuses altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher"]]> msgdma_tx" reuses dma_read_master "submodules/read_master"]]> q_sys" instantiated altera_msgdma "msgdma_tx"]]> queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher" msgdma_rx" instantiated modular_sgdma_dispatcher "dispatcher_internal"]]> queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher" msgdma_rx" instantiated altera_msgdma_prefetcher "prefetcher_internal"]]> queue size: 219 starting:dma_read_master "submodules/read_master" msgdma_tx" instantiated dma_read_master "read_mstr_internal"]]> queue size: 39 starting:altera_onchip_flash "submodules/altera_onchip_flash" Generating top-level entity altera_onchip_flash q_sys" instantiated altera_onchip_flash "onchip_flash"]]> queue size: 38 starting:altera_avalon_pio "submodules/q_sys_output_pio" Starting RTL generation for module 'q_sys_output_pio' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_output_pio --dir=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0014_output_pio_gen//q_sys_output_pio_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_output_pio' q_sys" instantiated altera_avalon_pio "output_pio"]]> queue size: 37 starting:sensor_recon "submodules/sensor_algo" q_sys" instantiated sensor_recon "sensor_interface"]]> queue size: 36 starting:altera_avalon_timer "submodules/q_sys_sys_clk_timer" Starting RTL generation for module 'q_sys_sys_clk_timer' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=q_sys_sys_clk_timer --dir=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt0007_504881647740679586.dir/0016_sys_clk_timer_gen//q_sys_sys_clk_timer_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'q_sys_sys_clk_timer' q_sys" instantiated altera_avalon_timer "sys_clk_timer"]]> queue size: 35 starting:altera_avalon_sysid_qsys "submodules/q_sys_sysid" q_sys" instantiated altera_avalon_sysid_qsys "sysid"]]> queue size: 34 starting:multiplexer "submodules/q_sys_tx_multiplexer" q_sys" instantiated multiplexer "tx_multiplexer"]]> queue size: 33 starting:udp_generator "submodules/udp_generator" q_sys" instantiated udp_generator "udp_generator"]]> queue size: 32 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 4 modules, 6 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 4 modules, 6 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> q_sys" instantiated altera_mm_interconnect "mm_interconnect_0"]]> queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "sensor_interface_calibration_ram_interface_translator"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv]]> queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "calibration_ram_s2_translator"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv]]> queue size: 33 starting:altera_mm_interconnect "submodules/q_sys_mm_interconnect_1" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 197 modules, 679 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 197 modules, 679 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.007s/0.008s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.005s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.007s/0.009s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.005s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.005s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.004s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.004s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.001s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.020s/0.048s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.005s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.004s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.002s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.005s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.007s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.000s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.006s Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.000s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.003s Timing: COM:3/0.006s/0.006s 218 modules, 742 connections]]> Transform: ResetAdaptation mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_001"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_008"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_022"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009"]]> mm_interconnect_1" reuses altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_028"]]> mm_interconnect_1" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> mm_interconnect_1" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> mm_interconnect_1" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"]]> mm_interconnect_1" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_001"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_014"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_001"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_014"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_001"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002"]]> mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter"]]> mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020"]]> q_sys" instantiated altera_mm_interconnect "mm_interconnect_1"]]> queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "sensor_interface_calibration_ram_interface_translator"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv]]> queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "calibration_ram_s2_translator"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv]]> queue size: 187 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_1" instantiated altera_merlin_master_agent "cpu_data_master_agent"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv]]> queue size: 179 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_1" instantiated altera_merlin_slave_agent "ddr3_ram_avl_agent"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 178 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_1" instantiated altera_avalon_sc_fifo "ddr3_ram_avl_agent_rsp_fifo"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 134 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router" mm_interconnect_1" instantiated altera_merlin_router "router"]]> queue size: 133 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_001" mm_interconnect_1" instantiated altera_merlin_router "router_001"]]> queue size: 132 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002" mm_interconnect_1" instantiated altera_merlin_router "router_002"]]> queue size: 130 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004" mm_interconnect_1" instantiated altera_merlin_router "router_004"]]> queue size: 126 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_008" mm_interconnect_1" instantiated altera_merlin_router "router_008"]]> queue size: 125 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009" mm_interconnect_1" instantiated altera_merlin_router "router_009"]]> queue size: 124 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010" mm_interconnect_1" instantiated altera_merlin_router "router_010"]]> queue size: 112 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_022" mm_interconnect_1" instantiated altera_merlin_router "router_022"]]> queue size: 106 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_028" mm_interconnect_1" instantiated altera_merlin_router "router_028"]]> queue size: 105 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" mm_interconnect_1" instantiated altera_merlin_traffic_limiter "cpu_data_master_limiter"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 103 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" mm_interconnect_1" instantiated altera_merlin_burst_adapter "ext_flash_avl_mem_burst_adapter"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> queue size: 101 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 100 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_001" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> queue size: 99 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux_002"]]> queue size: 93 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 92 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_001"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 91 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_002"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 79 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_014" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_014"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 72 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 71 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_001" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_001"]]> queue size: 70 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_002" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_002"]]> queue size: 62 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_010"]]> queue size: 58 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_014" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_014"]]> queue size: 51 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 50 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_001" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 49 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux_002"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 43 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" mm_interconnect_1" instantiated altera_merlin_width_adapter "calibration_ram_s1_rsp_width_adapter"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 41 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" mm_interconnect_1" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v]]> queue size: 27 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 8 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter_020" reuses error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0"]]> mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter_020"]]> queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" avalon_st_adapter_020" instantiated error_adapter "error_adapter_0"]]> queue size: 242 starting:altera_irq_mapper "submodules/q_sys_irq_mapper" q_sys" instantiated altera_irq_mapper "irq_mapper"]]> queue size: 241 starting:altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" q_sys" instantiated altera_irq_clock_crosser "irq_synchronizer"]]> queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/q_sys_avalon_st_adapter_error_adapter_0"]]> q_sys" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 8 starting:error_adapter "submodules/q_sys_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 240 starting:altera_avalon_st_adapter "submodules/q_sys_avalon_st_adapter_001" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter_001" reuses timing_adapter "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0"]]> q_sys" instantiated altera_avalon_st_adapter "avalon_st_adapter_001"]]> queue size: 7 starting:timing_adapter "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0" avalon_st_adapter_001" instantiated timing_adapter "timing_adapter_0"]]> queue size: 240 starting:altera_reset_controller "submodules/altera_reset_controller" q_sys" instantiated altera_reset_controller "rst_controller"]]> queue size: 233 starting:altera_nios2_gen2_unit "submodules/q_sys_cpu_cpu" Starting RTL generation for module 'q_sys_cpu_cpu' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64//perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=q_sys_cpu_cpu --dir=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen/ --quartus_bindir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/ --verilog --config=/tmp/alt0007_504881647740679586.dir/0023_cpu_gen//q_sys_cpu_cpu_processor_configuration.pl --do_build_sim=0 ] # 2024.10.11 10:10:22 (*) Starting Nios II generation # 2024.10.11 10:10:22 (*) Elaborating CPU configuration settings # 2024.10.11 10:10:22 (*) Creating all objects for CPU # 2024.10.11 10:10:22 (*) Testbench # 2024.10.11 10:10:22 (*) Instruction decoding # 2024.10.11 10:10:22 (*) Instruction fields # 2024.10.11 10:10:22 (*) Instruction decodes # 2024.10.11 10:10:23 (*) Signals for RTL simulation waveforms # 2024.10.11 10:10:23 (*) Instruction controls # 2024.10.11 10:10:23 (*) Pipeline frontend # 2024.10.11 10:10:23 (*) Pipeline backend # 2024.10.11 10:10:24 (*) Generating RTL from CPU objects # 2024.10.11 10:10:24 (*) Creating plain-text RTL # 2024.10.11 10:10:24 (*) Done Nios II generation Done RTL generation for module 'q_sys_cpu_cpu' cpu" instantiated altera_nios2_gen2_unit "cpu"]]> queue size: 230 starting:altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx" ddr3_ram" instantiated altera_mem_if_ddr3_afi_mux "m0"]]> queue size: 229 starting:altera_eth_tse_mac "submodules/altera_eth_tse_mac" eth_tse" instantiated altera_eth_tse_mac "i_tse_mac"]]> queue size: 228 starting:altera_gpio_lite "submodules/altera_gpio_lite" eth_tse" instantiated altera_gpio_lite "rgmii_in4_0"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_gpio_lite.sv]]> queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_soft_asmiblock_instance_name" soft_asmiblock_instance_name" reuses soft_asmiblock "submodules/soft_asmiblock"]]> ext_flash" instantiated altera_generic_quad_spi_controller "soft_asmiblock_instance_name"]]> queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock" soft_asmiblock_instance_name" instantiated soft_asmiblock "soft_asmiblock_instance_name"]]> queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_asmi_parallel_instance_name" asmi_parallel_instance_name" reuses altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name"]]> ext_flash" instantiated altera_generic_quad_spi_controller "asmi_parallel_instance_name"]]> queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name asmi_parallel_instance_name" instantiated altera_asmi_parallel "asmi_parallel_instance_name"]]> queue size: 224 starting:altera_generic_quad_spi_controller "submodules/q_sys_ext_flash_epcq_controller_instance_name" epcq_controller_instance_name" reuses altera_epcq_controller_core "submodules/altera_epcq_controller_arb"]]> ext_flash" instantiated altera_generic_quad_spi_controller "epcq_controller_instance_name"]]> queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb" epcq_controller_instance_name" instantiated altera_epcq_controller_core "epcq_controller_instance_name"]]> queue size: 224 starting:modular_sgdma_dispatcher "submodules/dispatcher" msgdma_rx" instantiated modular_sgdma_dispatcher "dispatcher_internal"]]> queue size: 223 starting:altera_msgdma_prefetcher "submodules/altera_msgdma_prefetcher" msgdma_rx" instantiated altera_msgdma_prefetcher "prefetcher_internal"]]> queue size: 222 starting:dma_write_master "submodules/write_master" msgdma_rx" instantiated dma_write_master "write_mstr_internal"]]> queue size: 219 starting:dma_read_master "submodules/read_master" msgdma_tx" instantiated dma_read_master "read_mstr_internal"]]> queue size: 218 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "sensor_interface_calibration_ram_interface_translator"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_translator.sv]]> queue size: 217 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "calibration_ram_s2_translator"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_translator.sv]]> queue size: 187 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_1" instantiated altera_merlin_master_agent "cpu_data_master_agent"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_master_agent.sv]]> queue size: 179 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_1" instantiated altera_merlin_slave_agent "ddr3_ram_avl_agent"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_slave_agent.sv]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 178 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_1" instantiated altera_avalon_sc_fifo "ddr3_ram_avl_agent_rsp_fifo"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 134 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router" mm_interconnect_1" instantiated altera_merlin_router "router"]]> queue size: 133 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_001" mm_interconnect_1" instantiated altera_merlin_router "router_001"]]> queue size: 132 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_002" mm_interconnect_1" instantiated altera_merlin_router "router_002"]]> queue size: 130 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_004" mm_interconnect_1" instantiated altera_merlin_router "router_004"]]> queue size: 126 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_008" mm_interconnect_1" instantiated altera_merlin_router "router_008"]]> queue size: 125 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_009" mm_interconnect_1" instantiated altera_merlin_router "router_009"]]> queue size: 124 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_010" mm_interconnect_1" instantiated altera_merlin_router "router_010"]]> queue size: 112 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_022" mm_interconnect_1" instantiated altera_merlin_router "router_022"]]> queue size: 106 starting:altera_merlin_router "submodules/q_sys_mm_interconnect_1_router_028" mm_interconnect_1" instantiated altera_merlin_router "router_028"]]> queue size: 105 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" mm_interconnect_1" instantiated altera_merlin_traffic_limiter "cpu_data_master_limiter"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 103 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" mm_interconnect_1" instantiated altera_merlin_burst_adapter "ext_flash_avl_mem_burst_adapter"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> queue size: 101 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 100 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_001" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> queue size: 99 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_cmd_demux_002" mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux_002"]]> queue size: 93 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 92 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_001" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_001"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 91 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_002" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_002"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 79 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_cmd_mux_014" mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_014"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 72 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"]]> queue size: 71 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_001" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_001"]]> queue size: 70 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_002" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_002"]]> queue size: 62 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_010" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_010"]]> queue size: 58 starting:altera_merlin_demultiplexer "submodules/q_sys_mm_interconnect_1_rsp_demux_014" mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_014"]]> queue size: 51 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 50 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_001" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 49 starting:altera_merlin_multiplexer "submodules/q_sys_mm_interconnect_1_rsp_mux_002" mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux_002"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 43 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" mm_interconnect_1" instantiated altera_merlin_width_adapter "calibration_ram_s1_rsp_width_adapter"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_address_alignment.sv]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 41 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" mm_interconnect_1" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> /auto/work/qinliqing/intelFPGA_lite/19.1/hit_pat/q_sys/synthesis/submodules/altera_std_synchronizer_nocut.v]]> queue size: 27 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 8 starting:altera_avalon_st_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter_020" reuses error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0"]]> mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter_020"]]> queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" avalon_st_adapter_020" instantiated error_adapter "error_adapter_0"]]> queue size: 8 starting:error_adapter "submodules/q_sys_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 7 starting:timing_adapter "submodules/q_sys_avalon_st_adapter_001_timing_adapter_0" avalon_st_adapter_001" instantiated timing_adapter "timing_adapter_0"]]> queue size: 5 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" c0" instantiated alt_mem_ddrx_mm_st_converter "a0"]]> queue size: 4 starting:soft_asmiblock "submodules/soft_asmiblock" soft_asmiblock_instance_name" instantiated soft_asmiblock "soft_asmiblock_instance_name"]]> queue size: 3 starting:altera_asmi_parallel "submodules/q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name" generating top-level entity q_sys_ext_flash_asmi_parallel_instance_name_asmi_parallel_instance_name asmi_parallel_instance_name" instantiated altera_asmi_parallel "asmi_parallel_instance_name"]]> queue size: 2 starting:altera_epcq_controller_core "submodules/altera_epcq_controller_arb" epcq_controller_instance_name" instantiated altera_epcq_controller_core "epcq_controller_instance_name"]]> queue size: 1 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 0 starting:error_adapter "submodules/q_sys_mm_interconnect_1_avalon_st_adapter_020_error_adapter_0" avalon_st_adapter_020" instantiated error_adapter "error_adapter_0"]]>