138 lines
5.5 KiB
Verilog
138 lines
5.5 KiB
Verilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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/*
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This block is used to breakout the 256 bit streaming ports to and from the write master.
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The information sent through the streaming ports is a bundle of wires and buses so it's
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fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
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This block also provides a layer of abstraction since the descriptor buffers block has
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no clue what format the descriptors are in except that the 'go' bit is written to. This
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means that using this block you could move descriptor information around without affecting
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the top level dispatcher logic.
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1.0 06/29/2009 - First version of this block of wires
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1.1 02/15/2011 - Added read_early_done_enable to the wire breakout
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1.2 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
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*/
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module read_signal_breakout (
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read_command_data_in, // descriptor from the read FIFO
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read_command_data_out, // reformated descriptor to the read master
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// breakout of command information
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read_address,
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read_length,
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read_transmit_channel,
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read_generate_sop,
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read_generate_eop,
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read_park,
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read_transfer_complete_IRQ_mask,
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read_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
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read_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
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read_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
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read_transmit_error,
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read_early_done_enable,
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// additional control information that needs to go out asynchronously with the command data
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read_stop,
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read_sw_reset
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);
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parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
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input [DATA_WIDTH-1:0] read_command_data_in;
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output wire [255:0] read_command_data_out;
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output wire [63:0] read_address;
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output wire [31:0] read_length;
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output wire [7:0] read_transmit_channel;
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output wire read_generate_sop;
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output wire read_generate_eop;
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output wire read_park;
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output wire read_transfer_complete_IRQ_mask;
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output wire [7:0] read_burst_count;
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output wire [15:0] read_stride;
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output wire [15:0] read_sequence_number;
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output wire [7:0] read_transmit_error;
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output wire read_early_done_enable;
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input read_stop;
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input read_sw_reset;
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assign read_address[31:0] = read_command_data_in[31:0];
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assign read_length = read_command_data_in[95:64];
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generate
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if (DATA_WIDTH == 256)
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begin
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assign read_early_done_enable = read_command_data_in[248];
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assign read_transmit_error = read_command_data_in[247:240];
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assign read_transmit_channel = read_command_data_in[231:224];
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assign read_generate_sop = read_command_data_in[232];
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assign read_generate_eop = read_command_data_in[233];
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assign read_park = read_command_data_in[234];
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assign read_transfer_complete_IRQ_mask = read_command_data_in[238];
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assign read_burst_count = read_command_data_in[119:112];
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assign read_stride = read_command_data_in[143:128];
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assign read_sequence_number = read_command_data_in[111:96];
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assign read_address[63:32] = read_command_data_in[191:160];
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end
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else
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begin
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assign read_early_done_enable = read_command_data_in[120];
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assign read_transmit_error = read_command_data_in[119:112];
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assign read_transmit_channel = read_command_data_in[103:96];
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assign read_generate_sop = read_command_data_in[104];
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assign read_generate_eop = read_command_data_in[105];
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assign read_park = read_command_data_in[106];
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assign read_transfer_complete_IRQ_mask = read_command_data_in[110];
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assign read_burst_count = 8'h00;
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assign read_stride = 16'h0000;
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assign read_sequence_number = 16'h0000;
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assign read_address[63:32] = 32'h00000000;
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end
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endgenerate
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// big concat statement to glue all the signals back together to go out to the read master (MSBs to LSBs)
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assign read_command_data_out = {{115{1'b0}}, // zero pad the upper 115 bits
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read_address[63:32],
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read_early_done_enable,
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read_transmit_error,
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read_stride,
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read_burst_count,
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read_sw_reset,
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read_stop,
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read_generate_eop,
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read_generate_sop,
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read_transmit_channel,
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read_length,
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read_address[31:0]};
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endmodule
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