\chapter{Front-End Electronics of the SciFi Tracker}
\label{ch:fee}

The front-end electronics of the \scifitracker{} follow a modular design.
Each HalfROB consists of one \MB{}, four \CB{}s, and four \PB{}s.
The latter are the direct interfaces to the SiPMs.
Each \PB{} houses four custom 64-channel ASICs (Application Specific Integrated Circuits) that perform the analogue processing and digitisation of the SiPM signals.
In the next step, the \CB{}s perform a hit clustering and noise suppression on the digital pattern provided by the \PB{}s with the help of two on-board FPGAs (Field Programmable Gate Arrays).
Lastly, the clustered data is encoded and shipped to the DAQ servers via optical transmitters located on the \MB{}.
In addition, the \MB{} is responsible for distributing power, clocks and control commands among all boards within one HalfROB.
\Vref{fig:fee-datapath} shows a block diagram of one HalfROB with the indicated data stream from the SiPMs to the optical transmitters.

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/FEE-Datapath}
  \caption{
    Block diagram of a HalfROB with the main components on each board denoted.
    The data stream is indicated by the green arrows.
    The blue arrows illustrate the bidirectional optical control link.
    Image edited from Ref.~\autocite{fee-design}.
  }
  \label{fig:fee-datapath}
\end{figure}

Following the path of the data, the various components of the SciFi front-end electronics will be discussed in the following sections.

\section{PACIFIC Board}
The \PB{} (PB) is a 14-layer PCB with a nominal thickness of \qty{1.6}{\milli\meter} that measures \qty{65}{\milli\meter} in length and \qty{60}{\milli\meter} in width~\autocite{pb-edms}.
It serves as the carrier board for four PACIFIC ASICs, which are responsible for the analogue processing and digitisation of the SiPM signals.
Further information on the PACIFIC chip follow in \cref{sec:pacific}.
The layout of both sides of the \PB{} is shown in \vref{fig:pb-schematic}.

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/PB_Schematic}
  \caption{
    Layout of the front (left) and back (right) of a \PB{}.
    The connectors to the SiPM flex cables are shown on the top left.
    On the bottom right, the FMC connection points to the \CB{} are displayed.
    The four PACIFIC ASICs are soldered on the square areas on the right.
    Image edited from Ref.~\autocite{pb-edms}.
  }
  \label{fig:pb-schematic}
\end{figure}

Besides from housing the PACIFIC ASICs, four 80-pins, \qty{0.5}{\milli\meter} pitch connectors\footnote{DF12(3.0)-80DS-0.5V by Hirose Electric Co., Ltd.} are located on the board.
They are used to connect two SiPM flex cables, which hold two female counterparts of these connectors on each cable (see \vref{fig:sipm-zoom}).
On each connector, 64 pins are used for the 64 channels of one SiPM die.
The remaining pins are connected to the bias voltage and ground.
In addition, for each connector pair, one line goes to the Pt1000 temperature sensor located on the backside of the SiPM arrays.
Thereby, a total of 256 SiPM channels are operated by one \PB{}.

The analogue SiPM signals are directed to the PACIFIC ASICs.
From there, the digital output is forwarded to a high-speed, 400-pin FMC (FPGA Mezzanine Card) connector\footnote{ASP-134602-01 (HPC) by Samtec, Inc.} that allows for the connection to the \CB{}.

Besides from being responsible for the routing of the signals, the \PB{} contains several monitoring circuits.
Two Pt1000 temperature sensors\footnote{Pt1000 SMD 0805 Class B by Heraeus Nexensos GmbH} are located between the four ASICs and the FMC connector on the backside of the board.
They are denoted as R10 and R21 on the right side of \vref{fig:pb-schematic}.
The readout is performed by an ADC (Analogue-to-Digital Converter) located on the \CB{} (see \cref{sec:cb}).
A monitoring of the bias voltages applied to the SiPM dies is enabled by four voltage divider circuits.
%They are required to produce an output voltage that lies in the range [$0, 1$]$\,\unit{\volt}$ of the ADC -- in contrast to typical bias voltages between \qtyrange[range-phrase={ and }]{50}{60}{\volt}.
The involved resistors are located next to the SiPM connectors and are denoted as R1-R9 and R11-R13 in \vref{fig:pb-schematic}.

Each \PB{} is assigned a unique 48-bit serial number that is stored on a 1-Wire serial ID device\footnote{DS2401P+ by Maxim Integrated}.



\section{PACIFIC ASIC}
\label{sec:pacific}

The PACIFIC is a low-power ASIC specifically designed for the \scifitracker{}.
This is also reflected by the acronym PACIFIC that stands for low-\textbf{\underline{p}}ower \textbf{\underline{A}}SIC  for the S\textbf{\underline{ci}}ntillating \textbf{\underline{Fi}}bre Tra\textbf{\underline{c}}ker.
The chip allows for the readout of 64 SiPM channels and was developed using TSMC's\footnote{Taiwan Semiconductor Manufacturing Company, Limited, Hsinchu, Taiwan} \qty{130}{\nano\meter} CMOS technology.
It is designed to be radiation tolerant and operate at the LHC clock frequency of \qty{40}{\mega\hertz} with a power consumption of less than \qty{10}{\milli\watt} per channel~\autocite{pacific-paper}.

\begin{figure}
  \centering
  \includegraphics[width=0.9\textwidth]{figures/fee/PACIFIC_Blocks}
  \caption{
    Logical structure of the PACIFIC ASIC.
    Image adapted from Ref.~\autocite{pacific-paper-albert}.
  }
  \label{fig:pacific-blocks}
\end{figure}


As shown in \vref{fig:pacific-blocks}, the PACIFIC consists of various logical blocks that are presented in the following.

\subsection{Signal Processing and Digitisation}
\label{sec:pacific_processing}
A block diagram of one channel of the PACIFIC ASIC is shown in \vref{fig:pacific-channel}.
The analogue processing and digitisation of the SiPM signal can be divided into five successive stages that are discussed in the following.

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/PACIFIC_Channel}
  \caption{
    Channel block diagram of the PACIFIC ASIC.
    Each channel consists of five stages in which the analogue SiPM signal is processed and digitised.
    Image taken from Ref.~\autocite{pacific-paper}.
  }
  \label{fig:pacific-channel}
\end{figure}


\subsubsection{Pre-amplification}
\label{sec:pacific_preamp}
The first stage of the signal processing chain is the pre-amplification, or input stage.
It is directly connected to the anode of the SiPM and provides a current mode input with a low impedance and high bandwidth of about \qty{50}{\ohm} and \qty{250}{\mega\hertz}, respectively~\autocite{pacific-datasheet}.

\begin{figure}
  \centering
  \includegraphics[width=0.8\textwidth]{figures/fee/PACIFIC_Voffset}
  \caption{
    Anode voltage generation circuit within the PACIFIC.
    Each channel can be connected independently to the output voltages $V_0$ to $V_{15}$.
    %With a typical reference voltage $V_\text{REF} = \qty{500}{\milli\volt}$, this circuit allows for step sizes of \qty{40}{\milli\volt}.
    Image adapted from Ref.~\autocite{pacific-datasheet}.
  }
  \label{fig:pacific-voffset}
\end{figure}

The input stage consists of a current conveyer based on a novel approach using two feedback loops~\autocite{albert-diss}.
It allows for the selection of four different gains, as well as the possibility to modify the bias voltage of each individual channel over a range of \qty{600}{\milli\volt}.
This is achieved by the implementation of the voltage divider chain as shown in \vref{fig:pacific-voffset} that produces voltages
\begin{equation}
 % V_x = \frac{3}{25} \cdot 2 V_\text{REF} + \frac{x}{25} \cdot 2 V_\text{REF} = \frac{2}{25}V_\text{REF}(x+3)
  V_x = \frac{R_x}{R_\text{tot}}\cdot 2 V_\text{REF} = \frac{(x+3)R}{25R}\cdot 2 V_\text{REF} = \frac{2}{25}V_\text{REF}(x+3)
\end{equation}
at the different outputs $V_x$.
With a typical reference voltage $V_\text{REF} = \qty{500}{\milli\volt}$, the bias voltage can be fine tuned in \qty{40}{\milli\volt} steps, which corresponds to a change in gain by about \qty{1}{\percent} around the nominal overvoltage $\OV{} = \qty{3.5}{\volt}$ as derived in \vref{eq:sipm-gain}.
Each channel can be connected independently to the output voltages $V_0$ to $V_{15}$ as determined by four control bits in the channel configuration registers (see \cref{sec:pacific_regs}).

The current conveyer is followed by a closed-loop transimpedance amplifier.
It converts the current signal coming from the SiPM to a voltage signal that is used for further processing.
As indicated in \vref{fig:pacific-channel}, three extra debug (DBG) pins are included in the design that give access to different stages in the analogue signal processing.
An internal multiplexer is used to select the channel to be tested.
\Vref{fig:pacific-preamp-shaper} (left) shows the typical debug output of the pre-amplification stage.
The signals on the oscilloscope are generated by illuminating the SiPMs with short light pulses (see \cref{sec:lis} for further details).
A band structure is visible at early times corresponding to different numbers of pixels with triggered avalanches.

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/PACIFIC_Preamp_Shaper}
  \caption{
    PACIFIC pre-amplifier (left) and shaper (right) output. Images adapted from Ref.~\autocite{pacific-paper-albert}.
  }
  \label{fig:pacific-preamp-shaper}
\end{figure}

\subsubsection{Shaping}
\label{sec:pacific_shaper}
As can be seen at the output of the pre-amplification stage in \vref{fig:pacific-preamp-shaper} (left), the signals extend over several \qty{25}{\nano\second} LHC clock cycle periods.
This is mainly due to the recovery time of the SiPM pixels as discussed in \cref{sec:sipm} and would lead to unwanted spillover into the following bunch crossing intervals.
Therefore, a shaper is used within the PACIFIC to suppress the exponential tail of the signal.
It is based on a pole-zero cancellation circuit as shown in \cref{fig:pacific-polezero}.
The impedance between the two nodes is given by
\begin{equation}
  Z(\omega) = \left(\frac{1}{R_\text{PZ1}} + i\omega C_\text{PZ1}\right)^{-1} = \frac{R_\text{PZ1}}{1+i\omega C_\text{PZ1}R_\text{PZ1}}
\end{equation}
which has a pole at
\begin{equation}
  \omega = \frac{i}{C_\text{PZ1}R_\text{PZ1}} \equiv \frac{i}{\tau_\text{PZ1}}\,.
\end{equation}
The time constant $\tau_\text{PZ1}$ thereby determines the fall time of the shaper output.
It can be tuned by modifying the resistor $R_\text{PZ1}$ and capacitor $C_\text{PZ1}$ within the circuit, which is enabled through dedicated control bits in the configuration registers (see \cref{sec:pacific_regs}).

Typical output signals of the shaping stage as seen on the oscilloscope are shown in \vref{fig:pacific-preamp-shaper} (right).
Compared to the pre-amplifier output, the fall time is reduced significantly allowing the signal to be fully integrated in the following stage.

\begin{figure}
  \centering
  \begin{minipage}[c]{0.33\textwidth}
    \centering
    \includegraphics[width=1.0\textwidth]{figures/fee/PACIFIC_Polezero}
    \caption{
      Pole-zero cancellation circuit as used in the shaping stage of the \mbox{PACIFIC} channels.
    }
    \label{fig:pacific-polezero}
  \end{minipage}
  \hfill
  \begin{minipage}[c]{0.63\textwidth}
    \centering
    \includegraphics[width=1.0\linewidth]{figures/fee/PACIFIC_TH_Circuit}
    \caption{
      Schematics of the track and hold stage of the \mbox{PACIFIC} channels.
    }
    \label{fig:pacific-th-circuit}
  \end{minipage}
\end{figure}

\subsubsection{Integration}
\label{sec:pacific_integration}
The amplified and shaped signal is integrated in each \qty{40}{\mega\hertz} clock cycle in order to accommodate for variations in the photon arrival time due to the decay and travel time in the scintillating fibres.
The implementation uses two gated integrators.
They integrate the signals in an interleaved manner at half the system clock frequency (\qty{20}{\mega\hertz}).
This means that while one integrator is in use, the remaining one is being reset.
This structure allows for a reduction of the dead time to a minimum.

It is of crucial importance that the two integrators have similar properties to ensure the same performance in even and odd bunch crossing numbers corresponding to the different integrators.
However, due to manufacturing tolerances, especially the DC baselines can show significant differences.
The DC baseline refers to the integrator output level in the absence of an input pulse.
Since any additional signal is added to it, it is also commonly designated as pedestal.
A correction mechanism is foreseen that allows for the adjustment of the reference voltage of each integrator thus effectively shifting the baseline.
It can be tuned by means of a 4-bit current output DAC (Digital-to-Analogue Converter) that can feed current in both directions.
This enables the reference voltage of each integrator to take 31 different values, which are controlled through dedicated control bits in the configuration registers (see \cref{sec:pacific_regs}).
The alignment of the DC baselines of the two integrators is also referred to as trimming and is explained in detail in \cref{sec:trimming}.


\subsubsection{Track and Hold}
The integrators are followed by a dual passive track and hold stage that stabilises and merges the signals from the two integrators for the subsequent digitisation step.
As shown in the schematics in \vref{fig:pacific-th-circuit}, it is based on two capacitors $C_{1,2}$ and several switches that are operating in synchronous with the previous stage.
Similar to the integrators, the switching is performed in an interleaved manner using the clock $\text{clk}$ and its inverted $\overbar{\text{clk}}$ at a frequency of \qty{20}{\mega\hertz}.
While integrator 1 is in use, its output $V_\text{int1}$ is connected to the capacitor $C_1$, but disconnected from the common track and hold output $V_\text{out}$.
At the same time, the capacitor $C_2$ is connected to $V_\text{out}$, but disconnected from integrator 2.
After \qty{25}{\nano\second}, the situation is reversed such that $C_2$ is connected to the integrator output $V_\text{int2}$.

In previous prototypes of the PACIFIC ASIC, the capacitors were directly connected to ground.
However, it was found that this design leads to a non-negligible amount of charge sharing in the order of \qty{25}{\percent} between the two capacitors because they are connected to each other for a brief moment during the switching process.
For an unirradiated detector, this resulted in \qty{60}{\percent} of fake hits in the bunch crossing after the detection of a signal at the same position.
The implementation of the track and hold stage was identified as a major contribution to this effect.
The redesigned schematic includes two additional switches driven by the clocks $\text{clk1}$ and $\text{clk2}$ as shown in \vref{fig:pacific-th-circuit}.
At the moment of the switching, they disconnect the capacitor that is currently not in use for a short period ($<\qty{1}{\nano\second}$).
In addition, the interleaved switching procedure as just described is slightly shifted with respect to each other to decouple the two capacitors even further.

\begin{figure}
  \centering
  \includegraphics[width=0.9\textwidth]{figures/fee/PACIFIC_TH_Output}
  \caption{
    Typical output of the track and hold stage of the PACIFIC channels.
    The distribution on the left represents the pulse height projection of the signals within the brown rectangle in logarithmic scale.
  }
  \label{fig:pacific-th-output}
\end{figure}


The typical output of the track and hold stage is shown in \vref{fig:pacific-th-output}.
Note that the signals are going in negative direction since the gated integrators are using an inverted structure.
The pulse height projection of the signals included in the oscilloscope image illustrates the clear peaking structure corresponding to different numbers of photoelectrons.
Unlike the debug output of the pre-amplifier or shaper (\vref{fig:pacific-preamp-shaper}), the output of the track and hold stage strongly depends on the timing of the pulsed light with respect to the system clock.
The delay needs to be tuned carefully such that the signals can be fully integrated in the previous stage.
At the optimal timing, the distance between the photoelectron peaks is maximised.
This aspect is explained in more detail in \cref{sec:lis-tests}.


\subsubsection{Digitisation}
\label{sec:pacific_digitisation}
The last stage of the signal processing in the PACIFIC channels is the digitisation stage.
The analogue SiPM signals processed in the previous steps are digitised by means of three PMOS comparators that act as a simple non-linear flash ADC~\autocite{pacific-paper}.
They feature a mean hysteresis of about $\qty{10}{\milli\volt}$ to avoid repetitive switching at the output when the signal level is close to the set threshold~\autocite{pacific-presentation-herve}.
The comparator thresholds are provided by three independent 8-bit current DACs included in each channel.
The generated currents are injected into a \qty{\approx 50}{\kilo\ohm} resistor allowing for voltages between ground and \qty{760}{\milli\volt}~\autocite{pacific-datasheet}.
In the default configuration, one threshold DAC step corresponds to about \qty{2.5}{\milli\volt}.

Due to the discrete SiPM signal amplitudes depending on the number of activated pixels (see \cref{sec:sipm}), having a larger granularity ADC offers little added value, while only consuming a higher bandwidth.
On the other hand, the independently adjustable thresholds provide the flexibility to efficiently digitise the signals in preparation for the following processing steps.
However, the disadvantage of this design is that appropriate thresholds must be set prior to taking data.
The calibration procedure required for this is described in \cref{sec:th_scan}.

Besides from the three threshold DACs in each individual channel, the PACIFIC ASIC features an additional set of threshold DACs that are common to all channels.
In the following, the latter are referred to as common thresholds, while the individual threshold DACs are called local thresholds.
As illustrated in \vref{fig:pacific-channel}, a switch is included in each channel that allows for the selection of the different sets of thresholds.
During the design phase of the chip, it was intended to primarily use the common thresholds.
While this allows for an easier handling, it requires that all 64 channels in each chip have a high uniformity in terms of gain and DC baselines.
However, it was found that especially the DC baselines show large variations that can not always be corrected by means of the trimming mechanism described earlier.
Therefore, the local threshold DACs became the standard when operating the detector.

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/PACIFIC_DAC_OffsetSlope_Control}
  \caption{
    Relationship between the digital input value and the output voltage of a PACIFIC threshold DAC.
    In addition, the effect of the slope (left) and offset (right) control is illustrated.
    Images adapted from Ref.~\autocite{pacific-datasheet}.
  }
  \label{fig:pacific-offset-slope-control}
\end{figure}

A circuit is implemented that allows for the adjustment of the range and granularity of the threshold DACs.
The slope can be modified by adding or removing current to the DACs' current reference.
A similar mechanism is foreseen at the output of the DACs, just before the resistor that performs the conversion to a voltage.
By adding a certain amount of current at this point, the offset can be tuned.
The slope and offset adjustment is applied to all threshold DACs (common and local) at the same time.
Both variables are controlled by 4 bits in the configuration registers each.
An additional bit determines the sign of the slope adjustment.

The relation between the set threshold DAC input value and the output voltage is shown in \vref{fig:pacific-offset-slope-control}.
In addition, it demonstrates the effect of the slope and offset adjustment.

The output of each PACIFIC channel is a 3-bit pattern at \qty{40}{\mega\hertz} corresponding to whether ($1$) or not ($0$) the signal amplitude exceeds the thresholds of the three comparators.



\subsection{Serialisation}
\label{sec:pacific_ser}
A fast serialiser block follows the PACIFIC channels and enables the data transmission to the \CB{}.
The complete serialisation procedure is illustrated in the digital timing diagram in \vref{fig:pacific-serialiser}.
Its operation relies on a \qty{320}{\mega\hertz} master clock (denoted as CLKout in the diagram).
Based on this clock, the \qty{40}{\mega\hertz} (CLKin), as well as the two complementary \qty{20}{\mega\hertz} clocks required for the analogue processing and digitisation are generated.

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/PACIFIC_Serialiser}
  \caption{
    Digital timing diagram of the PACIFIC serialiser during normal operation.
    The $x$-axis is labelled in units of the \qty{320}{\mega\hertz} clock period (CLKout) that determines the output data stream.
    Image taken from Ref.~\autocite{pacific-datasheet}.
  }
  \label{fig:pacific-serialiser}
\end{figure}

In the first step of the serialisation, the output of the three comparators of each PACIFIC channel is sampled at the rising edge of the \qty{40}{\mega\hertz} clock.
The outputs of four neighbouring channels are thereby written into a 12-bit internal register (intReg).
To stay within the available bandwidth, a simple compression is performed in which the 3 bits of each channel are arithmetically added to form a 2-bit integer that represents the number of comparators whose threshold levels were exceeded by the signal amplitude.
Assuming a strict hierarchy and proper functioning of the comparators, no information is lost in the process.
With the help of an internal shift register (shiftReg), the compressed data (ePortIn) is output sequentially over a differential link at the rising edge of the \qty{320}{\mega\hertz} clock (outData)
Each chip comprises 16 differential outputs to cover the total of 64 channels, resulting in a data rate of \qty{5.12}{\giga\bit/\second}.

Furthermore, an additional input signal that is referred to as SYNC is shown in the diagram.
As the name suggests, it is responsible for synchronising the total of \num{8192} PACIFIC ASICs installed in the \scifitracker{}.
It is evaluated at the rising edge of the \qty{320}{\mega\hertz} and triggers a reset of the state machine in the clock generator upon arrival.
Thereby, it ensures that the slower \qty{40}{\mega\hertz} and \qty{20}{\mega\hertz} clocks are generated simultaneously in the various chips at a predetermined time.



\subsection{Slow Control Interface and Configuration Registers}
\label{sec:pacific_regs}
The PACIFIC features a slow control interface that is based on standard 10-bit addressing \IIC{}~\autocite{i2c-specification}.
Efficient reading and writing of larger amounts of continuous data is enabled by automatic incrementation of the target address without the need to repeat the 2-byte preamble for every transmitted byte of data.

\begin{table}
  \centering
  \caption{Digital input and output signals of the PACIFIC that interact with the slow control and register blocks.}
  \label{tab:pacific_io_signals}
  \begin{tabular}{@{}llll@{}}
    \toprule
    Signal    & Type   & Logic       & Description                           \\ \midrule
    RESET     & Input  & Active low  & Global digital reset                  \\
    DISACLK   & Input  & Active low  & Disables \IIC{} clock                 \\
    LDINIT    & Input  & Active low  & Loads initial register values         \\
    ERROR1    & Output & Active high & Hamming code detected single bit-flip    \\
    ERRORM    & Output & Active high & Hamming code detected multiple bit-flips \\
    ERROR1GEN & Input  & Active low  & Forces single bit-flips for debugging \\
    REFRESH   & Input  & Active low  & Clears error flags ERROR1 \& ERRORM      \\ \bottomrule
  \end{tabular}
\end{table}

The 10-bit address space is required to allow addressing a total of \num{340} logical registers.
Of these, \num{336} read/write registers contain the configuration parameters of the chip.
The additional four are read-only and allow for the monitoring of internal ADC readings and error detection counters.
The registers are logically organised in groups of \num{8} bits resulting in a total of \num{2688} control bits of which \num{2683} are actually in use.

A small fraction of the configuration registers apply to all the \num{64} channels of the PACIFIC.
It includes the parameters for the common bias block and controls, among others, the slope and offset adjustment of the threshold DACs, the pole-zero cancellation parameters, as well as the DAC values of the common thresholds themselves.
This functionality is covered by \num{107} control bits within \num{14} registers.
An additional \num{80} control bits (\num{10} registers) are used for debugging purposes like controlling an internal channel multiplexer to measure the various stages of the analogue processing chain with an oscilloscope as shown in \cref{sec:pacific_processing}.

By far the largest fraction of the configuration registers determines the behaviour of the individual \num{64} channels.
This includes the SiPM bias voltage offset (4~bits) and trimming of the reference voltages of the two integrators (10~bits).
Additionally, the local 8-bit threshold DACs of the three comparators can be selected (1~bit) and adjusted (\numproduct{3 x 8}~bits).
Thereby, \num{39} control bits are required for each PACIFIC channel, resulting in a total of \num{2496} bits, which are logically organised in blocks of eight channels.

Protection against erroneous state changes of the control bits due to ionising radiation (single event upset, SEU) is provided by a Hamming encoding algorithm~\autocite{hamming}.
Each configuration register is split into two 4-bit blocks that are covered by an extended Hamming(7,4) code with an additional parity bit.
Thereby, every 4~bits of data are protected by 4 additional parity bits that allow to detect state changes in up to 3~bits.
Additionally, it can distinguish between errors in single or multiple bits.
While single bit-flips can be corrected on the fly, the configuration has to be rewritten in case of multiple bit-flips.
Both types of errors are counted and stored in two of the four read-only registers mentioned before.

A complete list of the configuration registers is given in the PACIFIC data sheet~\autocite{pacific-datasheet}.
In addition, the PACIFIC features several digital input and output signals that interact with them.
They are summarised in \vref{tab:pacific_io_signals}.

\subsection{Threshold Scan}
\label{sec:th_scan}
Since each PACIFIC channel only features a set of three adjustable comparators, the full SiPM photoelectron spectrum as can be seen with a high-resolution ADC can not be resolved.
However, the determination of the amplitudes corresponding to different numbers of generated photoelectrons (pe) is required to set appropriate thresholds for the operation of the detector.
This process is also referred to as PACIFIC calibration.

Despite the lack of a full ADC, the position of the photoelectron peaks can also be estimated by scanning the threshold DAC counts (hereinafter referred to as DACs) over their entire dynamic range.
In each step, several thousand events are recorded and the ratio of events above threshold is determined.
At the same time, the SiPM channels are illuminated with pulsed light with the help of the light injection system, which is further described in \cref{sec:lis}.

The result of such a threshold scan is an integrated spectrum as shown in \vref{fig:scurve-fit}.
Due to the shape of the curve, it is often referred to as S-curve.
In order to determine the peak positions of the underlying spectrum, a dedicated calibration tool has been developed~\autocite{lukas-thesis}.
It is based on modeling the spectrum of photoelectron peaks $k$ by a sum of Gaussian functions
\begin{equation}
  N(x) = \sum_{k\ge0} A_k \cdot \frac{1}{\sqrt{2\pi\sigma_k^2}} \cdot \exp\left(-\frac{(x-p_k)^2}{2\sigma_k^2}\right)
\end{equation}
with amplitudes $A_k$, means $p_k$ and widths $\sigma_k$~\autocite{sipm-model}.
The width of the first peak $\sigma_0$, corresponding to the channel baseline or pedestal, is determined by the electronic noise, while subsequent peaks are additionally widened due to slight variations $\sigma_1$ between pixels
\begin{equation}
  \sigma_k^2 = \sigma_0^2 + k \cdot \sigma_1^2\,.
  \label{eq:peak-widths}
\end{equation}
The amplitudes $A_k$ are primarily dependant on the light intensity $\mu$ that describes the mean number of photons within a Poisson distribution.
However, due to pixel crosstalk $\lambda$ (see \cref{sec:sipm}), it is modified to the so-called Generalised Poisson distribution~\autocite{generalised-poisson}
\begin{equation}
  A_k(\mu, \lambda) = \frac{\mu\cdot(\mu+k\cdot\lambda)^{k-1}\cdot \text{exp}(-\mu-k\cdot\lambda)}{k!}\,.
\end{equation}
When performing the threshold scan as described previously, the course of the S-curve is given by the complementary cumulative distribution function of $N(x)$
\begin{equation}
  S(x) = \text{P}(X > x) = \int_x^{\infty} N(x')\,\text{d}x' = 1 - \sum_{k\ge0} A_k(\mu, \lambda) \cdot \frac{1}{2} \left[1+\text{erf}\left(\frac{x-p_k}{\sigma_k \sqrt{2}}\right)\right]\,.
\end{equation}
Ideally, the peak positions $p_k$ have the same distance to each other, which is hereinafter referred to as photoelectron peak separation.
It is determined by the gain of the SiPM as well as the analogue processing chain in the PACIFIC.
Since the photoelectron peaks become only visible by means of the threshold scans, they are stated in units of threshold DACs in the following.
As can be seen in \vref{fig:scurve-fit}, the separation between the peak positions $p_k$ is not constant, which is due to non-linearities in the PACIFIC channels.
Therefore, the positions of the first six peaks are determined individually when performing the fits of the S-curves.
Along with the light intensity $\mu$, crosstalk probability $\lambda$, and the two width parameters $\sigma_0$ and $\sigma_1$, a total of 10 free parameters are used in the fit of a single \Scurve{}.

\begin{figure}
  \centering
  \includegraphics[width=0.75\textwidth]{figures/fee/ScurveFit}
  \caption{
    SiPM photoelectron spectrum and corresponding data (\Scurve{}) as determined by a \mbox{PACIFIC} threshold scan.
    Image adapted from Ref.~\autocite{lukas-poster}.
  }
  \label{fig:scurve-fit}
\end{figure}

Based on the obtained parameter values, the threshold DAC settings of the three comparators per PACIFIC channel are calibrated.
The default operating thresholds are set to be in the middle of the determined positions of the 1st, 2nd, 3rd and 4th photoelectron peak, also referred to as $[1.5, 2.5, 3.5]\,\text{pe}$.
Thereby, in terms of the recorded S-curves, the thresholds are tuned to be in the middle of the plateaus, i.e. the regions where the ratio stays constant over a few DACs.
With a typical photoelectron peak separation of \qty{15}{DACs} and peak width parameters $\sigma_{0,1} \approx \qty{1}{DACs}$, the width of the \qty{1.5}{pe} plateau is about \qty{10}{DACs}, which corresponds to the margin of error in the determination of the threshold.
Due to the variations in the SiPM pixels, the peaks are widened with increasing numbers of photoelectrons according to \cref{eq:peak-widths} thus reducing the width of the plateaus.

However, the peak separation of \qty{15}{DACs} is only achieved in the case where the SiPM signals are fully integrated by the PACIFIC channels.
For non-optimal timings, the charge accumulated by the PACIFIC integrators is reduced resulting in squashed S-curves in the horizontal direction.
On the other hand, the plateau heights are determined by the light intensity, which has to be low enough to be able to locate the pedestal position, but large enough in order to identify the higher order photoelectron peaks.
Light intensities corresponding to mean number of detected photons $\mu$ between 1 and 2 have been found to be optimal.

Technically the scan procedure is complicated:
A separate threshold scan is required for each of the three comparators, resulting in a total of \num{768} steps per channel.
This is because the output of the PACIFIC is encoded in 2 bits per channel (see \cref{sec:pacific_ser}).
Thereby, only the number of exceeded comparator threshold levels are kept, while the information about the individual comparator response is lost.
Therefore, while scanning one comparator, the thresholds of the remaining two are set to the maximum value (\qty{256}{DACs}).
This provides sensitivity to a single comparator, as any change in output can be traced back to the currently scanned comparator.


\section{Cluster Board}
\label{sec:cb}

\begin{figure}
  \centering
  \includegraphics[width=0.9\textwidth]{figures/fee/CB}
  \caption{
    Close-up view of a \CB{} mounted on the bottom side of a \MB{}.
    The connection to the \PB{} on the left can be established through the black FMC connector.
  }
  \label{fig:cb}
\end{figure}

The \CB{} (CB) forms the bridge between the PACIFIC and \MB{}.
With \qty{60}{\milli\meter} it matches the same width as the \PB{}, despite being about \qty{35}{\percent} longer.
A close-up photograph of a \CB{} mounted on the backside of a \MB{} is shown in \vref{fig:cb}.
It also displays the black 400-pin FMC connector that is used to establish the connection to the \PB{}.
The same connector type is used for mounting on the \MB{}.

The main components of the \CB{} are two FPGAs located on the bottom of the PCB.
They perform the hit reconstruction and noise suppression based on the digitised signals provided by the PACIFIC ASICs.
The FPGAs, as well as the ASICs on the associated \PB{}, are controlled by a dedicated slow control chip that will be discussed shortly.

Similar to the \PB{}, each \CB{} is equipped with three Pt1000 sensors to allow the monitoring of the temperatures on the PCB.



\subsection{Cluster SCA}
\label{sec:cluster-sca}
A CERN GBT-SCA chip~\autocite{gbt-sca} is used as the Slow Control Adapter (SCA) on the \CB{}.
It provides the interface to control and monitor the various front-end electronics components.
The GigaBit Transceiver (GBT) project was founded to address the challenges of growing beam intensities and radiation doses at the LHC.
The GBT-SCA, built in commercial \qty{130}{\nm} CMOS technology, is part of a series of ASICs that were designed in this context to implement a radiation-hard bidirectional \qty{4.8}{\giga\bit/s} optical fibre link between the front- and back-end electronics~\autocite{gbt-project}.

As an universally applicable chip for the LHCb detector, the GBT-SCA supports various control buses that are commonly used in High Energy Physics (HEP).
These include one Serial Peripheral Interface (SPI) master, one JTAG master, 16 independent \IIC{} masters, and 32 general-purpose input/output (GPIO) pins.
In addition, it provides 31 analogue inputs that are multiplexed to a pre-calibrated 12-bit ADC covering the range between \qtyrange[range-phrase={ and }]{0}{1}{\volt}.
Each input features a switchable \qty{100}{\micro\ampere} current source that allows for the operation of externally connected resistance thermometers.
One additional input is internally connected to an embedded temperature sensor.
Conversely, four 8-bit DACs are available that can provide voltages between \qtyrange[range-phrase={ and }]{0}{1}{\volt} on four different analogue output ports~\autocite{gbt-sca-manual}.

Besides from providing the interface to the various supported control buses, the GBT-SCA features three 8-bit control registers itself.
With the help of the 24 available control bits in these registers, the channels that are not in use in a specific application can be disabled to reduce the overall power consumption.
The 16 \IIC{} master interfaces can be switched independently.
Four additional control bits allow to turn off or on the SPI and JTAG interface, as well as the ADC and GPIO pins, leaving four reserve bits unused.
Initially, all control registers start-up with 0x00, which means that all control buses are deactivated by default.
An additional 24-bit read-only register contains a unique ID that is written on internal electronic fuses during the production and testing of the SCA chip.

\subsubsection{Application on the Cluster Board}

The Cluster (Board) SCA utilises six of the available \IIC{} masters.
Since the \PB{} does not have its own SCA, four of these are used for the communication with the \IIC{} slaves of the four associated PACIFIC ASICs.
The remaining two channels control the two FPGAs located on the \CB{}.

The JTAG master interface is connected to both FPGAs in a daisy chained manner according to IEEE 1149.1 Standard~\autocite{jtag-standard}.
It is thereby possible to re-program the FPGAs, as well as performing boundary scan tests.
Alternatively, re-programming of the FPGAs is also possible through the available SPI interface that is connected as a reserve.

Of the available 31 analogue ADC inputs, 11 are in use.
They are connected to the Pt1000 temperature sensors on the \CB{}~(3 sensors), the associated \PB{}~(2), as well as on the backside of the two connected SiPM arrays~(2).
Hence, the \qty{100}{\micro\ampere} current source is enabled for these channels to allow for the measurement of the temperature dependent resistance.
The remaining four ADC lines are used for monitoring of the bias voltages of the individual SiPM dies.

In contrast to the ADC inputs, almost all 32 available GPIO pins are utilised in the application of the Cluster SCA.
With the exception of ERROR1GEN, all digital PACIFIC input and output signals listed in \vref{tab:pacific_io_signals} are covered.
With four PACIFIC ASICs associated to each Cluster SCA, this results in a total of 24 occupied GPIO pins.
Another six lines are divided across both FPGAs for performing different types of resets.
The last used pin drives the JTAG reset signal (TRST) leaving only one vacant GPIO pin.



\subsection{Cluster FPGA}
\label{sec:cluster-fpga}

Two radiation tolerant IGLOO2 FPGAs\footnote{IGLOO2 FPGA M2GL090T-FGG484 by Microsemi} provide the key functionality of the \CB{}.
The flash-based FPGAs are built in \qty{65}{\nano\meter} technology and come in a 484-ball BGA (Ball Grid Array) package for mounting on the bottom side of the board~\autocite{clusterboard-manual}.

They perform the hit reconstruction on the digitised SiPM signals received by the PACIFICs, and prepare the data for transmission over the optical links to the DAQ system at the back-end.
Both FPGAs are operating based on an identical firmware that can be loaded through the JTAG or SPI interface of the Cluster SCA as described previously.
However, a subtle distinction is made at one pin that is pulled to \qty{1.5}{\volt} for one FPGA, while being connected to ground for the other.
Within the firmware, this information is used to determine the position on the \CB{}, which is required for locating the origin of the data at the back-end.
Further details are given in \cref{sec:fibre-mapping}.

Each FPGA processes the information from one SiPM array (128~channels) that is readout by two PACIFICs (64~channels each).
With 16 differential outputs per PACIFIC as discussed in \cref{sec:pacific_ser}, this corresponds to a total of 32 FPGA data input lines.

In the first step, the incoming PACIFIC data stream needs to be deserialised.
The block in the FPGA that is responsible for that task operates at a clock frequency of \qty{160}{\mega\hertz}.
In order to cope with the input rate of \qty{320}{\mega\bit/\second} per line, it samples the data at both the rising and falling edge of the clock, which is commonly referred to as Double Data Rate (DDR).


\subsubsection{Clustering}
\label{sec:clustering}
The next processing stage is the clustering block that operates at the general clock frequency of \qty{40}{\mega\hertz}.
It is used to compress the data before transmission over the optical links by reconstructing hit positions while removing noise and redundant zeros (zero suppression).

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/Clustering}
  \caption{
    Illustration of the clustering algorithm.
    The height of each rectangle at the top depicts the SiPM signal amplitude in one channel.
    The 2-bit patterns below represent the outputs of the PACIFIC channels after applying the three comparator thresholds.
    Five clusters are identified by the algorithm as indicated by the green and red colors depending on the fulfilled condition.
    %Grey rectangles correspond to channels which are not part of a formed cluster.
  }
  \label{fig:clustering}
\end{figure}


The hit finding and clustering algorithm follows a similar logic as the procedure to form clusters of VELO hits before the LHCb upgrade~\autocite{guido-diss}.
It is based on the three comparator thresholds in each PACIFIC channel (see \cref{sec:pacific_digitisation}).
They are named following their function within the clustering procedure:

\begin{itemize}
  \item \textbf{Seed threshold:}
    The seed threshold is set to a medium level.
    It marks the starting point for every potential cluster.
    Depending on the signal amplitude within the channel, as well as the output of the neighbouring channels, it is discarded or becomes an actual cluster.
  \item \textbf{Neighbour threshold:}
    The neighbour threshold is set to the lowest level of the three.
    Starting from the channel that exceeds the seed threshold, the cluster algorithm scans the adjacent channels for signal amplitudes above (at least) the neighbour threshold.
    This process continues in both directions until no more channels exceeding the neighbour threshold are found.
    At least one adjacent channel above the neighbour threshold is required for a potential cluster to become an actual cluster.
    All the channels that were collected along the way are considered to be part of the cluster.
  \item \textbf{High threshold:}
    The high threshold is set to the highest level of the three.
    If the signal amplitude not only exceeds the seed, but also the high threshold, it is considered an actual cluster.
    In this case, it is irrelevant whether there are adjacent channels above the neighbour threshold.
\end{itemize}
The clustering algorithm is illustrated in \vref{fig:clustering}.
To achieve a sufficient compression of the data, only the positions of formed clusters are transmitted over the optical links.
The position of a cluster $\bar{x}$ is calculated as the weighted arithmetic mean
\begin{equation}
  \bar{x} = \left. \sum\limits_{i=1}^n w_i x_i \middle/ \sum\limits_{i=1}^n w_i \right.
\end{equation}
with the involved channel indices $x_i$ and corresponding weights $w_i$ that depend on the exceeded threshold values.

However, the weighted mean is only used for clusters that involve up to four channels.
Larger clusters are internally split into multiple fragments.
Once one fragment contains four channels, a new fragment is created.
These types of clusters are flagged and two positions are transmitted: the (unweighted) arithmetic mean of the first and the last cluster fragment.
With a mean cluster size of \num{2.5}, up to \qty{10}{\percent} of the clusters involve four or more channels.
Hits of particles that are relevant for physics analyses mostly involve only up to four channels, while larger clusters typically originate from (secondary) particles at high angles, noise, or delta rays.
To avoid biases in the position due to these effects, the distinction between large and small clusters is made~\autocite{clustering-note}.


\subsubsection{Data Format}
\label{sec:dataformat}

\begin{table}
  \centering
  \caption{
    General data format as used in the \scifitracker{}.
    It consists of a 20-bit header along with a 92-bit payload containing the calculated cluster positions.
  }
  \label{tab:dataformat-ff}
  \begin{tabular}{@{}crl@{}}
    \toprule
                                                                         & Bit(s)  & Description                                                   \\ \midrule
    \parbox[t]{1mm}{\multirow{5}{*}{\rotatebox[origin=c]{90}{Header}}}   & 111:100 & Bunch crossing ID. Ranges from 0 to 3653.                     \\
                                                                         & 99      & Raw data flag. Set to 0 in case of cluster data.              \\
                                                                         & 98      & Parity bit of the 19 other header bits.                           \\
                                                                         & 97      & TFC flag. Set to 1 at arrival of control command(s).          \\
                                                                         & 96:92   & Number of formed clusters.                                     \\ \midrule
     \parbox[t]{1mm}{\multirow{6}{*}{\rotatebox[origin=c]{90}{Payload}}} & 91:90   & Reserved.                                                     \\
                                                                         & 89:81   & Position information of the 1st formed cluster (if existing).  \\
                                                                         & 80:72   & Position information of the 2nd formed cluster (if existing).  \\
                                                                         & ...     & ...                                                            \\
                                                                         & 17:9    & Position information of the 9th formed cluster (if existing).  \\
                                                                         & 8:0     & Position information of the 10th formed cluster (if existing). \\ \bottomrule
  \end{tabular}
\end{table}

After the clustering, the data needs to be formatted and serialised in preparation for the transmission via the optical fibres.
The corresponding block in the Cluster FPGA operates at a clock frequency of \qty{80}{\mega\hertz}.
Along with the calculated cluster positions, it receives the time-sensitive commands from the control system.
The available information is encoded in a 112-bit data frame for each bunch crossing period.
Depending on the location of the ROB within the detector, and the mode in which it is operated, different formats are used.

The general data format is shown in \vref{tab:dataformat-ff}.
It consists of a 20-bit header and 92-bit payload.
Within the header, 12 bits are used to label the bunch crossing ID of the current event.
It ranges from 0 to 3653 (incl.) and is required to time-align the incoming data from a total of \num{4096} optical fibres from the \scifitracker{} at the DAQ servers.
The number of formed clusters in the event is encoded as 5 bits.
The remaining 3 bits in the header comprises additional meta information and are still subject to change.

The payload contains the calculated positions of the formed clusters.
Each cluster is assigned a 9-bit number.
The determined position itself is encoded in 8 of the 9 bits.
Since each Cluster FPGA processes the output of \num{128} PACIFIC channels, the position within the SiPM array can thereby be encoded in \num{0.5}-channel steps.
For large clusters involving more than four channels, bit 9 is set to 1 and sent along with the 8-bit position (unweighted arithmetic mean) of the last fragment of the cluster.
The position of the first fragment of the corresponding large cluster is encoded in the preceding 9 bits.

Since both the header and the payload are of fixed length, the general data format as shown in \vref{tab:dataformat-ff} is also referred to as Fixed header, Fixed payload (FF) format.
It is used in \qty{80}{\percent} of the ROBs during normal data taking periods.
The remaining ROBs are operated in the so-called FV format with a fixed length header but a variable payload size.
This concerns \num{48} ROBs reading out the fibre modules that are directly surrounding the beam pipe.
Since these modules are experiencing the highest occupancies, having a payload of variable length allows to circumvent the limitation of ten clusters per event as it is the case for the FF data format.
The FV format uses a 32 events deep FIFO in the Cluster FPGA that allows unused space in low occupancy events to be filled with the data of previous events containing a large number of hits~\autocite{clusterboard-manual}.

In addition, a modified FF data format exists that is used for debugging and calibration purposes.
In these cases, the payload contains the raw 2-bit outputs of the PACIFIC channels instead of the cluster positions.
However, the 92-bit payload is not sufficient to hold the raw data of the \num{128} associated channels.
Therefore, it requires multiple 112-bit data frames to transmit a single event, which means that it does not allow for a readout of the detector at the full rate of \qty{40}{\mega\hertz}.
This type of data is for instance required for performing threshold scans in order to calibrate the PACIFIC comparators (see \cref{sec:th_scan}).

Independent of the format, the data frames are sent to the \MB{} via 28 differential outputs.
To allow for the transmission of the 4 bits per line and bunch crossing period of \qty{25}{\nano\second}, the data is serialised at both edges (DDR) of the underlying \qty{80}{\mega\hertz} clock.



\section{Master Board}
The \MB{} (MB) presents the interface between the SciFi front-end electronics and the DAQ system at the opposite side of the optical links.
The basis of the \MB{} consists of a 16-layer PCB with a nominal thickness of \qty{2.15}{\milli\meter}~\autocite{masterboard-manual}.
With a length of \qty{132.5}{\milli\meter} and width of \qty{256.2}{\milli\meter} it directly connects to four adjacent \qty{60}{\milli\meter} wide Cluster-PACIFIC Board pairs~\autocite{mb-edms}.
As shown in the exploded view in \vref{fig:mb}, it houses various components that allow for the data transmission and communication with the back-end, as well as for providing power to the PACIFIC and Cluster Boards.

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/MB}
  \caption{
    Exploded view of a Master Board showing the various mounted components.
    Image modified from Ref.~\autocite{mb-edms}.
  }
  \label{fig:mb}
\end{figure}

A total of eight dedicated chips, the so-called Data GBTX ASICs, receive the data from the eight Cluster FPGAs and encode it into the GBT protocol that is used for transmission over the optical links~\autocite{gbt-project}.
Another ASIC of the same type, the Master GBTX, operates in a different mode that allows for the bidirectional communication with the back-end electronics.
The \MB{} features an additional FPGA that is referred to as Housekeeping (HK) FPGA.
It enables the operation of the light injection system (see \cref{sec:lis}) and is responsible for the monitoring of different Master GBTX status registers.

On each board, 13 FEASTMP \DCDC{} converters~\autocite{feastmp} transform the \qty{8}{\volt} input voltage provided by the MARATON power supplies (see \cref{sec:lv}) into four different voltage levels required by the various components, including the ones mounted on the PACIFIC and Cluster boards.
In addition, a 26-pin D-SUB connector is installed on the board and connects to the CAEN modules (see \cref{sec:hv}) for biasing of the 16 associated SiPM dies.
Monitoring of the board temperature is enabled by eight NTC thermistors\footnote{B57301V2472H060 by TDK Electronics} mounted on different positions.


In the following, the key components of the \MB{} are discussed in more detail.


\subsection{Master GBTX}
\label{sec:master-gbtx}
The Master GBTX is essential for the operation of the SciFi front-end electronics as it is responsible for the communication with the back-end~\autocite{gbtx}.
Same as the GBT-SCA covered in \cref{sec:cluster-sca}, the underlying GBTX ASIC is part of the GBT project~\autocite{gbt-project}.
In order to establish the bidirectional optical link, it is operated in close conjunction with two other chips of the GBT project.

The downlink is realised by connecting to a GigaBit Trans-Impedance Amplifier (GBTIA) ASIC.
The GBTIA amplifies and converts the weak photocurrent provided by the PIN diode that is detecting the incoming light through the optical fibre~\autocite{gbtia}.
The resulting digital differential voltage is received by the input stage of the GBTX.
Based on the data stream, a clock and data recovery (CDR) circuit recovers and generates the required \qty{4.8}{\giga\hertz} clock to correctly sample the data.
Afterwards, the data is deserialised.

The uplink connection is enabled by a GigaBit Laser Driver (GBLD) ASIC~\autocite{gbld}.
It receives the serialised data from the GBTX and drives a \qty{850}{\nano\meter} vertical-cavity surface-emitting laser (VCSEL) accordingly.
Parameters of the GBLD like bias and modulation currents can be modified via a simplified \IIC{} master within the GBTX.
It is solely designed for this purpose and therefore cannot be used for the communication with other \IIC{} devices.

Both the receiving part consisting of the GBTIA ASIC and PIN diode, as well as the transmitting part comprising the GBLD chip and VCSEL are embedded into a single device that is referred to as Versatile Transceiver (VTRx).
While the design work of the two associated ASICs was carried out in the framework of the GBT project, the VTRx is part of the Versatile Link project at the LHC~\autocite{versatile-link-project}.

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/GBT_Dataformat}
  \caption{
    Structure of the 120-bit GBT frame as used in the Master GBTX for communication with the back-end electronics.
    It consists of a 4-bit header, 2-bit internal and external slow control fields (IC and EC), 80 bits of data, and 32 bits used for a Forward Error Correction (FEC) code.
  }
  \label{fig:gbt_dataformat}
\end{figure}

A GBT frame consists of 120 bits that are exchanged in each bunch crossing period (\qty{25}{\nano\second}) resulting in the total data rate of \qty{4.8}{\giga\bit/\second}.
The frame structure is illustrated in \vref{fig:gbt_dataformat}.
Each GBT frame is led by a 4-bit header that is required to synchronise the data stream at the frame level~\autocite{gbtx-manual}.
Repeated recognition of the header results in a valid synchronisation, also referred to as frame-locking.
Another 4 bits are reserved for slow control operations, which are split into internal and external control (IC and EC).
The 2-bit IC field is used for the internal control of the GBTX itself and can be used to access a total of \num{366} read/write and \num{70} read-only registers.
The 2-bit EC field is reserved for the implementation of an external slow control application, e.g. a separate GBT-SCA chip.
In case of the Master GBTX, this field with an associated bandwidth of \qty{80}{\mega\bit/\second} is used for the communication with the Master SCA (see \cref{sec:master-sca}).
The largest fraction of the GBT frame is allocated to an 80-bit data (D) field that can be used flexibly for the transmission of physics data, trigger signals and slow control commands.
The unified handling of these three functions is one of the greatest strengths of the GBT architecture.
In case of the Master GBTX, \numproduct{4 x 2} bits within the data field are used for the communication with the four associated Cluster SCAs (see \cref{sec:cluster-sca}).
Another \numproduct{8 x 8} bits are allocated for trigger signals going to the eight Cluster FPGAs (see \cref{sec:cluster-fpga}) within each HalfROB.
An additional \num{2} bits within the data field are reserved for the control of the light injection system via the HK FPGA (see \cref{sec:lis}).

The remaining 32 bits are required for the implementation of a Forward Error Correction (FEC) code.
It is based on two interleaved Reed-Solomon RS(15,11) encoded words with 4-bit symbols~\autocite{reed-solomon}.
With a coding efficiency of \qty{70}{\percent}, it is capable of correcting bursts of 16 consecutive incorrectly transmitted bits~\autocite{gbtx-manual}.
The FEC is combined with a pseudorandom, self-synchronising scrambling algorithm to achieve a DC-balanced data transmission~\autocite{gbt-scrambling}.
DC-balanced signals contain an even distribution of 0s and 1s in order to prevent bit errors that can occur otherwise after a long series of the same bit state (caused for instance by unwanted charging of the coupling capacitor).

The electrical connection of the GBTX chip with the various front-end devices is realised by so-called E-Links.
In the standard configuration, one E-Link is built from three differential signal pairs: downlink and uplink data, as well as a differential clock line.
However, not all three signal pairs have to be implemented in every application.
In addition, the E-Links offer a high flexibility in terms of the used data rate, which can be selected between \num{80}, \num{160} or \qty{320}{\mega\bit/\second} resulting in \num{2}, \num{4} or \num{8} assigned bits in the GBT frame, respectively.
Even higher bandwidths can be achieved by configuring multiple data lines in parallel.

In addition to the E-Links, the GBTX implements a clock manager circuit that provides eight external user clocks with programmable phases and frequencies.
The clock frequency can be independently selected between \num{40}, \num{80}, \num{160} and \qty{320}{\mega\hertz}, while the phase can be varied in \qty{50}{\pico\second} steps.
In case of the Master GBTX, the eight external clocks are set to the system frequency of \qty{40}{\mega\hertz} and are provided as reference clocks to the eight Data GBTX ASICs (see \cref{sec:data-gbtx}).


\subsection{Master SCA}
\label{sec:master-sca}

The Master SCA connects to the \qty{80}{\mega\bit/\second} E-Link of the Master GBTX that is assigned to the EC field.
It is based on the identical GBT-SCA chip employed in the Cluster SCA.
General remarks about the GBT-SCA ASIC can be found in \cref{sec:cluster-sca}.

On the \MB{}, the SCA utilises ten of the available \IIC{} master interfaces for the control of the eight Data GBTX ASICs, as well as the HK FPGA and light injection system.
Re-programming of the HK FPGA is enabled via the SCA's JTAG interface, or alternatively the SPI, which is connected as a reserve.
Eight ADC inputs are allocated to monitor the temperature of the PCB using the eight NTC thermistors mounted on the board.
An additional ADC line is used to measure the input (low) voltage.

All of the 32 available GPIO pins are in use.
They are set up as 15 output and 17 input lines.
Four inputs are indicating the connectivity to the four Versatile Twin Transmitter (VTTx) modules (see \cref{sec:data-gbtx}).
The remaining input pins are responsible for the monitoring of the power-good signals from the 13 FEASTMP \DCDC{} converters.
The \DCDC{} converters are arranged in four sections.
One section is always enabled, providing power to the essential components that are required for the communication with the back-end: the Master SCA itself, the Master GBTX, and the VTRx module.
The remaining three sections can be controlled with the help of three GPIO output lines.
Like this, it is possible to independently power on/off the left and right half of the \MB{} including the associated Cluster and PACIFIC Boards, as well as the \qty{3.3}{\volt} \DCDC{} converter that is powering the Cluster FPGAs.
Reset signals going to the Data GBTX ASICs and the HK FPGA (soft, hard and JTAG reset) are driven by 11 output pins and an additional line can be used to disable the light injection system.


\subsection{Data GBTX}
\label{sec:data-gbtx}
Unlike the Master GBTX that is configured for bidirectional communication with the back-end, the eight Data GBTX ASICs mounted on the \MB{} only provide an uplink data stream.
Therefore, instead of recovering the clock from the optical link, they receive the \qty{40}{\mega\hertz} reference clock from the Master GBTX.
In addition, the internal registers of the Data GBTX are accessed via \IIC{} from the Master SCA.

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/GBT_Dataformat_Widebus}
  \caption{
    Structure of the 120-bit GBT frame in wide mode as used in the Data GBTX for transmission of the physics data.
    In the wide frame mode, the Forward Error Correction (FEC) is omitted in exchange for additional bandwidth.
    For compatibility reasons, the allocation of the first 80 bits in the data field is identical to the default GBT frame structure depicted in  \cref{fig:gbt_dataformat}.
  }
  \label{fig:gbt_dataformat_wide}
\end{figure}


As discussed in \cref{sec:dataformat}, the data transmission from the Cluster FPGA takes place via 28 differential E-Link data lines each operating at \qty{160}{\mega\bit/\second}.
Thereby, each Data GBTX receives a data frame consisting of 112 bits per bunch crossing interval.
As this exceeds the available bandwidth in the default GBT frame structure presented in \cref{fig:gbt_dataformat}, a different format for the optical data transmission to the back-end has to be used.
Therefore, the Data GBTX ASICs are operating in the GBT wide frame mode.
As illustrated in \vref{fig:gbt_dataformat_wide}, the available data field is extended to 112 bits in this mode.
However, no protection against transfer errors is available as the FEC field is traded for the additional \qty{40}{\percent} bandwidth.

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/Datachain}
  \caption{
    Data stream and corresponding bandwidths between the different components of the SciFi front-end electronics.
    In total, \num{4096} instances of the shown chain are present in the detector, resulting in a total data rate of about \qty{20}{\tera\bit/\second} arriving at the back-end.
  }
  \label{fig:datachain}
\end{figure}

The Data GBTX marks the last stage of the data chain, before being transmitted over the optical fibres to the back-end.
A summary of the complete chain within the SciFi front-end electronics is pictured in \vref{fig:datachain}.
The following optical transmission of the data is realised by four Versatile Twin Transmitter (VTTx) modules~\autocite{versatile-link-application-note}.
The package is identical to the VTRx modules, but, to address the typical need for asymmetric bandwidth in HEP experiments, the optical receiver is replaced with an additional transmitter channel.
Thereby, two neighbouring Data GBTX ASICs share one VTTx module.

Five of the eight external user clocks of each Data GBTX are utilised and provided to the various stages in the data chain, ranging from \qty{40}{\mega\hertz} as required by the clustering block to \qty{320}{\mega\hertz} used for the operation of the PACIFICs.
Their phases have to be carefully adjusted to each other to ensure a stable and reliable data transfer over the complete chain.
Further details about this tuning process is given in \cref{sec:timing_scans}.


\section{Light Injection System}
\label{sec:lis}
The light injection system (LIS) is a critical component for the proper functioning of the \scifitracker{}.
It enables the calibration of the individual channels by artificially injecting light into the scintillating fibres close to the SiPMs while performing the PACIFIC threshold scans (see \cref{sec:th_scan}).

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/LIS}
  \caption{
    Schematic illustration of a fully assembled detector module including the light injection system.
    Image adapted from Ref.~\autocite{lis}.
  }
  \label{fig:lis}
\end{figure}

As shown in \vref{fig:lis}, the main part of the LIS is located within the end plugs of the fibre modules.
It consists of a \qty{670}{\nano\meter} VCSEL and a plastic optical fibre that guides the emitted light towards the fibre mat end piece.
The last \qty{13}{\centi\meter} of the optical fibre, matching the width of the fibre mat, is embedded into an aluminium bar that is referred to as light injection bar.
Along that length, the fibre is scratched allowing light to escape.
Subsequently, the escaped photons travel through the transparent end piece, enter the scintillating fibres, and finally reach the SiPM channels.

The VCSEL is driven by an external GBLD, the same chip that is used in the transmitter channels of the VTRx and VTTx modules.
A pair of two GBLDs and two VCSELs is mounted on a 6-layer PCB~\autocite{lis}.
Each fibre module is equipped with two of these boards in order to illuminate the four fibre mats contained within.
A \qty{28}{\centi\meter} long flex cable is guided along the surface of the fibre module and connects the LIS PCB with the \MB{} via a 20-pin low-profile connector\footnote{TLH-010-0.50-G-D-A by Samtec, Inc.}.

Operational settings of a GBLD pair, like bias and modulation currents, can be accessed from the Master SCA via \IIC{} (see \cref{sec:master-sca}).
The input signal to the GBLDs, in the following referred to as LIS pulse, is provided by the HK FPGA and determines the delay and duration of the resulting light pulse.
The generation of the LIS pulse is based on a dedicated calibration command from the control system.
Unlike the slow control commands, the so-called CalibC pulse is a time-sensitive signal that can be issued in a particular bunch crossing period and thus be shifted in steps of \qty{25}{\nano\second}.
As part of the GBT frame, it is received by the Master GBTX and provided to the HK FPGA via a dedicated E-Link.

However, as discussed previously in \cref{sec:pacific_processing}, finer tuning of the LIS pulse other than the \qty{25}{\nano\second} steps is required in order to align it with respect to the \mbox{PACIFIC} integration intervals.
For that purpose, two unused external user clocks with programmable phase and frequency that are available in one of the Data GBTX ASICs are utilised.
They are denoted as the start and stop clock and are set to the lowest possible frequency, i.e. to \qty{40}{\mega\hertz}.
The generation of the LIS pulse is based on the interplay of the different signals and illustrated in the timing diagram in \vref{fig:lis-timing-diagram}.

\begin{figure}
  \centering
  \includegraphics[width=1.0\textwidth]{figures/fee/LIS_Timing_Diagram}
  \caption{
    Timing diagram of the LIS pulse generation in the HK FPGA.
    The system clock and CalibC pulse are received from the Master GBTX.
    The start and stop clocks are provided by the third Data GBTX on the \MB{}.
  }
  \label{fig:lis-timing-diagram}
\end{figure}

Upon arrival of the CalibC pulse, the first rising edge of the start clock defines the start of the LIS pulse.
Similarly, the following rising edge of the stop clock marks the end of the resulting pulse.
Like this, it is possible to vary the delay of the LIS pulse in very fine steps (\qty{50}{\pico\second}) by shifting the phases of the two clocks equally.
In addition, the width of the pulse and thereby the light intensity can be adjusted by only shifting the phase of the stop clock.
However, given the underlying clock frequencies of \qty{40}{\mega\hertz}, both the delay and duration of the pulse can only be adjusted within a range of \qty{25}{\nano\second}.
In case of the delay, this is accounted for by issuing the CalibC command in the previous or following bunch crossing period.
LIS pulse widths larger than \qty{25}{\nano\second} are typically not required but are still possible by instructing the HK FPGA to skip a certain amount of stop clock edges, thereby effectively increasing the width in steps of \qty{25}{\nano\second}.

In practice, the delay and width can not be varied freely over the entire dynamic range of \qty{25}{\ns}, which can become an issue in particular for the delay, if the best timing happens to be out of reach.
The reason for this is that when the clock and CalibC edges are too close to each other ($< \qty{1}{\nano\second}$), due to jitter, the order of the signals is not guaranteed.
The result is an unstable pulse that shows jumps by about \qty{25}{\nano\second} in either delay or width.
In case of the width, the unstable configurations are simply avoided and compensated by changing the modulation current of the GBLD to tune the light intensity.
However, no alternative method is available for changing the delay of the LIS pulse.
Therefore, a mechanism was implemented that allows for the clocking of the CalibC signal by the falling edge of the system clock instead of the rising edge, thereby effectively shifting it by \qty{12.5}{\nano\second}.
In principle, this allows for a range of the pulse delay of \qty{37.5}{\nano\second}, which is still covering the full \qty{25}{\ns} bunch crossing period when avoiding the configurations around the edges.

To validate the LIS pulse generation, the output light pulse was measured with the help of a PIN diode and an oscilloscope using different delays and widths of the generated LIS pulse.
\Vref{fig:lis-osci} shows the signal from the PIN diode, as well as the LIS and CalibC pulse, which was used as the trigger.
In addition, the measured light pulses with different delay and width configurations are displayed, demonstrating a proper functioning of the LIS and its tuning mechanisms as described previously.

\begin{figure}
  \begin{subfigure}{1.0\linewidth}
    \centering
    \includegraphics[width=1.0\textwidth]{figures/fee/LIS_Oscilloscope}
    \caption{Overview}
  \end{subfigure}\\[1ex]
  \begin{subfigure}{0.49\linewidth}
    \centering
    \includegraphics[width=1.0\textwidth]{figures/fee/LIS_Oscilloscope_Delays}
    \caption{Different pulse delays}
  \end{subfigure}
  \hfill
  \begin{subfigure}{0.49\linewidth}
    \centering
    \includegraphics[width=1.0\textwidth]{figures/fee/LIS_Oscilloscope_Widths}
    \caption{Different pulse widths}
  \end{subfigure}

  \caption{
    Validation of the LIS pulse generation using an oscilloscope and a PIN diode that measures the output light of the VCSEL.
    The top image (a) shows the three probed signals.
    The bottom images display the measured PIN diode voltages for different LIS pulse delays (b) and widths (c).
    The CalibC pulse appears later as it was probed on a separate setup due to difficult accessibility at the LIS itself.
    Nevertheless, it serves as a reference signal and was used as the trigger for the oscilloscope.
  }
  \label{fig:lis-osci}
\end{figure}

Besides from enabling the calibration of the detector, the LIS also plays an important role for the commissioning of the front-end electronics as it allows to identify malfunctioning channels.
Further details about the usage of the LIS in the commissioning is given in \cref{sec:lis-tests}.



\section{Quality Assurance}
\label{sec:qa}
After production, the individual front-end electronics components undergo different quality assurance (QA) tests to ensure proper functioning.
These include standard test procedures of the assembled PCBs like
\begin{itemize}
  \setlength\itemsep{0em}
  \item 3D Automated Optical Inspection (3D AOI)
  \item Automated X-ray Inspection (AXI)
  \item Flying Probe Testing (FPT)
  \item Temperature Cycle Testing (TCT)
\end{itemize}
that are mainly conducted on-site at the production companies.
Additionally, for some parts, extended functional tests are performed at the institutes within the SciFi collaboration~\autocite{lis,fee-qa}.

The QA of the \PB{}s is conducted at Tsinghua University and the University of Valencia.
Within a custom designed test DAQ developed at Heidelberg University, each board has to pass a series of tests.
Starting with a check of the power consumption, it is ensured that the communication via \IIC{} and the digital input signals are operational.
As one of the last steps, the DC baselines of the two integrators per channel are aligned (trimming) and the obtained parameters (trim DACs) are saved along with the ID of the board.
Further details about the trimming procedure are given in \cref{sec:trimming}.
Prior of being mounted on a \PB{}, each PACIFIC ASIC also undergoes an individual test sequence.
%Besides from similar checks as performed on the board-level described before, the reference voltages $V_\text{REF}$ and $V_\text{refDCFB}$ are tuned to match their intended values of \qty{0.5}{\volt} and \qty{0.7}{\volt} in the process.
Besides from similar checks as performed on the board-level described before, the reference voltages are tuned in the process to match their intended values.

In case of the \CB{}, the assembled PCBs are examined at LPC in Clermont-Ferrand.
Within a dedicated setup, two boards are tested in parallel.
The procedure includes the injection and evaluation of test patterns, monitoring the current consumption, as well as testing the functionalities of the GBT-SCA.
Furthermore, the programmability of the Cluster FPGAs is ensured.

At RWTH Aachen, the test setup for the LIS components is located.
Therein, the operational settings for the bias ($I_\text{bias}$) and modulation currents ($I_\text{mod}$) of the GBLDs and VCSELs are determined in order to achieve a predefined light intensity.
These values are of crucial importance for the calibration of the PACIFIC threshold DACs (see \cref{sec:th_scan}) that is required to take high quality physics data.
Therefore, a further fine-tuning of $I_\text{bias}$ and $I_\text{mod}$ is performed on the LHCb site at CERN during the QA of the fully assembled fibre modules including LIS, cold boxes and SiPMs.

Apart from the tests at the production company, the \MBs{} do not undergo individual testing but are examined in conjunction with the remaining boards:
In a dedicated setup on the LHCb site, every assembled ROB is thoroughly tested in its final configuration including being readout via the optical links.
Further details about the test-stand and procedure are given in \cref{sec:fe-tester}.

The test results of the different QA steps are saved in a dedicated database hosted at Heidelberg University~\autocite{scifi-db}.
This includes in particular the individual operation parameters required for the later operation of the detector that are obtained during the tests.
