117 lines
4.5 KiB
Verilog
117 lines
4.5 KiB
Verilog
// megafunction wizard: %LPM_DIVIDE%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: LPM_DIVIDE
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// ============================================================
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// File Name: div.v
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// Megafunction Name(s):
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// LPM_DIVIDE
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//
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// Simulation Library Files(s):
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// lpm
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2019 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and any partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details, at
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//https://fpgasoftware.intel.com/eula.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module div (
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clken,
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clock,
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denom,
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numer,
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quotient,
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remain);
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input clken;
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input clock;
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input [29:0] denom;
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input [39:0] numer;
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output [39:0] quotient;
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output [29:0] remain;
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wire [39:0] sub_wire0;
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wire [29:0] sub_wire1;
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wire [39:0] quotient = sub_wire0[39:0];
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wire [29:0] remain = sub_wire1[29:0];
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lpm_divide LPM_DIVIDE_component (
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.clken (clken),
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.clock (clock),
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.denom (denom),
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.numer (numer),
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.quotient (sub_wire0),
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.remain (sub_wire1),
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.aclr (1'b0));
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defparam
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LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED",
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LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
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LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
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LPM_DIVIDE_component.lpm_pipeline = 26,
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LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
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LPM_DIVIDE_component.lpm_widthd = 30,
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LPM_DIVIDE_component.lpm_widthn = 40;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
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// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
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// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
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// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
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// Retrieval info: PRIVATE: new_diagram STRING "1"
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// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
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// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
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// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
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// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "26"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
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// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "30"
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// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "40"
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// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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// Retrieval info: USED_PORT: denom 0 0 30 0 INPUT NODEFVAL "denom[29..0]"
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// Retrieval info: USED_PORT: numer 0 0 40 0 INPUT NODEFVAL "numer[39..0]"
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// Retrieval info: USED_PORT: quotient 0 0 40 0 OUTPUT NODEFVAL "quotient[39..0]"
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// Retrieval info: USED_PORT: remain 0 0 30 0 OUTPUT NODEFVAL "remain[29..0]"
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// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @denom 0 0 30 0 denom 0 0 30 0
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// Retrieval info: CONNECT: @numer 0 0 40 0 numer 0 0 40 0
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// Retrieval info: CONNECT: quotient 0 0 40 0 @quotient 0 0 40 0
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// Retrieval info: CONNECT: remain 0 0 30 0 @remain 0 0 30 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL div.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL div.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL div.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL div.bsf TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL div_inst.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL div_bb.v FALSE
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// Retrieval info: LIB_FILE: lpm
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