328 lines
10 KiB
Verilog
328 lines
10 KiB
Verilog
/******************************************************************************
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* Copyright *
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* Scintillating Fibre Beam Profile Monitor Software by Michal Dziewiecki, *
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* Blake Leverington and Liqing Qin is licensed under CC BY 4.0 *
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* https://creativecommons.org/licenses/by/4.0/ *
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* funded by the Deutsche Forschungsgemeinschaft *
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* (DFG, German Research Foundation) Projektnummer 419255448 *
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* Project Leader: B.Leverington *
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*******************************************************************************
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* Create Date - Oct 15th. 2024 *
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* Author: L.Qin *
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* Module - bkg_subtraction_pipe.v *
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******************************************************************************/
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/*Created by Lq.Qin on Oct 15th. 2024*/
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//background subtraction module
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//tested with algo_top_cl_cali_tb.v with bkg_subtraction_pipe
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//tested with bkg_subtraction_pipe_tb
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//okay... it is not really pipe.... has to read a ram after use the previous output of this ram
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module bkg_subtraction_pipe #(parameter BKG_FRAME = 4)(
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//clock and reset
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input wire clk,
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input wire rst, // connect to rst_run
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//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence // 163 word = 3 header + 160 data
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input wire [31:0] data_in_data, // st.data
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output wire data_in_ready, // .ready
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input wire data_in_valid, // .valid
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input wire [1:0] data_in_empty, // .empty
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input wire data_in_endofpacket, // .endofpacket
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input wire data_in_startofpacket, // .startofpacket
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//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //160 word only with data
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output wire [31:0] data_out_data, // st.data
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input wire data_out_ready, // .ready
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output wire data_out_valid, // .valid
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output wire [1:0] data_out_empty, // .empty
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output wire data_out_endofpacket, // .endofpacket
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output wire data_out_startofpacket, // .startofpacket
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output wire bkg_sub_on,
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//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //3 headers
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output wire [31:0] to_udp_data, // st.data
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input wire to_udp_ready, // .ready
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output wire to_udp_valid, // .valid
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output wire [1:0] to_udp_empty, // .empty
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output wire to_udp_endofpacket, // .endofpacket
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output wire to_udp_startofpacket // .startofpacket
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//output rst_frame // I have to think about this rst_frame when is a good timing! or do I need it? 26.June. 2024
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);
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localparam SHIFT_BIT = $clog2(BKG_FRAME);
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wire rst_frame = data_in_startofpacket;
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wire data_out_ready_for3header = to_udp_ready;
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/************************* Frame Counter***********************************/
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/*
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This is a frame counter;
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frameID +1 at the rising edge of data_in_startofpacket
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if frame increase at 10kHz, the 27-bit frameID can count 3.72 hour frame
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*/
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reg [26:0] frameID;
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reg data_in_startofpacket_last;
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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begin
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data_in_startofpacket_last <= 1'b0;
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frameID<= 27'b0;
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end
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else
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begin
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data_in_startofpacket_last <= data_in_startofpacket;
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if (~data_in_startofpacket_last && data_in_startofpacket)
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frameID<= frameID + 1'b1;
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end
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end
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//**********************bkg_subtraction or not *****************
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reg[1:0] state_bkg;
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localparam STATE_BKG_IDLE = 0;
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localparam STATE_RAM_RST = 1;
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localparam STATE_BKG_ADD = 3;
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localparam STATE_BKG_OUT = 2;
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assign bkg_sub_on = (state_bkg == STATE_BKG_OUT)? 1'b1:1'b0;
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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state_bkg <= STATE_BKG_IDLE;
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else if (frameID <=27'd1)
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state_bkg <= STATE_RAM_RST;
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else if (frameID >BKG_FRAME+1)
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state_bkg <= STATE_BKG_OUT;
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else
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state_bkg <= STATE_BKG_ADD;
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end
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/************** bkg RAM ****************************/
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/*
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for prepare the bkg signal by two RAM;
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one for data_in_data[31:16]; the other for data_in_data[15:0]
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the signal after bkg subtraction is 16 bit signed; the LSM bit is dropped out; (it's not important with current noise level)
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*/
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reg[8:0] rdaddress; //for read ram
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reg[8:0] wraddress;
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wire wren;
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//data_in_data + ram0_q
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reg[31:0] ram0_data;
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reg[31:0] ram1_data;
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wire[31:0] ram0_q;
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wire[31:0] ram1_q;
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ram4bkg ram4bkg0 (
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.data(ram0_data), //32 bits
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.rdaddress(rdaddress),
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.clock(clk),
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.wraddress(wraddress),
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.wren(wren),
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.q(ram0_q) //32 bits
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);
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ram4bkg ram4bkg1 (
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.data(ram1_data), //32 bits
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.rdaddress(rdaddress),
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.clock(clk),
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.wraddress(wraddress),
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.wren(wren),
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.q(ram1_q) //32 bits
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);
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wire[15:0] bkg0;
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wire[15:0] bkg1;
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assign bkg0 = bkg_sub_on?ram0_q[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
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assign bkg1 = bkg_sub_on?ram1_q[SHIFT_BIT+15:SHIFT_BIT]:16'b0;
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//data_in_data - bkg0
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reg[16:0] data0_sub;
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reg[16:0] data1_sub;
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//data_in_data
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wire[15:0] data0_in_data;
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wire[15:0] data1_in_data;
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//reverse the polarity of ADC signal for calculation => no for simulation
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assign data0_in_data = ~data_in_data[31:16];
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assign data1_in_data = ~data_in_data[15:0];
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// *********************** ST interface ***********************
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reg [3:0] state; //State of the state machine
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localparam STATE_IDLE = 4'd0; //waiting for SOP
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localparam STATE_WORD0 = 4'd1; //sending first word :
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localparam STATE_WORD1 = 4'd2; //sending second word:
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localparam STATE_WORD2 = 4'd3; //sending third word :
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localparam STATE_RDRAM0 = 4'd4; //wait to read the first channel of ram
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localparam STATE_INPUT0 = 4'd5; //data_in_ready do sub and sum
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localparam STATE_RDRAM1 = 4'd6; //data_in_data is ready to output, data_out_startofpacket is high; read next ram
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localparam STATE_INPUT = 4'd7; //data_in_ready do sub and sum for next
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localparam STATE_RDRAM = 4'd8;
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localparam STATE_OUTPUT_LAST = 4'd9; //output last, data_out_endofpacket is high
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localparam STATE_LOC = 4'd10; //
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wire state_bkg_valid;
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wire state_data_valid;
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// Check if state_bkg is either STATE_RAM_RST or STATE_BKG_ADD for write
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assign state_bkg_valid = (state_bkg == STATE_RAM_RST) || (state_bkg == STATE_BKG_ADD);
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// Check if state is STATE_DATA and both data_in_valid and data_out_ready are true
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assign state_data_valid = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST);
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// Final wren assignment combining the conditions
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assign wren = (state_bkg_valid && state_data_valid)? 1'b1 : 1'b0;
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//The state machine
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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begin
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state <= STATE_IDLE;
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end
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else
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case(state)
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STATE_IDLE:
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begin
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rdaddress <= 0;
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wraddress <= 0;
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if (data_in_startofpacket)
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begin
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state <= STATE_WORD0;
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end
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end
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STATE_WORD0:
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begin
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if (data_in_valid && data_out_ready_for3header)
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begin
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state <= STATE_WORD1;
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end
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end
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STATE_WORD1:
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begin
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if (data_in_valid && data_out_ready_for3header)
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begin
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state <= STATE_WORD2;
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end
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end
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STATE_WORD2:
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begin
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if (data_in_valid && data_out_ready_for3header)
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begin
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state <= STATE_RDRAM0;
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rdaddress <= 0;
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end
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end
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STATE_RDRAM0:
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begin
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state <= STATE_INPUT0;
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end
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STATE_INPUT0:
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begin
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if (data_in_valid)
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begin
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state <= STATE_RDRAM1;
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rdaddress <= rdaddress + 1'b1;
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data0_sub <= data0_in_data - bkg0;
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data1_sub <= data1_in_data - bkg1;
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if (state_bkg == STATE_BKG_ADD)
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begin
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ram0_data <= data0_in_data + ram0_q;
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ram1_data <= data1_in_data + ram1_q;
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end else
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begin
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ram0_data <= 0;
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ram1_data <= 0;
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end
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end
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end
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STATE_RDRAM1:
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begin
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if (data_out_ready)
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state <= STATE_INPUT;
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end
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STATE_INPUT:
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begin
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if (data_in_valid)
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begin
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if (data_in_endofpacket)
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state <= STATE_OUTPUT_LAST;
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else
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state <= STATE_RDRAM;
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rdaddress <= rdaddress + 1'b1;
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wraddress <= wraddress + 1'b1;
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data0_sub <= data0_in_data - bkg0;
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data1_sub <= data1_in_data - bkg1;
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if (state_bkg == STATE_BKG_ADD)
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begin
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ram0_data <= data0_in_data + ram0_q;
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ram1_data <= data1_in_data + ram1_q;
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end else
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begin
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ram0_data <= 0;
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ram1_data <= 0;
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end
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end
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end
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STATE_RDRAM:
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begin
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if (data_out_ready)
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state <= STATE_INPUT;
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end
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STATE_OUTPUT_LAST:
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begin
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if (data_out_ready)
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state <= STATE_LOC;
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end
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STATE_LOC:
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begin
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state <= STATE_IDLE;
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end
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default:
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begin
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state <= STATE_IDLE;
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end
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endcase
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end
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//output 160 words
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assign data_in_ready = ((state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2) && data_out_ready_for3header) || (state == STATE_INPUT) ||(state == STATE_INPUT0);
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assign data_out_valid = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST) ? 1'b1 : 1'b0;
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assign data_out_data = (state == STATE_RDRAM1 || state == STATE_RDRAM || state == STATE_OUTPUT_LAST)? (bkg_sub_on? {data0_sub[16:1],data1_sub[16:1]}: {data0_sub[15:0],data1_sub[15:0]}):0;
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assign data_out_startofpacket = (state == STATE_RDRAM1)? 1'b1: 1'b0;
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assign data_out_endofpacket = (state == STATE_OUTPUT_LAST) ? 1'b1 : 1'b0;
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assign data_out_empty = 0;
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//output the 3 header to upd
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assign to_udp_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:0;
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assign to_udp_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_valid: 1'b0;
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assign to_udp_empty = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_empty: 2'b0;
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assign to_udp_startofpacket = data_in_startofpacket;
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assign to_udp_endofpacket = (state == STATE_WORD2)?data_in_valid: 1'b0;
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endmodule
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