HITDAQ/FPGA_firmware
2024-10-29 16:18:41 +01:00
..
2024-10-16 10:07:43 +02:00
2024-10-16 10:07:43 +02:00
2024-10-11 14:49:54 +02:00
2024-10-11 14:49:54 +02:00
2024-10-29 16:18:41 +01:00
2024-10-15 14:03:00 +02:00
2024-10-16 10:07:43 +02:00
2024-10-11 14:49:54 +02:00
2024-10-16 10:07:43 +02:00
2024-10-15 14:03:00 +02:00
2024-10-11 14:49:54 +02:00

This firmware is generted from Simple Socket Server Example. 

M.Dziewiecki created sensor_interface.v in 2019, which controls, collects, and sends ADC data to ethernet.

L.Qin created algo_top_cl_cali_rms.v in 2024, which reconstructs the position and sigma from the ADC data.