77 lines
1.6 KiB
Verilog
77 lines
1.6 KiB
Verilog
//This is a testbench from the UDP generator
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`timescale 1 ns / 1 ns
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module serial_testbench();
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//Signals
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reg clk;
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reg rst;
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reg [8:0] tx_data;
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reg [7:0] clk_divisor;
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reg trigger;
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wire serdata;
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wire tx_idle;
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wire newdata;
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wire [8:0] rx_data;
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wire rx_error;
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wire rx_idle;
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initial
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begin
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clk = 0;
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rst = 1;
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tx_data = 9'h155;
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clk_divisor = 20;
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trigger = 0;
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#50
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rst = 0;
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#20
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trigger = 1;
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#20
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trigger = 0;
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#12000
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tx_data = 9'h05E;
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#20
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trigger = 1;
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#20
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trigger = 0;
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#20000
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$stop;
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end
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always #10 clk = ~clk;
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serial_tx the_tx (
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.clk (clk), // full-speed clock
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.rst (rst), // reset
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.data (tx_data), // data to send
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.clk_divisor (clk_divisor), // defines baudrate
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.trigger (trigger), // pulse to start transmission
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.tx (serdata), // tx serial connection
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.idle (tx_idle) // 1 if sender in idle state
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);
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serial_rx the_rx(
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.clk (clk), // full-speed clock
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.rst (rst), // reset
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.clk_divisor (clk_divisor), // defines baudrate
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.rx (serdata), // rx serial connection
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.newdata (newdata), // pulses for new data received
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.data (rx_data), // data to send
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.error (rx_error), // bad start or stop bit
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.idle (rx_idle)
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);
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endmodule |