131 lines
4.4 KiB
Verilog
131 lines
4.4 KiB
Verilog
//This is a testbench from the UDP generator
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`timescale 1 ns / 1 ns
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module sensor_testbench();
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//Signals
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reg clk_clk; // clk.clk
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reg rst_reset; // rst.reset
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reg [2:0] csr_address; // csr.address
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reg csr_write; // .write
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reg [31:0] csr_writedata; // .writedata
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reg [3:0] csr_byteenable; // .byteenable
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reg csr_read; // .read
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wire [31:0] csr_readdata; // .readdata
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wire [31:0] data_out_data; // data_out.data
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wire [1:0] data_out_empty; // .empty
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wire data_out_endofpacket; // .endofpacket
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wire data_out_startofpacket; // .startofpacket
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reg data_out_ready; // .ready
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wire data_out_valid; // .valid
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reg in_trg; // sensor.in_trg
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wire out_dac_clk; // .out_dac_clk
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wire out_dac_cnv; // .out_dac_cnv
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reg [4:0] in_adc_data; // .in_dac_data
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wire out_sensor_rst; // .out_sensor_rst
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wire out_sensor_clk; // .out_sensor_clk
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wire out_sensor_gain; // .out_sensor_gain
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wire serial;
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reg [7:0] ext;
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initial
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begin
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clk_clk = 0;
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rst_reset = 1;
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csr_address = 3'd0;
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csr_write = 0;
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csr_writedata = 32'd0;
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csr_byteenable = 4'b1111;
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csr_read = 0;
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data_out_ready = 1;
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in_trg = 0;
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in_adc_data = 5'b0;
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ext = 0;
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#50
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rst_reset = 0;
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//write 0xAAAA0032 to register 2
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#20
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csr_write = 1;
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csr_byteenable = 4'b1111;
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csr_address = 3'd2;
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csr_writedata = 32'hAAAA0032;
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#20
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csr_write = 0;
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//write 0x00040004 to register 1
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#20
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csr_write = 1;
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csr_byteenable = 4'b1111;
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csr_address = 3'd1;
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csr_writedata = 32'h00040004;
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#20
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csr_write = 0;
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//write 0x00060001 to register 0
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#20
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csr_write = 1;
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csr_byteenable = 4'b1111;
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csr_address = 3'd0;
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csr_writedata = 32'h00060001;
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#20
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csr_write = 0;
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#500000
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$stop;
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end
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always #10 clk_clk = ~clk_clk;
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always #20 in_adc_data = in_adc_data + 1; //dummy hay to ADCs
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always #50010 in_trg = ~in_trg;
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sensor_interface the_sensor_interface (
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.clk_clk (clk_clk), // clk.clk
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.rst_reset (rst_reset), // rst.reset
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.csr_address (csr_address), // csr.address
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.csr_write (csr_write), // .write
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.csr_writedata (csr_writedata), // .writedata
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.csr_byteenable (csr_byteenable), // .byteenable
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.csr_read (csr_read), // .read
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.csr_readdata (csr_readdata), // .readdata
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.data_out_data (data_out_data), // data_out.data
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.data_out_empty (data_out_empty), // .empty
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.data_out_endofpacket (data_out_endofpacket), // .endofpacket
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.data_out_startofpacket (data_out_startofpacket),// .startofpacket
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.data_out_ready (data_out_ready), // .ready
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.data_out_valid (data_out_valid), // .valid
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.in_trg (in_trg), // sensor.in_trg
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.out_adc_clk (out_adc_clk), // .out_dac_clk
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.out_adc_cnv (out_adc_cnv), // .out_dac_cnv
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.in_adc_data (in_adc_data), // .in_dac_data
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.out_sensor_rst (out_sensor_rst), // .out_sensor_rst
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.out_sensor_clk (out_sensor_clk), // .out_sensor_clk
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.out_sensor_gain (out_sensor_gain), // .out_sensor_gain
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.serial_rx (serial), //receive data
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.serial_tx (serial), //send data
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.ext_input (ext) //SMA etc.
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);
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endmodule |