85 lines
2.4 KiB
Verilog
85 lines
2.4 KiB
Verilog
//a module bridge the avalon streaming interfaces with data length from 32 bit to 16 bit
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//long to short
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//32 bits to 16 bits [31:16] streaming out first and then [15:0]
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//ST long to ST short
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//tested by stl2sts_tb.v
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module stl2sts(
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//clock and reset
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input wire clk,
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input wire rst,
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//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
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input wire [31:0] data_in_data, // st.data
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output wire data_in_ready, // .ready
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input wire data_in_valid, // .valid
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input wire [1:0] data_in_empty, // .empty
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input wire data_in_endofpacket, // .endofpacket
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input wire data_in_startofpacket, // .startofpacket
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//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
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output wire [15:0] data_out_data, // st.data
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input wire data_out_ready, // .ready
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output wire data_out_valid, // .valid
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output wire data_out_empty, // .empty
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output wire data_out_endofpacket, // .endofpacket
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output wire data_out_startofpacket // .startofpacket
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);
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reg[1:0] state;
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localparam STATE_IDLE = 2'd0; //waiting for startofpacket
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localparam STATE1 = 2'd1; //streaming [31:16]
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localparam STATE2 = 2'd3; //streaming [15:0]
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localparam STATE_LOCK = 2'd2; //Finishing streaming
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assign data_in_ready = (state == STATE2 && data_out_ready)? 1'b1:1'b0;
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assign data_out_data = (state == STATE1)? data_in_data[31:16]:(state== STATE2)? data_in_data[15:0]: 16'b0;
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assign data_out_valid = (state == STATE1 || state == STATE2)?data_in_valid:1'b0;
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assign data_out_empty = 1'b0;
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assign data_out_startofpacket = (state == STATE1)? data_in_startofpacket: 1'b0;
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assign data_out_endofpacket = (state == STATE2)? data_in_endofpacket: 1'b0;
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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state <= STATE_IDLE;
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else case(state)
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STATE_IDLE:
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begin
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if (data_in_startofpacket)
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state <= STATE1;
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end
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STATE1:
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begin
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if (data_in_valid && data_out_ready)
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state <= STATE2;
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end
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STATE2:
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begin
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if (data_in_valid && data_out_ready)
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begin
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if (data_in_endofpacket)
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state <= STATE_LOCK;
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else
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state <= STATE1;
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end
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end
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STATE_LOCK:
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state <= STATE_IDLE;
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default:
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state <= STATE_IDLE;
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endcase
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end
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endmodule
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