HITDAQ/FPGA_firmware/sensor_algo_qsys/ram_sim.qip
2024-10-11 14:49:54 +02:00

7 lines
432 B
Plaintext

set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "19.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_sim.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_sim_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_sim_bb.v"]