91 lines
2.6 KiB
Tcl
91 lines
2.6 KiB
Tcl
#
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# This file is intended to be sourced from a top.sdc
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# It contains references to TCL variables that are defined in the top.sdc
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#
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post_message -type info "Reading file: \'rgmii_clocks.sdc\'"
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# Set the periods of the clocks used in the design
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set PERIOD_125 8.0
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set PERIOD_25 [expr 8.0 * 5]
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set PERIOD_2p5 [expr 8.0 * 50]
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# Create the erx_clk on the port
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create_clock \
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-name enet_rx_clk \
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-period $PERIOD_125 \
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[get_ports {enet_rx_clk}]
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# Create the external virtual PHY clock
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create_clock \
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-name virtual_phy_clk \
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-period $PERIOD_125 \
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# Define the clocks that can appear on the output of the TX clock mux
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# Create the 125MHz mux output
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create_generated_clock \
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-name tx_clk_125 \
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-source [get_pins "$enet_pll_125"] \
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[get_pins {tx_clk_to_the_tse_mac|combout}]
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# Create the 25MHz mux output
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create_generated_clock \
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-name tx_clk_25 \
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-source [get_pins "$enet_pll_25"] \
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-add \
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[get_pins {tx_clk_to_the_tse_mac|combout}]
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# Create the 2.5MHz mux output
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create_generated_clock \
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-name tx_clk_2p5 \
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-source [get_pins "$enet_pll_2p5"] \
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-add \
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[get_pins {tx_clk_to_the_tse_mac|combout}]
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# All of the mux outputs are exclusive
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set_clock_groups \
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-exclusive \
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-group [get_clocks {tx_clk_125}] \
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-group [get_clocks {tx_clk_25}] \
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-group [get_clocks {tx_clk_2p5}]
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# Create the 125Mhz etx_clk output
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create_generated_clock \
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-name enet_gtx_clk_125 \
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-source [get_pins {tx_clk_to_the_tse_mac|combout}] \
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-master_clock {tx_clk_125} \
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[get_ports {enet_gtx_clk}]
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# Create the 25Mhz etx_clk output
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create_generated_clock \
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-name enet_gtx_clk_25 \
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-source [get_pins {tx_clk_to_the_tse_mac|combout}] \
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-master_clock {tx_clk_25} \
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-add \
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[get_ports {enet_gtx_clk}]
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# Create the 2p5Mhz etx_clk output
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create_generated_clock \
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-name enet_gtx_clk_2p5 \
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-source [get_pins {tx_clk_to_the_tse_mac|combout}] \
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-master_clock {tx_clk_2p5} \
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-add \
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[get_ports {enet_gtx_clk}]
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# Cut all the unrelated clock transfers to the external clocks
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set_clock_groups -exclusive \
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-group [get_clocks {tx_clk_125}] \
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-group [get_clocks {enet_gtx_clk_25 enet_gtx_clk_2p5}]
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set_clock_groups -exclusive \
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-group [get_clocks {tx_clk_25}] \
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-group [get_clocks {enet_gtx_clk_125 enet_gtx_clk_2p5}]
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set_clock_groups -exclusive \
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-group [get_clocks {tx_clk_2p5}] \
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-group [get_clocks {enet_gtx_clk_125 enet_gtx_clk_25}]
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# This path does not need to be constrained
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set_false_path -to [get_ports {enet_gtx_clk}]
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