24 lines
2.3 KiB
Verilog
24 lines
2.3 KiB
Verilog
st_splitter16 u0 (
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.st_splitter16_clk_clk (<connected-to-st_splitter16_clk_clk>), // st_splitter16_clk.clk
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.st_splitter16_reset_reset (<connected-to-st_splitter16_reset_reset>), // st_splitter16_reset.reset
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.st_splitter16_in_ready (<connected-to-st_splitter16_in_ready>), // st_splitter16_in.ready
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.st_splitter16_in_valid (<connected-to-st_splitter16_in_valid>), // .valid
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.st_splitter16_in_startofpacket (<connected-to-st_splitter16_in_startofpacket>), // .startofpacket
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.st_splitter16_in_endofpacket (<connected-to-st_splitter16_in_endofpacket>), // .endofpacket
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.st_splitter16_in_empty (<connected-to-st_splitter16_in_empty>), // .empty
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.st_splitter16_in_data (<connected-to-st_splitter16_in_data>), // .data
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.st_splitter16_out0_ready (<connected-to-st_splitter16_out0_ready>), // st_splitter16_out0.ready
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.st_splitter16_out0_valid (<connected-to-st_splitter16_out0_valid>), // .valid
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.st_splitter16_out0_startofpacket (<connected-to-st_splitter16_out0_startofpacket>), // .startofpacket
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.st_splitter16_out0_endofpacket (<connected-to-st_splitter16_out0_endofpacket>), // .endofpacket
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.st_splitter16_out0_empty (<connected-to-st_splitter16_out0_empty>), // .empty
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.st_splitter16_out0_data (<connected-to-st_splitter16_out0_data>), // .data
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.st_splitter16_out1_ready (<connected-to-st_splitter16_out1_ready>), // st_splitter16_out1.ready
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.st_splitter16_out1_valid (<connected-to-st_splitter16_out1_valid>), // .valid
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.st_splitter16_out1_startofpacket (<connected-to-st_splitter16_out1_startofpacket>), // .startofpacket
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.st_splitter16_out1_endofpacket (<connected-to-st_splitter16_out1_endofpacket>), // .endofpacket
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.st_splitter16_out1_empty (<connected-to-st_splitter16_out1_empty>), // .empty
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.st_splitter16_out1_data (<connected-to-st_splitter16_out1_data>) // .data
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);
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