45 lines
1.3 KiB
Verilog
45 lines
1.3 KiB
Verilog
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module st_splitter16 (
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st_splitter16_clk_clk,
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st_splitter16_reset_reset,
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st_splitter16_in_ready,
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st_splitter16_in_valid,
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st_splitter16_in_startofpacket,
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st_splitter16_in_endofpacket,
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st_splitter16_in_empty,
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st_splitter16_in_data,
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st_splitter16_out0_ready,
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st_splitter16_out0_valid,
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st_splitter16_out0_startofpacket,
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st_splitter16_out0_endofpacket,
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st_splitter16_out0_empty,
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st_splitter16_out0_data,
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st_splitter16_out1_ready,
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st_splitter16_out1_valid,
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st_splitter16_out1_startofpacket,
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st_splitter16_out1_endofpacket,
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st_splitter16_out1_empty,
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st_splitter16_out1_data);
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input st_splitter16_clk_clk;
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input st_splitter16_reset_reset;
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output st_splitter16_in_ready;
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input st_splitter16_in_valid;
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input st_splitter16_in_startofpacket;
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input st_splitter16_in_endofpacket;
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input [0:0] st_splitter16_in_empty;
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input [15:0] st_splitter16_in_data;
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input st_splitter16_out0_ready;
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output st_splitter16_out0_valid;
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output st_splitter16_out0_startofpacket;
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output st_splitter16_out0_endofpacket;
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output [0:0] st_splitter16_out0_empty;
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output [15:0] st_splitter16_out0_data;
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input st_splitter16_out1_ready;
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output st_splitter16_out1_valid;
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output st_splitter16_out1_startofpacket;
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output st_splitter16_out1_endofpacket;
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output [0:0] st_splitter16_out1_empty;
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output [15:0] st_splitter16_out1_data;
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endmodule
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