68 lines
9.8 KiB
Verilog
68 lines
9.8 KiB
Verilog
q_sys u0 (
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.altpll_shift_c0_clk (<connected-to-altpll_shift_c0_clk>), // altpll_shift_c0.clk
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.altpll_shift_locked_conduit_export (<connected-to-altpll_shift_locked_conduit_export>), // altpll_shift_locked_conduit.export
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.button_pio_external_connection_export (<connected-to-button_pio_external_connection_export>), // button_pio_external_connection.export
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.clock_bridge_0_in_clk_clk (<connected-to-clock_bridge_0_in_clk_clk>), // clock_bridge_0_in_clk.clk
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.ddr3_ram_pll_ref_clk_clk (<connected-to-ddr3_ram_pll_ref_clk_clk>), // ddr3_ram_pll_ref_clk.clk
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.debug_uart_external_connection_rxd (<connected-to-debug_uart_external_connection_rxd>), // debug_uart_external_connection.rxd
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.debug_uart_external_connection_txd (<connected-to-debug_uart_external_connection_txd>), // .txd
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.enet_pll_c0_clk (<connected-to-enet_pll_c0_clk>), // enet_pll_c0.clk
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.enet_pll_c1_clk (<connected-to-enet_pll_c1_clk>), // enet_pll_c1.clk
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.enet_pll_c2_clk (<connected-to-enet_pll_c2_clk>), // enet_pll_c2.clk
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.enet_pll_c3_clk (<connected-to-enet_pll_c3_clk>), // enet_pll_c3.clk
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.enet_pll_c4_clk (<connected-to-enet_pll_c4_clk>), // enet_pll_c4.clk
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.enet_pll_locked_conduit_export (<connected-to-enet_pll_locked_conduit_export>), // enet_pll_locked_conduit.export
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.eth_tse_mac_mdio_connection_mdc (<connected-to-eth_tse_mac_mdio_connection_mdc>), // eth_tse_mac_mdio_connection.mdc
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.eth_tse_mac_mdio_connection_mdio_in (<connected-to-eth_tse_mac_mdio_connection_mdio_in>), // .mdio_in
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.eth_tse_mac_mdio_connection_mdio_out (<connected-to-eth_tse_mac_mdio_connection_mdio_out>), // .mdio_out
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.eth_tse_mac_mdio_connection_mdio_oen (<connected-to-eth_tse_mac_mdio_connection_mdio_oen>), // .mdio_oen
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.eth_tse_mac_rgmii_connection_rgmii_in (<connected-to-eth_tse_mac_rgmii_connection_rgmii_in>), // eth_tse_mac_rgmii_connection.rgmii_in
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.eth_tse_mac_rgmii_connection_rgmii_out (<connected-to-eth_tse_mac_rgmii_connection_rgmii_out>), // .rgmii_out
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.eth_tse_mac_rgmii_connection_rx_control (<connected-to-eth_tse_mac_rgmii_connection_rx_control>), // .rx_control
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.eth_tse_mac_rgmii_connection_tx_control (<connected-to-eth_tse_mac_rgmii_connection_tx_control>), // .tx_control
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.eth_tse_mac_status_connection_set_10 (<connected-to-eth_tse_mac_status_connection_set_10>), // eth_tse_mac_status_connection.set_10
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.eth_tse_mac_status_connection_set_1000 (<connected-to-eth_tse_mac_status_connection_set_1000>), // .set_1000
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.eth_tse_mac_status_connection_eth_mode (<connected-to-eth_tse_mac_status_connection_eth_mode>), // .eth_mode
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.eth_tse_mac_status_connection_ena_10 (<connected-to-eth_tse_mac_status_connection_ena_10>), // .ena_10
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.eth_tse_pcs_mac_rx_clock_connection_clk (<connected-to-eth_tse_pcs_mac_rx_clock_connection_clk>), // eth_tse_pcs_mac_rx_clock_connection.clk
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.eth_tse_pcs_mac_tx_clock_connection_clk (<connected-to-eth_tse_pcs_mac_tx_clock_connection_clk>), // eth_tse_pcs_mac_tx_clock_connection.clk
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.ext_flash_flash_dataout_conduit_dataout (<connected-to-ext_flash_flash_dataout_conduit_dataout>), // ext_flash_flash_dataout.conduit_dataout
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.ext_flash_flash_dclk_out_conduit_dclk_out (<connected-to-ext_flash_flash_dclk_out_conduit_dclk_out>), // ext_flash_flash_dclk_out.conduit_dclk_out
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.ext_flash_flash_ncs_conduit_ncs (<connected-to-ext_flash_flash_ncs_conduit_ncs>), // ext_flash_flash_ncs.conduit_ncs
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.frame_timer_export (<connected-to-frame_timer_export>), // frame_timer.export
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.led_pio_external_connection_export (<connected-to-led_pio_external_connection_export>), // led_pio_external_connection.export
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.mem_if_ddr3_emif_0_status_local_init_done (<connected-to-mem_if_ddr3_emif_0_status_local_init_done>), // mem_if_ddr3_emif_0_status.local_init_done
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.mem_if_ddr3_emif_0_status_local_cal_success (<connected-to-mem_if_ddr3_emif_0_status_local_cal_success>), // .local_cal_success
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.mem_if_ddr3_emif_0_status_local_cal_fail (<connected-to-mem_if_ddr3_emif_0_status_local_cal_fail>), // .local_cal_fail
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.mem_resetn_in_reset_reset_n (<connected-to-mem_resetn_in_reset_reset_n>), // mem_resetn_in_reset.reset_n
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.memory_mem_a (<connected-to-memory_mem_a>), // memory.mem_a
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.memory_mem_ba (<connected-to-memory_mem_ba>), // .mem_ba
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.memory_mem_ck (<connected-to-memory_mem_ck>), // .mem_ck
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.memory_mem_ck_n (<connected-to-memory_mem_ck_n>), // .mem_ck_n
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.memory_mem_cke (<connected-to-memory_mem_cke>), // .mem_cke
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.memory_mem_cs_n (<connected-to-memory_mem_cs_n>), // .mem_cs_n
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.memory_mem_dm (<connected-to-memory_mem_dm>), // .mem_dm
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.memory_mem_ras_n (<connected-to-memory_mem_ras_n>), // .mem_ras_n
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.memory_mem_cas_n (<connected-to-memory_mem_cas_n>), // .mem_cas_n
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.memory_mem_we_n (<connected-to-memory_mem_we_n>), // .mem_we_n
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.memory_mem_reset_n (<connected-to-memory_mem_reset_n>), // .mem_reset_n
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.memory_mem_dq (<connected-to-memory_mem_dq>), // .mem_dq
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.memory_mem_dqs (<connected-to-memory_mem_dqs>), // .mem_dqs
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.memory_mem_dqs_n (<connected-to-memory_mem_dqs_n>), // .mem_dqs_n
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.memory_mem_odt (<connected-to-memory_mem_odt>), // .mem_odt
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.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
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.sensor_in_adc_data (<connected-to-sensor_in_adc_data>), // sensor.in_adc_data
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.sensor_in_trg (<connected-to-sensor_in_trg>), // .in_trg
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.sensor_out_adc_clk (<connected-to-sensor_out_adc_clk>), // .out_adc_clk
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.sensor_out_adc_cnv (<connected-to-sensor_out_adc_cnv>), // .out_adc_cnv
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.sensor_out_sensor_clk (<connected-to-sensor_out_sensor_clk>), // .out_sensor_clk
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.sensor_out_sensor_gain (<connected-to-sensor_out_sensor_gain>), // .out_sensor_gain
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.sensor_out_sensor_rst (<connected-to-sensor_out_sensor_rst>), // .out_sensor_rst
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.sensor_status_status_out (<connected-to-sensor_status_status_out>), // sensor_status.status_out
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.sensor_synchro_ext_input (<connected-to-sensor_synchro_ext_input>), // sensor_synchro.ext_input
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.sensor_synchro_serial_rx (<connected-to-sensor_synchro_serial_rx>), // .serial_rx
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.sensor_synchro_serial_tx (<connected-to-sensor_synchro_serial_tx>), // .serial_tx
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.sys_clk_clk (<connected-to-sys_clk_clk>) // sys_clk.clk
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);
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