133 lines
4.1 KiB
Verilog
133 lines
4.1 KiB
Verilog
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module q_sys (
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altpll_shift_c0_clk,
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altpll_shift_locked_conduit_export,
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button_pio_external_connection_export,
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clock_bridge_0_in_clk_clk,
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ddr3_ram_pll_ref_clk_clk,
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debug_uart_external_connection_rxd,
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debug_uart_external_connection_txd,
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enet_pll_c0_clk,
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enet_pll_c1_clk,
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enet_pll_c2_clk,
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enet_pll_c3_clk,
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enet_pll_c4_clk,
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enet_pll_locked_conduit_export,
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eth_tse_mac_mdio_connection_mdc,
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eth_tse_mac_mdio_connection_mdio_in,
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eth_tse_mac_mdio_connection_mdio_out,
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eth_tse_mac_mdio_connection_mdio_oen,
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eth_tse_mac_rgmii_connection_rgmii_in,
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eth_tse_mac_rgmii_connection_rgmii_out,
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eth_tse_mac_rgmii_connection_rx_control,
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eth_tse_mac_rgmii_connection_tx_control,
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eth_tse_mac_status_connection_set_10,
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eth_tse_mac_status_connection_set_1000,
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eth_tse_mac_status_connection_eth_mode,
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eth_tse_mac_status_connection_ena_10,
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eth_tse_pcs_mac_rx_clock_connection_clk,
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eth_tse_pcs_mac_tx_clock_connection_clk,
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ext_flash_flash_dataout_conduit_dataout,
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ext_flash_flash_dclk_out_conduit_dclk_out,
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ext_flash_flash_ncs_conduit_ncs,
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frame_timer_export,
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led_pio_external_connection_export,
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mem_if_ddr3_emif_0_status_local_init_done,
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mem_if_ddr3_emif_0_status_local_cal_success,
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mem_if_ddr3_emif_0_status_local_cal_fail,
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mem_resetn_in_reset_reset_n,
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memory_mem_a,
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memory_mem_ba,
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memory_mem_ck,
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memory_mem_ck_n,
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memory_mem_cke,
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memory_mem_cs_n,
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memory_mem_dm,
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memory_mem_ras_n,
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memory_mem_cas_n,
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memory_mem_we_n,
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memory_mem_reset_n,
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memory_mem_dq,
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memory_mem_dqs,
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memory_mem_dqs_n,
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memory_mem_odt,
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reset_reset_n,
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sensor_in_adc_data,
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sensor_in_trg,
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sensor_out_adc_clk,
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sensor_out_adc_cnv,
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sensor_out_sensor_clk,
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sensor_out_sensor_gain,
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sensor_out_sensor_rst,
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sensor_status_status_out,
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sensor_synchro_ext_input,
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sensor_synchro_serial_rx,
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sensor_synchro_serial_tx,
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sys_clk_clk);
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output altpll_shift_c0_clk;
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output altpll_shift_locked_conduit_export;
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input [8:0] button_pio_external_connection_export;
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input clock_bridge_0_in_clk_clk;
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input ddr3_ram_pll_ref_clk_clk;
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input debug_uart_external_connection_rxd;
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output debug_uart_external_connection_txd;
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output enet_pll_c0_clk;
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output enet_pll_c1_clk;
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output enet_pll_c2_clk;
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output enet_pll_c3_clk;
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output enet_pll_c4_clk;
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output enet_pll_locked_conduit_export;
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output eth_tse_mac_mdio_connection_mdc;
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input eth_tse_mac_mdio_connection_mdio_in;
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output eth_tse_mac_mdio_connection_mdio_out;
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output eth_tse_mac_mdio_connection_mdio_oen;
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input [3:0] eth_tse_mac_rgmii_connection_rgmii_in;
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output [3:0] eth_tse_mac_rgmii_connection_rgmii_out;
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input eth_tse_mac_rgmii_connection_rx_control;
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output eth_tse_mac_rgmii_connection_tx_control;
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input eth_tse_mac_status_connection_set_10;
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input eth_tse_mac_status_connection_set_1000;
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output eth_tse_mac_status_connection_eth_mode;
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output eth_tse_mac_status_connection_ena_10;
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input eth_tse_pcs_mac_rx_clock_connection_clk;
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input eth_tse_pcs_mac_tx_clock_connection_clk;
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inout [3:0] ext_flash_flash_dataout_conduit_dataout;
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output ext_flash_flash_dclk_out_conduit_dclk_out;
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output [0:0] ext_flash_flash_ncs_conduit_ncs;
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output frame_timer_export;
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output [7:0] led_pio_external_connection_export;
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output mem_if_ddr3_emif_0_status_local_init_done;
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output mem_if_ddr3_emif_0_status_local_cal_success;
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output mem_if_ddr3_emif_0_status_local_cal_fail;
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input mem_resetn_in_reset_reset_n;
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output [13:0] memory_mem_a;
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output [2:0] memory_mem_ba;
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inout [0:0] memory_mem_ck;
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inout [0:0] memory_mem_ck_n;
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output [0:0] memory_mem_cke;
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output [0:0] memory_mem_cs_n;
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output [0:0] memory_mem_dm;
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output [0:0] memory_mem_ras_n;
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output [0:0] memory_mem_cas_n;
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output [0:0] memory_mem_we_n;
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output memory_mem_reset_n;
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inout [7:0] memory_mem_dq;
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inout [0:0] memory_mem_dqs;
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inout [0:0] memory_mem_dqs_n;
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output [0:0] memory_mem_odt;
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input reset_reset_n;
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input [4:0] sensor_in_adc_data;
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input sensor_in_trg;
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output sensor_out_adc_clk;
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output sensor_out_adc_cnv;
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output sensor_out_sensor_clk;
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output sensor_out_sensor_gain;
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output sensor_out_sensor_rst;
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output [7:0] sensor_status_status_out;
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input [7:0] sensor_synchro_ext_input;
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input sensor_synchro_serial_rx;
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output sensor_synchro_serial_tx;
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input sys_clk_clk;
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endmodule
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