22 lines
1.7 KiB
Verilog
22 lines
1.7 KiB
Verilog
cali_ram u0 (
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.cali_ram_s2_address (<connected-to-cali_ram_s2_address>), // cali_ram_s2.address
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.cali_ram_s2_chipselect (<connected-to-cali_ram_s2_chipselect>), // .chipselect
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.cali_ram_s2_clken (<connected-to-cali_ram_s2_clken>), // .clken
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.cali_ram_s2_write (<connected-to-cali_ram_s2_write>), // .write
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.cali_ram_s2_readdata (<connected-to-cali_ram_s2_readdata>), // .readdata
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.cali_ram_s2_writedata (<connected-to-cali_ram_s2_writedata>), // .writedata
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.cali_ram_s2_byteenable (<connected-to-cali_ram_s2_byteenable>), // .byteenable
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.cali_ram_clk2_clk (<connected-to-cali_ram_clk2_clk>), // cali_ram_clk2.clk
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.cali_ram_reset2_reset (<connected-to-cali_ram_reset2_reset>), // cali_ram_reset2.reset
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.cali_ram_reset1_reset (<connected-to-cali_ram_reset1_reset>), // cali_ram_reset1.reset
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.cali_ram_s1_address (<connected-to-cali_ram_s1_address>), // cali_ram_s1.address
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.cali_ram_s1_clken (<connected-to-cali_ram_s1_clken>), // .clken
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.cali_ram_s1_chipselect (<connected-to-cali_ram_s1_chipselect>), // .chipselect
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.cali_ram_s1_write (<connected-to-cali_ram_s1_write>), // .write
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.cali_ram_s1_readdata (<connected-to-cali_ram_s1_readdata>), // .readdata
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.cali_ram_s1_writedata (<connected-to-cali_ram_s1_writedata>), // .writedata
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.cali_ram_s1_byteenable (<connected-to-cali_ram_s1_byteenable>), // .byteenable
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.cali_ram_clk1_clk (<connected-to-cali_ram_clk1_clk>) // cali_ram_clk1.clk
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);
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