HITDAQ/FPGA_firmware/output_files/.qsys_edit/preferences.xml
2024-10-11 14:49:54 +02:00

16 lines
456 B
XML

<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<debug showDebugMenu="0" />
<systemtable filter="All Interfaces">
<columns>
<connections preferredWidth="47" />
<irq preferredWidth="34" />
<inputclock preferredWidth="170" />
<name preferredWidth="186" />
</columns>
</systemtable>
<library expandedCategories="Library,Project" />
<window width="1920" height="1017" x="0" y="23" />
<hdlexample language="VERILOG" />
</preferences>