17 lines
349 B
Verilog
17 lines
349 B
Verilog
// clkctrl.v
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// Generated using ACDS version 19.1 670
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`timescale 1 ps / 1 ps
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module clkctrl (
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input wire inclk, // altclkctrl_input.inclk
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output wire outclk // altclkctrl_output.outclk
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);
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clkctrl_altclkctrl_0 altclkctrl_0 (
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.inclk (inclk), // altclkctrl_input.inclk
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.outclk (outclk) // altclkctrl_output.outclk
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);
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endmodule
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