180 lines
5.0 KiB
Verilog
180 lines
5.0 KiB
Verilog
//This is a testbench from the UDP generator
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`timescale 1 ns / 1 ns
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module udp_testbench();
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//Signals
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reg clk_clk; // clk.clk
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reg rst_reset; // rst.reset
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reg [2:0] csr_address; // csr.address
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reg csr_write; // .write
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reg [31:0] csr_writedata; // .writedata
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reg [3:0] csr_byteenable; // .byteenable
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reg csr_read; // .read
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wire [31:0] csr_readdata; // .readdata
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reg [31:0] data_in_data; // data_in.data
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wire data_in_ready; // .ready
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reg data_in_valid; // .valid
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reg [1:0] data_in_empty; // .empty
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reg data_in_endofpacket; // .endofpacket
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reg data_in_startofpacket; // .startofpacket
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wire [31:0] data_out_data; // data_out.data
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wire [1:0] data_out_empty; // .empty
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wire data_out_endofpacket; // .endofpacket
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wire data_out_startofpacket; // .startofpacket
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reg data_out_ready; // .ready
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wire data_out_valid; // .valid
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initial
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begin
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clk_clk = 0;
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rst_reset = 1;
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csr_address = 3'd0;
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csr_write = 0;
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csr_writedata = 32'd0;
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csr_byteenable = 4'b1111;
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csr_read = 0;
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data_in_data = 32'd0;
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data_in_valid = 0;
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data_in_empty = 2'd0;
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data_in_endofpacket = 0;
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data_in_startofpacket = 0;
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data_out_ready = 0;
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#50
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rst_reset = 0;
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//write 0x00F00001 to register 0 - size=240 + enable
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#20
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csr_write = 1;
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csr_byteenable = 4'b1111;
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csr_address = 3'd0;
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csr_writedata = 32'h00100001;
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#20
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csr_write = 0;
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csr_byteenable = 4'b0000;
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csr_address = 3'd0;
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csr_writedata = 32'h00000000;
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//write 0x0A000711 to register 1 - SRC IP = 10.0.7.17
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#20
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csr_write = 1;
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csr_byteenable = 4'b1111;
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csr_address = 3'd1;
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csr_writedata = 32'h0A000711;
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#20
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csr_write = 0;
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csr_byteenable = 4'b0000;
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csr_address = 3'd0;
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csr_writedata = 32'h00000000;
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//write 0x0A000701 to register 2 - DST IP = 10.0.7.1
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#20
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csr_write = 1;
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csr_byteenable = 4'b1111;
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csr_address = 3'd2;
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csr_writedata = 32'h0A000701;
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#20
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csr_write = 0;
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csr_byteenable = 4'b0000;
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csr_address = 3'd0;
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csr_writedata = 32'h00000000;
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//write 0x01000100 to register 3 - SRC port = 4096, DST port = 4096
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#20
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csr_write = 1;
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csr_byteenable = 4'b1111;
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csr_address = 3'd3;
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csr_writedata = 32'h01000100;
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#20
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csr_write = 0;
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csr_byteenable = 4'b0000;
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csr_address = 3'd0;
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csr_writedata = 32'h00000000;
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//write 0xc705aa63 to register 4 - DST MAC lower bytes = 70 05 aa 63
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#20
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csr_write = 1;
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csr_byteenable = 4'b1111;
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csr_address = 3'd4;
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csr_writedata = 32'hc705aa63;
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#20
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csr_write = 0;
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csr_byteenable = 4'b0000;
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csr_address = 3'd0;
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csr_writedata = 32'h00000000;
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//write 0x000018d6 to register 5 - DST MAC higher bytes = 18 d6
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#20
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csr_write = 1;
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csr_byteenable = 4'b1111;
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csr_address = 3'd5;
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csr_writedata = 32'h000018d6;
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#20
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csr_write = 0;
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csr_byteenable = 4'b0000;
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csr_address = 3'd0;
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csr_writedata = 32'h00000000;
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//Start transmission
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#102
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data_in_valid = 1;
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data_in_startofpacket = 1;
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data_in_data = 32'h12345678;
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//backpressure - ready signal from receiver
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#40
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data_out_ready = 1;
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#20
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data_in_startofpacket = 0;
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//finish sending data
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#480
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data_in_endofpacket = 1;
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#20
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data_in_endofpacket = 0;
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data_in_valid = 0;
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#1500
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$stop;
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end
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always #10 clk_clk = ~clk_clk;
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// UDP generator
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udp_generator the_udp_generator (
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.clk_clk (clk_clk), // clk.clk
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.rst_reset (rst_reset), // rst.reset
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.csr_address (csr_address), // csr.address
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.csr_write (csr_write), // .write
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.csr_writedata (csr_writedata), // .writedata
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.csr_byteenable (csr_byteenable), // .byteenable
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.csr_read (csr_read), // .read
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.csr_readdata (csr_readdata), // .readdata
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.data_in_data (data_in_data), // data_in.data
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.data_in_ready (data_in_ready), // .ready
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.data_in_valid (data_in_valid), // .valid
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.data_in_empty (data_in_empty), // .empty
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.data_in_endofpacket (data_in_endofpacket), // .endofpacket
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.data_in_startofpacket(data_in_startofpacket), // .startofpacket
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.data_out_data (data_out_data), // data_out.data
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.data_out_empty (data_out_empty), // .empty
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.data_out_endofpacket (data_out_endofpacket), // .endofpacket
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.data_out_startofpacket(data_out_startofpacket),// .startofpacket
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.data_out_ready (data_out_ready), // .ready
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.data_out_valid (data_out_valid) // .valid
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);
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endmodule |