109 lines
2.9 KiB
Verilog
109 lines
2.9 KiB
Verilog
//a module bridge the avalon streaming interfaces with data length from 16 bit to 32bit
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//short to long
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//First fill [31:16] and then fill [15:0]
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//ST short to ST long
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//the number of ST short data_in_data has to be even
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//tested by sts2stl_tb.v
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module sts2stl(
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//clock and reset
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input wire clk,
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input wire rst,
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//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
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input wire [15:0] data_in_data, // st.data
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output wire data_in_ready, // .ready
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input wire data_in_valid, // .valid
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input wire data_in_empty, // .empty
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input wire data_in_endofpacket, // .endofpacket
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input wire data_in_startofpacket, // .startofpacket
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//avalon ST(Streaming) source: 0 readlatency and 0 readallowence
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output wire [31:0] data_out_data, // st.data
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input wire data_out_ready, // .ready
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output wire data_out_valid, // .valid
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output wire [1:0] data_out_empty, // .empty
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output wire data_out_endofpacket, // .endofpacket
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output wire data_out_startofpacket // .startofpacket
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);
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reg[2:0] state;
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localparam STATE_IDLE = 3'd0; //waiting for startofpacket
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localparam STATE10 = 3'd1; // collecting [31:16]
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localparam STATE20 = 3'd3; // collecting [15:0]
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localparam STATE1 = 3'd7;
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localparam STATE2 = 3'd6;
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localparam STATE_LOCK = 3'd5; //Finishing streaming
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reg[15:0] data_buffer; //buffer for the first and then fill [31:16]
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assign data_in_ready = ((state == STATE20 || state == STATE2) && data_out_ready)? 1'b1:(state == STATE1 || state == STATE10)? 1'b1: 1'b0;
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assign data_out_data = (state == STATE2 || state == STATE20)? {data_buffer, data_in_data}: 32'b0;
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assign data_out_valid = (state == STATE2 || state == STATE20)? data_in_valid: 1'b0;
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assign data_out_empty = 2'b0;
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assign data_out_startofpacket = (state == STATE20)? 1'b1: 1'b0;
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assign data_out_endofpacket = (state == STATE2)? data_in_endofpacket: 1'b0;
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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state <= STATE_IDLE;
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else case(state)
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STATE_IDLE:
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begin
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if (data_in_startofpacket)
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state <= STATE10;
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end
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STATE10:
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begin
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if (data_in_valid)
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begin
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state <= STATE20;
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data_buffer <= data_in_data;
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end
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end
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STATE20:
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begin
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if (data_in_valid && data_out_ready)
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begin
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if (data_in_endofpacket)
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state <= STATE_LOCK;
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else
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state <= STATE1;
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end
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end
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STATE1:
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begin
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if (data_in_valid)
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begin
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state <= STATE2;
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data_buffer <= data_in_data;
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end
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end
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STATE2:
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begin
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if (data_in_valid && data_out_ready)
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begin
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if (data_in_endofpacket)
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state <= STATE_LOCK;
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else
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state <= STATE1;
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end
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end
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STATE_LOCK:
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state <= STATE_IDLE;
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default:
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state <= STATE_IDLE;
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endcase
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end
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endmodule
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