HITDAQ/FPGA_firmware/sensor_algo_qsys/st_splitter16.qsys
2024-10-11 14:49:54 +02:00

92 lines
3.0 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element st_splitter16
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10M50DAF484C6GES" />
<parameter name="deviceFamily" value="MAX 10" />
<parameter name="deviceSpeedGrade" value="6" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="st_splitter16_clk"
internal="st_splitter16.clk"
type="clock"
dir="end" />
<interface
name="st_splitter16_in"
internal="st_splitter16.in"
type="avalon_streaming"
dir="end" />
<interface
name="st_splitter16_out0"
internal="st_splitter16.out0"
type="avalon_streaming"
dir="start" />
<interface
name="st_splitter16_out1"
internal="st_splitter16.out1"
type="avalon_streaming"
dir="start" />
<interface
name="st_splitter16_reset"
internal="st_splitter16.reset"
type="reset"
dir="end" />
<module
name="st_splitter16"
kind="altera_avalon_st_splitter"
version="19.1"
enabled="1">
<parameter name="BITS_PER_SYMBOL" value="8" />
<parameter name="CHANNEL_WIDTH" value="1" />
<parameter name="DATA_WIDTH" value="16" />
<parameter name="ERROR_DESCRIPTOR" value="" />
<parameter name="ERROR_WIDTH" value="1" />
<parameter name="MAX_CHANNELS" value="1" />
<parameter name="NUMBER_OF_OUTPUTS" value="2" />
<parameter name="QUALIFY_VALID_OUT" value="1" />
<parameter name="READY_LATENCY" value="0" />
<parameter name="USE_CHANNEL" value="0" />
<parameter name="USE_DATA" value="1" />
<parameter name="USE_ERROR" value="0" />
<parameter name="USE_PACKETS" value="1" />
<parameter name="USE_READY" value="1" />
<parameter name="USE_VALID" value="1" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>