14 lines
299 B
Verilog
14 lines
299 B
Verilog
ram_sim ram_sim_inst (
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.address_a ( address_a_sig ),
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.address_b ( address_b_sig ),
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.clock ( clock_sig ),
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.data_a ( data_a_sig ),
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.data_b ( data_b_sig ),
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.rden_a ( rden_a_sig ),
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.rden_b ( rden_b_sig ),
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.wren_a ( wren_a_sig ),
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.wren_b ( wren_b_sig ),
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.q_a ( q_a_sig ),
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.q_b ( q_b_sig )
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);
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