9 lines
168 B
Verilog
9 lines
168 B
Verilog
ram4bkg ram4bkg_inst (
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.clock ( clock_sig ),
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.data ( data_sig ),
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.rdaddress ( rdaddress_sig ),
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.wraddress ( wraddress_sig ),
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.wren ( wren_sig ),
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.q ( q_sig )
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);
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