HITDAQ/FPGA_firmware/sensor_algo_qsys/data_caled_ram.qip
2024-10-11 14:49:54 +02:00

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set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "19.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "data_caled_ram.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "data_caled_ram_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "data_caled_ram_bb.v"]