218 lines
6.7 KiB
Verilog
218 lines
6.7 KiB
Verilog
//background subtraction module
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//tested with bkg_subtraction_tb.v
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module bkg_subtraction #(parameter BKG_FRAME = 4)(
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//clock and reset
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input wire clk,
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input wire rst, // connect to rst_run
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//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence // 163 word = 3 header + 160 data
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input wire [31:0] data_in_data, // st.data
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output wire data_in_ready, // .ready
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input wire data_in_valid, // .valid
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input wire [1:0] data_in_empty, // .empty
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input wire data_in_endofpacket, // .endofpacket
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input wire data_in_startofpacket, // .startofpacket
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//avalon ST(Streaming) source: 0 readlatency and 0 readallowence //160 word only with data
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output wire [31:0] data_out_data, // st.data
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input wire data_out_ready, // .ready
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output wire data_out_valid, // .valid
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output wire [1:0] data_out_empty, // .empty
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output wire data_out_endofpacket, // .endofpacket
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output wire data_out_startofpacket // .startofpacket
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//output rst_frame // I have to think about this rst_frame when is a good timing! or do I need it? 26.June. 2024
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);
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wire bkg_sub_on;
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wire rst_frame = data_in_startofpacket;
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/************************* Frame Counter***********************************/
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/*
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This is a frame counter;
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frameID +1 at the rising edge of data_in_startofpacket
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if frame increase at 10kHz, the 27-bit frameID can count 3.72 hour frame
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*/
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reg [26:0] frameID;
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reg data_in_startofpacket_last;
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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begin
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data_in_startofpacket_last <= 1'b0;
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frameID<= 27'b0;
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end
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else
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begin
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data_in_startofpacket_last <= data_in_startofpacket;
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if (~data_in_startofpacket_last && data_in_startofpacket)
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frameID<= frameID + 1'b1;
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end
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end
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// *********************** ST interface ***********************
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reg [4:0] state; //State of the state machine
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localparam STATE_IDLE = 5'd0; //waiting for SOP
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localparam STATE_WORD0 = 5'd1; //sending first word :
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localparam STATE_WORD1 = 5'd2; //sending second word:
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localparam STATE_WORD2 = 5'd3; //sending third word :
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localparam STATE_DATA_PRO = 5'd4; //blocking data get bkg_signal; and do the subtraction
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localparam STATE_DATA_NEXT = 5'd7; //sending data
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localparam STATE_LOC = 5'd5; //calculatebb
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//Helper stuff
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reg [7:0] tx_ctr; //counter of sent data words range: 0~255
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localparam WORDS_TO_SEND = 163;
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//the number of clocks for STATE_DATA_PRO
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reg [5:0] delay_ctr;
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localparam DELAY_CLOCKS = 6'd2;
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/************** bkg RAM ****************************/
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/*
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for prepare the bkg signal by two RAM;
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one for data_in_data[31:16]; the other for data_in_data[15:0]
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the signal after bkg subtraction is 16 bit signed; the LSM bit is dropped out; (it's not important with current noise level)
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*/
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wire[15:0] bkgH;
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wire[15:0] bkgL;
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wire[31:0] bkg_input_data;
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wire bkg_input_valid;
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assign bkg_input_valid = (state == STATE_DATA_NEXT && data_out_ready);
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//assign bkg_input_valid = 1'b1;
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//signal after subtract background
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//got the background signal at the third clock in STATE_DATA_PRO
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//and subtract it to 16 bit by giving up the LSM, i.e. divide 2.
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reg [16:0] signal0_17bit;
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reg [16:0] signal1_17bit;
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wire[15:0] signal0;
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wire[15:0] signal1;
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assign signal0 = bkg_sub_on?signal0_17bit[16:1]:signal0_17bit[15:0];
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assign signal1 = bkg_sub_on?signal1_17bit[16:1]:signal1_17bit[15:0];
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bkg_ram #(.TOTAL_FRAME(BKG_FRAME)) bkg_ram0(
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.clk_clk(clk),
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.rst_reset(rst),
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.frameID(frameID[26:0]),
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.address(tx_ctr),
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.data_in_data(bkg_input_data),
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.data_in_valid(bkg_input_valid),
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.bkg_signal({bkgH,bkgL}),
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.bkg_sub_status(bkg_sub_on)
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);
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assign bkg_input_data = (state==STATE_DATA_NEXT)?data_in_data:15'b0;
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wire data_out_ready_for3header = 1'b1;
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//The state machine
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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begin
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state <= STATE_IDLE;
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end
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else
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case(state)
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STATE_IDLE:
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begin
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if (data_in_startofpacket)
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begin
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state <= STATE_WORD0;
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tx_ctr <= 0;
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end
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end
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STATE_WORD0:
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begin
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if (data_in_valid && data_out_ready_for3header)
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begin
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state <= STATE_WORD1;
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tx_ctr <= tx_ctr+ 1'b1;
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end
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end
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STATE_WORD1:
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begin
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if (data_in_valid && data_out_ready_for3header)
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begin
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state <= STATE_WORD2;
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tx_ctr <= tx_ctr +1'b1;
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end
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end
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STATE_WORD2:
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begin
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if (data_in_valid && data_out_ready_for3header)
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begin
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state <= STATE_DATA_PRO;
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tx_ctr <= tx_ctr +1'b1;
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delay_ctr <= DELAY_CLOCKS -1'b1;
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end
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end
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STATE_DATA_PRO:
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begin
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if (data_in_valid)
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begin
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delay_ctr <= delay_ctr -1'b1;
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if (delay_ctr == 0)
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begin
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state <= STATE_DATA_NEXT;
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delay_ctr <= DELAY_CLOCKS - 1'b1;
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signal0_17bit <= {1'b0, data_in_data[31:16]}-{1'b0,bkgH};
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signal1_17bit <= {1'b0, data_in_data[15:0]}-{1'b0,bkgL};
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end
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end
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end
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STATE_DATA_NEXT:
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begin
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if (data_out_ready)
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begin
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tx_ctr <= tx_ctr+1'b1;
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if (tx_ctr == WORDS_TO_SEND -1) //last word, size matches
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state <= STATE_LOC;
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else
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state <= STATE_DATA_PRO;
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end
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end
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STATE_LOC:
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begin
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state <= STATE_IDLE;
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end
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default:
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begin
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state <= STATE_IDLE;
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end
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endcase
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end
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//output 163 words
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//assign data_in_ready = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT)&&data_out_ready;
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//assign data_out_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT) ? 1'b1 : 1'b0;
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//the output data is be reversed....so during transfer without signal it's FFFFF, the software HIT-DAQ will reverse it again
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//assign data_out_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:
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// (state == STATE_DATA_NEXT)? {signal0,signal1}: 0;
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//assign data_out_startofpacket = data_in_startofpacket;
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//assign data_out_endofpacket = (state == STATE_DATA_NEXT & tx_ctr == WORDS_TO_SEND-1) ? 1'b1 : 1'b0;
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//assign data_out_empty = 0;
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//output 160 words
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assign data_in_ready = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2) || (state == STATE_DATA_NEXT && data_out_ready);
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assign data_out_valid = (state == STATE_DATA_NEXT) ? 1'b1 : 1'b0;
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assign data_out_data = (state == STATE_DATA_NEXT)? {signal0,signal1}: 0;
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assign data_out_startofpacket = (state == STATE_DATA_NEXT && tx_ctr == 8'd3)? 1'b1: 1'b0;
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assign data_out_endofpacket = (state == STATE_DATA_NEXT & tx_ctr == WORDS_TO_SEND-1) ? 1'b1 : 1'b0;
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assign data_out_empty = 0;
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endmodule
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