91 lines
2.4 KiB
Verilog
91 lines
2.4 KiB
Verilog
// module algo_top
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//bkg + stl2sts tested by algo_top_tb.v
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module algo_top(
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//clock and reset
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input wire clk,
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input wire rst, // connect to rst_run
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//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence // 163 word = 3 header + 160 data
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input wire [31:0] data_in_data, // st.data
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output wire data_in_ready, // .ready
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input wire data_in_valid, // .valid
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input wire [1:0] data_in_empty, // .empty
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input wire data_in_endofpacket, // .endofpacket
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input wire data_in_startofpacket, // .startofpacket
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//avalon ST(Streaming) source: 0 readlatency and 0 readallowence // ?? word only with data
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output wire [15:0] data_out_data, // st.data
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input wire data_out_ready, // .ready
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output wire data_out_valid, // .valid
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output wire [1:0] data_out_empty, // .empty
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output wire data_out_endofpacket, // .endofpacket
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output wire data_out_startofpacket // .startofpacket
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);
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wire [31:0] wire_data0;
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wire wire_ready0;
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wire wire_valid0;
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wire [2:0] wire_empty0;
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wire wire_endofpacket0;
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wire wire_startofpacket0;
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bkg_subtraction #(.BKG_FRAME(4)) bkg_subtraction0(
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.clk (clk),
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.rst (rst),
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.data_in_data (data_in_data),
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.data_in_ready (data_in_ready),
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.data_in_valid (data_in_valid),
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.data_in_empty (data_in_empty),
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.data_in_startofpacket (data_in_startofpacket),
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.data_in_endofpacket (data_in_endofpacket),
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.data_out_data (wire_data0),
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.data_out_empty (wire_empty0),
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.data_out_endofpacket (wire_endofpacket0),
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.data_out_startofpacket (wire_startofpacket0),
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.data_out_ready (wire_ready0),
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.data_out_valid (wire_valid0)
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);
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stl2sts stl2sts0(
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.clk (clk),
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.rst (rst),
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.data_in_data (wire_data0),
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.data_in_ready (wire_ready0),
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.data_in_valid (wire_valid0),
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.data_in_empty (wire_empty0),
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.data_in_startofpacket (wire_startofpacket0),
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.data_in_endofpacket (wire_endofpacket0),
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.data_out_data (data_out_data),
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.data_out_empty (data_out_empty),
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.data_out_endofpacket (data_out_endofpacket),
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.data_out_startofpacket (data_out_startofpacket),
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.data_out_ready (data_out_ready),
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.data_out_valid (data_out_valid)
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);
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endmodule
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