82 lines
2.8 KiB
Systemverilog
82 lines
2.8 KiB
Systemverilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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//---------------------------------------------------------------------
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//
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// Module Name : asmiblock
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// Description : Standard/QUAD IO mode
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//
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//---------------------------------------------------------------------
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`timescale 1 ps/1 ps
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module soft_asmiblock #(
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parameter IO_MODE = "STANDARD",
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parameter CS_WIDTH = 1
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)(
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dclk,
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sce,
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dataout,
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dataoe,
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datain,
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dclk_out,
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ncs
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);
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input dclk;
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input [CS_WIDTH-1:0] sce;
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input [3:0] dataout;
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input [3:0] dataoe;
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inout [3:0] datain;
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output dclk_out;
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output [CS_WIDTH-1:0] ncs;
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wire oe;
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wire data[3:0];
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wire data_buf[3:0];
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assign oe = 1'b0;
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assign dclk_out = (oe === 1'b0) ? dclk : (oe === 1'b1) ? 1'bz : 1'bx;
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assign ncs = (oe === 1'b0) ? sce : (oe === 1'b1) ? 1'bz : 1'bx;
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assign data[0] = (oe === 1'b0) ? data_buf[0] : (oe === 1'b1) ? 1'bz : 1'bx;
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assign data_buf[0] = (dataoe[0] === 1'b1) ? dataout[0] : (dataoe[0] === 1'b0) ? 1'bz : 1'bx;
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assign datain[0] = data[0];
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assign data[1] = (oe === 1'b0) ? data_buf[1] : (oe === 1'b1) ? 1'bz : 1'bx;
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assign data_buf[1] = (dataoe[1] === 1'b1) ? dataout[1] : (dataoe[1] === 1'b0) ? 1'bz : 1'bx;
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assign datain[1] = data[1];
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generate
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if (IO_MODE == "STANDARD") begin
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assign data[2] = (oe === 1'b0) ? data_buf[2] : (oe === 1'b1) ? 1'bz : 1'bx;
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assign data_buf[2] = (dataoe[2] === 1'b1) ? 1'b1 : (dataoe[2] === 1'b0) ? 1'bz : 1'bx;
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assign datain[2] = data[2];
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assign data[3] = (oe === 1'b0) ? data_buf[3] : (oe === 1'b1) ? 1'bz : 1'bx;
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assign data_buf[3] = (dataoe[3] === 1'b1) ? 1'b1 : (dataoe[3] === 1'b0) ? 1'bz : 1'bx;
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assign datain[3] = data[3];
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end
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else begin
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assign data[2] = (oe === 1'b0) ? data_buf[2] : (oe === 1'b1) ? 1'bz : 1'bx;
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assign data_buf[2] = (dataoe[2] === 1'b1) ? dataout[2] : (dataoe[2] === 1'b0) ? 1'bz : 1'bx;
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assign datain[2] = data[2];
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assign data[3] = (oe === 1'b0) ? data_buf[3] : (oe === 1'b1) ? 1'bz : 1'bx;
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assign data_buf[3] = (dataoe[3] === 1'b1) ? dataout[3] : (dataoe[3] === 1'b0) ? 1'bz : 1'bx;
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assign datain[3] = data[3];
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end
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endgenerate
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endmodule // asmiblock
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