180 lines
8.5 KiB
Verilog
180 lines
8.5 KiB
Verilog
//module top
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//the output datapacket is 166 words; 0~2 is header; 3~162 is data's inverse signed; and last 4 words are not inversed
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module sensor_rms (
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//Clock/reset
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input wire clk_clk, // clk.clk
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input wire rst_reset, // rst.reset
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//Avalon MM slave
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input wire [1:0] csr_address, // avalon_slave.address
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input wire csr_read, // .read
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output wire [31:0] csr_readdata, // .readdata
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input wire csr_write, // .write
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input wire [31:0] csr_writedata, // .writedata
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input wire [3:0] csr_byteenable, // .byteenable
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//Avalon ST transmitter
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output wire [31:0] data_out_data, // avalon_streaming_source.data
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output wire data_out_endofpacket, // .endofpacket
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output wire data_out_startofpacket, // .startofpacket
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input wire data_out_ready, // .ready
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output wire data_out_valid, // .valid
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output wire [1:0] data_out_empty, // .empty
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//Sensor interface
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input wire in_trg, // sensor.in_trg
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output wire out_adc_clk, // .out_dac_clk
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output wire out_adc_cnv, // .out_dac_cnv
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input wire [4:0] in_adc_data, // .in_dac_data
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output wire out_sensor_rst, // .out_sensor_rst
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output wire out_sensor_clk, // .out_sensor_clk
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output wire out_sensor_gain, // .out_sensor_gain
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//Serial synchro interface
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input wire serial_rx, //receive data
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output wire serial_tx, //send data
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input wire [7:0] ext_input, //SMA etc.
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//Debug information
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output wire [7:0] status_out //status bits - same as in reg0_read[15:8]
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//output wire[26:0] frameID
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);
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wire [31:0] data_out_data1; // Output data
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wire data_out_endofpacket1; // Output end-of-packet signal
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wire data_out_startofpacket1; // Output start-of-packet signal
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wire data_out_ready1; // Output ready signal
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wire data_out_valid1; // Output valid signal
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wire [1:0] data_out_empty1; // Output empty signal
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wire [31:0] data_out_data_algo; // Output data
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wire data_out_endofpacket_algo; // Output end-of-packet signal
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wire data_out_startofpacket_algo; // Output start-of-packet signal
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wire data_out_ready_algo; // Output ready signal
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wire data_out_valid_algo; // Output valid signal
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wire [1:0] data_out_empty_algo; // Output empty signal
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wire int_rst;
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wire sig_ram_last;
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wire bkg_sub_on;
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wire rst_frame;
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//data for sig after bkg subtraction
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wire sig_rdclk; //the read port for sig_ram
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wire[8:0] sig_rdaddress; //0~319 for data. 500~502 for the 3 words head
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wire[31:0] sig_out;
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//the output of cluster_locate
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wire[8:0] sig_ch_left;
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wire[8:0] sig_ch_right;
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wire has_cluster;
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wire no_cluster;
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sensor_interface the_sensor_interface (
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.clk_clk (clk_clk), // clk.clk
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.rst_reset (rst_reset), // rst.reset
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.csr_address (csr_address), // csr.address
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.csr_write (csr_write), // .write
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.csr_writedata (csr_writedata), // .writedata
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.csr_byteenable (csr_byteenable), // .byteenable
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.csr_read (csr_read), // .read
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.csr_readdata (csr_readdata), // .readdata
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.data_out_data (data_out_data1), // data_out.data
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.data_out_empty (data_out_empty1), // .empty
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.data_out_endofpacket (data_out_endofpacket1), // .endofpacket
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.data_out_startofpacket (data_out_startofpacket1),// .startofpacket
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.data_out_ready (data_out_ready1), // .ready
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.data_out_valid (data_out_valid1), // .valid
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.in_trg (in_trg), // sensor.in_trg
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.out_adc_clk (out_adc_clk), // .out_dac_clk
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.out_adc_cnv (out_adc_cnv), // .out_dac_cnv
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.in_adc_data (in_adc_data), // .in_dac_data
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.out_sensor_rst (out_sensor_rst), // .out_sensor_rst
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.out_sensor_clk (out_sensor_clk), // .out_sensor_clk
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.out_sensor_gain (out_sensor_gain), // .out_sensor_gain
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.serial_rx (serial_rx), //receive data
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.serial_tx (serial_tx), //send data
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.ext_input (ext_input), //SMA etc.
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.int_rst (int_rst)
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);
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data_interface #(.BKG_FRAME(8192), .CLU_THRESHOLD(14), .CLU_SIZE(4)) data_interface_dut (
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.clk_clk(clk_clk), // Clock input
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.rst_reset(int_rst), // Reset input
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.data_in_data(data_out_data1), // Input data
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.data_in_ready(data_out_ready1), // Input ready signal
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.data_in_valid(data_out_valid1), // Input valid signal
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.data_in_empty(data_out_empty1), // Input empty signal
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.data_in_endofpacket(data_out_endofpacket1), // Input end-of-packet signal
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.data_in_startofpacket(data_out_startofpacket1), // Input start-of-packet signal
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.data_out_data(data_out_data_algo), // Output data
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.data_out_endofpacket(data_out_endofpacket_algo), // Output end-of-packet signal
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.data_out_startofpacket(data_out_startofpacket_algo), // Output start-of-packet signal
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.data_out_ready(data_out_ready_algo), // Output ready signal
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.data_out_valid(data_out_valid_algo), // Output valid signal
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.data_out_empty(data_out_empty_algo), // Output empty signal
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.bkg_sub_on(bkg_sub_on),
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.rst_frame(rst_frame),
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//data for sig after bkg subtraction
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.sig_rdclk(sig_rdclk), //the read port for sig_ram
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.sig_rdaddress(sig_rdaddress), //0~319 for data. 500~502 for the 3 words head
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.sig_out(sig_out),
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.sig_ram_last(sig_ram_last),
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.sig_ch_left(sig_ch_left),
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.sig_ch_right(sig_ch_right),
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.has_cluster(has_cluster),
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.no_cluster(no_cluster)
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);
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rms rms_but(
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.clk_clk(clk_clk), // clk.clk
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.rst_reset(rst_frame), // the reset should connect to the rst_frame
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//data for sig after bkg subtraction
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.bkg_sub_on(bkg_sub_on), //indicate that bkg_sub is on
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.sig_rdclk(sig_rdclk), //the read port for sig_ram
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.sig_rdaddress(sig_rdaddress), //0~319 for data. 500~502 for the 3 words head
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.sig(sig_out),
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.sig_ram_last(sig_ram_last),
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.data_in_data(data_out_data_algo), // Input data
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.data_in_ready(data_out_ready_algo), // Input ready signal
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.data_in_valid(data_out_valid_algo), // Input valid signal
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.data_in_empty(data_out_empty_algo), // Input empty signal
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.data_in_endofpacket(data_out_endofpacket_algo), // Input end-of-packet signal
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.data_in_startofpacket(data_out_startofpacket_algo), // Input start-of-packet signal
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//the output of cluster_locate
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.sig_ch_left(sig_ch_left),
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.sig_ch_right(sig_ch_right),
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.has_cluster(has_cluster),
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.no_cluster(no_cluster),
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.data_out_data(data_out_data), // Output data
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.data_out_endofpacket(data_out_endofpacket), // Output end-of-packet signal
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.data_out_startofpacket(data_out_startofpacket), // Output start-of-packet signal
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.data_out_ready(data_out_ready), // Output ready signal
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.data_out_valid(data_out_valid), // Output valid signal
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.data_out_empty(data_out_empty) // Output empty signal
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);
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endmodule |