45 lines
1.3 KiB
Verilog
45 lines
1.3 KiB
Verilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module rw_manager_lfsr72(
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clk,
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nrst,
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ena,
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word
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);
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input clk;
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input nrst;
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input ena;
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output reg [71:0] word;
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always @(posedge clk or negedge nrst) begin
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if(~nrst) begin
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word <= 72'hAAF0F0AA55F0F0AA55;
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end
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else if(ena) begin
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word[71] <= word[0];
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word[70:66] <= word[71:67];
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word[65] <= word[66] ^ word[0];
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word[64:25] <= word[65:26];
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word[24] <= word[25] ^ word[0];
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word[23:19] <= word[24:20];
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word[18] <= word[19] ^ word[0];
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word[17:0] <= word[18:1];
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end
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end
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endmodule
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