73 lines
2.0 KiB
Verilog
73 lines
2.0 KiB
Verilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module rw_manager_lfsr36(
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clk,
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nrst,
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ena,
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word
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);
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input clk;
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input nrst;
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input ena;
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output reg [35:0] word;
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always @(posedge clk or negedge nrst) begin
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if(~nrst) begin
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word <= 36'hF0F0AA55;
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end
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else if(ena) begin
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word[35] <= word[0];
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word[34] <= word[35];
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word[33] <= word[34];
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word[32] <= word[33];
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word[31] <= word[32];
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word[30] <= word[31];
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word[29] <= word[30];
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word[28] <= word[29];
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word[27] <= word[28];
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word[26] <= word[27];
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word[25] <= word[26];
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word[24] <= word[25] ^ word[0];
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word[23] <= word[24];
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word[22] <= word[23];
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word[21] <= word[22];
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word[20] <= word[21];
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word[19] <= word[20];
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word[18] <= word[19];
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word[17] <= word[18];
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word[16] <= word[17];
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word[15] <= word[16];
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word[14] <= word[15];
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word[13] <= word[14];
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word[12] <= word[13];
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word[11] <= word[12];
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word[10] <= word[11];
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word[9] <= word[10];
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word[8] <= word[9];
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word[7] <= word[8];
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word[6] <= word[7];
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word[5] <= word[6];
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word[4] <= word[5];
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word[3] <= word[4];
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word[2] <= word[3];
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word[1] <= word[2];
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word[0] <= word[1];
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end
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end
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endmodule
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