128 lines
3.5 KiB
Verilog
128 lines
3.5 KiB
Verilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module rw_manager_jumplogic(
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ck,
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reset_n,
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cntr_value,
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cntr_load,
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reg_select,
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reg_load_select,
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jump_value,
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jump_load,
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jump_check,
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jump_taken,
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jump_address,
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cntr_3,
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jump_ptr_0_export,
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jump_ptr_1_export,
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jump_cntr_0_export,
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jump_cntr_1_export
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);
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parameter DATA_WIDTH = 8;
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input ck;
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input reset_n;
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input [DATA_WIDTH-1:0] cntr_value;
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input cntr_load;
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input [1:0] reg_select;
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input [1:0] reg_load_select;
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input [DATA_WIDTH-1:0] jump_value;
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input jump_load;
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input jump_check;
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output jump_taken;
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output [DATA_WIDTH-1:0] jump_address;
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output [DATA_WIDTH-1:0] cntr_3;
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output [7:0] jump_ptr_0_export;
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output [7:0] jump_ptr_1_export;
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output [7:0] jump_cntr_0_export;
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output [7:0] jump_cntr_1_export;
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reg [7:0] cntr [0:3];
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reg [7:0] cntr_shadow [0:3];
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reg [7:0] jump_pointers [0:3];
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assign jump_ptr_0_export = jump_pointers [0];
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assign jump_ptr_1_export = jump_pointers [1];
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assign jump_cntr_0_export = cntr [0];
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assign jump_cntr_1_export = cntr [1];
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wire [3:0] comparisons;
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assign jump_address = jump_pointers[reg_select];
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assign jump_taken = (jump_check & ~comparisons[reg_select]);
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assign cntr_3 = cntr[3];
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genvar c;
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generate
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for(c = 0; c < 4; c = c + 1)
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begin : jumpcounter
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assign comparisons[c] = (cntr[c] == {DATA_WIDTH{1'b0}});
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always @(posedge ck or negedge reset_n) begin
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if(~reset_n) begin
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cntr[c] <= {DATA_WIDTH{1'b0}};
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end
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else if (cntr_load && reg_load_select == c) begin
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cntr[c] <= cntr_value;
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end
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else if (jump_check && reg_select == c) begin
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cntr[c] <= (comparisons[c]) ? cntr_shadow[c] : cntr[c] - 1'b1;
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end
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end
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end
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endgenerate
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always @(posedge ck or negedge reset_n) begin
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if(~reset_n) begin
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jump_pointers[0] <= {DATA_WIDTH{1'b0}};
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jump_pointers[1] <= {DATA_WIDTH{1'b0}};
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jump_pointers[2] <= {DATA_WIDTH{1'b0}};
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jump_pointers[3] <= {DATA_WIDTH{1'b0}};
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cntr_shadow[0] <= {DATA_WIDTH{1'b0}};
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cntr_shadow[1] <= {DATA_WIDTH{1'b0}};
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cntr_shadow[2] <= {DATA_WIDTH{1'b0}};
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cntr_shadow[3] <= {DATA_WIDTH{1'b0}};
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end
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else begin
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if(jump_load) begin
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jump_pointers[0] <= (reg_load_select == 2'b00)? jump_value : jump_pointers[0];
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jump_pointers[1] <= (reg_load_select == 2'b01)? jump_value : jump_pointers[1];
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jump_pointers[2] <= (reg_load_select == 2'b10)? jump_value : jump_pointers[2];
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jump_pointers[3] <= (reg_load_select == 2'b11)? jump_value : jump_pointers[3];
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end
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if(cntr_load) begin
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cntr_shadow[0] <= (reg_load_select == 2'b00)? cntr_value : cntr_shadow[0];
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cntr_shadow[1] <= (reg_load_select == 2'b01)? cntr_value : cntr_shadow[1];
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cntr_shadow[2] <= (reg_load_select == 2'b10)? cntr_value : cntr_shadow[2];
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cntr_shadow[3] <= (reg_load_select == 2'b11)? cntr_value : cntr_shadow[3];
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end
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end
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end
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endmodule
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