233 lines
7.8 KiB
Verilog
233 lines
7.8 KiB
Verilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module rw_manager_ddr3 (
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avl_clk,
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avl_reset_n,
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avl_address,
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avl_write,
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avl_writedata,
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avl_read,
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avl_readdata,
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avl_waitrequest,
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afi_clk,
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afi_reset_n,
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afi_addr,
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afi_ba,
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afi_cs_n,
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afi_cke,
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afi_odt,
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afi_ras_n,
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afi_cas_n,
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afi_we_n,
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afi_dqs_burst,
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afi_rst_n,
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afi_wdata,
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afi_wdata_valid,
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afi_dm,
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afi_rdata_en,
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afi_rdata_en_full,
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afi_rdata,
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afi_rdata_valid,
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afi_wrank,
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afi_rrank,
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csr_clk,
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csr_ena,
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csr_dout_phy,
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csr_dout
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);
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parameter AVL_DATA_WIDTH = 32;
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parameter AVL_ADDR_WIDTH = 16;
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parameter MEM_ADDRESS_WIDTH = 19;
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parameter MEM_CONTROL_WIDTH = 4;
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parameter MEM_DQ_WIDTH = 36;
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parameter MEM_DM_WIDTH = 4;
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parameter MEM_NUMBER_OF_RANKS = 1;
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parameter MEM_CLK_EN_WIDTH = 1;
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parameter MEM_BANK_WIDTH = 2;
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parameter MEM_ODT_WIDTH = 2;
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parameter MEM_CHIP_SELECT_WIDTH = 1;
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parameter MEM_READ_DQS_WIDTH = 4;
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parameter MEM_WRITE_DQS_WIDTH = 4;
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parameter AFI_RATIO = 2;
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parameter RATE = "Half";
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parameter HCX_COMPAT_MODE = 0;
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parameter DEVICE_FAMILY = "STRATIXIV";
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parameter AC_ROM_INIT_FILE_NAME = "AC_ROM.hex";
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parameter INST_ROM_INIT_FILE_NAME = "inst_ROM.hex";
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parameter DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT = 0;
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parameter DEBUG_WRITE_TO_READ_RATIO = 0;
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parameter MAX_DI_BUFFER_WORDS_LOG_2 = 0;
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parameter AVL_CLK_PS = 123;
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parameter AFI_CLK_PS = 456;
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parameter ENABLE_NON_DES_CAL = 0;
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parameter TREFI = 36000;
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parameter REFRESH_INTERVAL = 30000;
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parameter TRFC = 370;
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parameter AP_MODE_EN= 2'b00;
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input avl_clk;
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input avl_reset_n;
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input [AVL_ADDR_WIDTH-1:0] avl_address;
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input avl_write;
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input [AVL_DATA_WIDTH-1:0] avl_writedata;
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input avl_read;
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output [AVL_DATA_WIDTH-1:0] avl_readdata;
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output avl_waitrequest;
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input afi_clk;
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input afi_reset_n;
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output [MEM_ADDRESS_WIDTH * AFI_RATIO - 1:0] afi_addr;
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output [MEM_BANK_WIDTH * AFI_RATIO - 1:0] afi_ba;
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output [MEM_CHIP_SELECT_WIDTH * AFI_RATIO - 1:0] afi_cs_n;
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output [MEM_CLK_EN_WIDTH * AFI_RATIO - 1:0] afi_cke;
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output [MEM_ODT_WIDTH * AFI_RATIO - 1:0] afi_odt;
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output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_ras_n;
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output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_cas_n;
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output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_we_n;
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output [MEM_WRITE_DQS_WIDTH * AFI_RATIO - 1:0] afi_dqs_burst;
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output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_rst_n;
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output [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_wdata;
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output [MEM_WRITE_DQS_WIDTH * AFI_RATIO - 1:0] afi_wdata_valid;
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output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1:0] afi_dm;
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output [AFI_RATIO-1:0] afi_rdata_en;
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output [AFI_RATIO-1:0] afi_rdata_en_full;
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input [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_rdata;
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input [AFI_RATIO-1:0] afi_rdata_valid;
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output [MEM_WRITE_DQS_WIDTH * MEM_NUMBER_OF_RANKS * AFI_RATIO -1:0] afi_wrank;
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output [MEM_READ_DQS_WIDTH * MEM_NUMBER_OF_RANKS * AFI_RATIO -1:0] afi_rrank;
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input csr_clk;
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input csr_ena;
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input csr_dout_phy;
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output csr_dout;
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parameter AC_BUS_WIDTH = 30;
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wire [AC_BUS_WIDTH - 1:0] ac_bus;
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rw_manager_generic rw_mgr_inst (
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.avl_clk(avl_clk),
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.avl_reset_n(avl_reset_n),
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.avl_address(avl_address),
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.avl_write(avl_write),
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.avl_writedata(avl_writedata),
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.avl_read(avl_read),
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.avl_readdata(avl_readdata),
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.avl_waitrequest(avl_waitrequest),
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.afi_clk(afi_clk),
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.afi_reset_n(afi_reset_n),
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.ac_masked_bus (afi_cs_n),
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.ac_bus (ac_bus),
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.afi_wdata(afi_wdata),
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.afi_dm(afi_dm),
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.afi_odt(afi_odt),
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.afi_rdata(afi_rdata),
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.afi_rdata_valid(afi_rdata_valid[0]),
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.afi_wrank(afi_wrank),
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.afi_rrank(afi_rrank),
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.csr_clk(csr_clk),
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.csr_ena(csr_ena),
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.csr_dout_phy(csr_dout_phy),
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.csr_dout(csr_dout)
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);
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defparam rw_mgr_inst.AVL_CLK_PS = AVL_CLK_PS;
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defparam rw_mgr_inst.AFI_CLK_PS = AFI_CLK_PS;
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defparam rw_mgr_inst.ENABLE_NON_DES_CAL = ENABLE_NON_DES_CAL;
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defparam rw_mgr_inst.TREFI = TREFI;
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defparam rw_mgr_inst.REFRESH_INTERVAL = REFRESH_INTERVAL;
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defparam rw_mgr_inst.TRFC = TRFC;
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defparam rw_mgr_inst.AVL_DATA_WIDTH = AVL_DATA_WIDTH;
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defparam rw_mgr_inst.AVL_ADDRESS_WIDTH = AVL_ADDR_WIDTH;
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defparam rw_mgr_inst.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
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defparam rw_mgr_inst.MEM_DM_WIDTH = MEM_DM_WIDTH;
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defparam rw_mgr_inst.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
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defparam rw_mgr_inst.AC_BUS_WIDTH = AC_BUS_WIDTH;
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defparam rw_mgr_inst.AC_MASKED_BUS_WIDTH = MEM_CHIP_SELECT_WIDTH * AFI_RATIO;
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defparam rw_mgr_inst.MASK_WIDTH = MEM_CHIP_SELECT_WIDTH;
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defparam rw_mgr_inst.AFI_RATIO = AFI_RATIO;
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defparam rw_mgr_inst.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
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defparam rw_mgr_inst.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
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defparam rw_mgr_inst.MEM_NUMBER_OF_RANKS = MEM_NUMBER_OF_RANKS;
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defparam rw_mgr_inst.RATE = RATE;
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defparam rw_mgr_inst.HCX_COMPAT_MODE = HCX_COMPAT_MODE;
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defparam rw_mgr_inst.DEVICE_FAMILY = DEVICE_FAMILY;
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defparam rw_mgr_inst.DEBUG_READ_DI_WIDTH = 32;
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defparam rw_mgr_inst.DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT = DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT;
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defparam rw_mgr_inst.DEBUG_WRITE_TO_READ_RATIO = DEBUG_WRITE_TO_READ_RATIO;
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defparam rw_mgr_inst.MAX_DI_BUFFER_WORDS_LOG_2 = MAX_DI_BUFFER_WORDS_LOG_2;
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defparam rw_mgr_inst.AC_ROM_INIT_FILE_NAME = AC_ROM_INIT_FILE_NAME;
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defparam rw_mgr_inst.INST_ROM_INIT_FILE_NAME = INST_ROM_INIT_FILE_NAME;
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defparam rw_mgr_inst.AC_ODT_BIT =
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(AFI_RATIO == 4) ? 27 :
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(AFI_RATIO == 2) ? 25 :
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24;
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defparam rw_mgr_inst.AP_MODE_EN = AP_MODE_EN;
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generate
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begin
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wire [MEM_ADDRESS_WIDTH-1:0] afi_address_half;
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assign afi_address_half = ac_bus[12:0];
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assign afi_addr = {AFI_RATIO{afi_address_half}};
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assign afi_ba = {AFI_RATIO{ac_bus[15:13]}};
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assign afi_rst_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[16]}};
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assign afi_ras_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[17]}};
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assign afi_cas_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[18]}};
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assign afi_we_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[19]}};
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if (AFI_RATIO == 4) begin
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assign afi_dqs_burst = {{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[23]}},
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{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[22]}},
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{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[21]}},
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{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[20]}}};
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assign afi_rdata_en_full = {AFI_RATIO{ac_bus[24]}};
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assign afi_rdata_en = {AFI_RATIO{ac_bus[25]}};
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assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[26]}};
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assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[28]}};
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end else if (AFI_RATIO == 2) begin
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assign afi_dqs_burst = {{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 2){ac_bus[21]}}, {(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 2){ac_bus[20]}}};
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assign afi_rdata_en_full = {AFI_RATIO{ac_bus[22]}};
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assign afi_rdata_en = {AFI_RATIO{ac_bus[23]}};
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assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[24]}};
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assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[26]}};
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end else begin
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assign afi_dqs_burst = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[20]}};
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assign afi_rdata_en_full = {AFI_RATIO{ac_bus[21]}};
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assign afi_rdata_en = {AFI_RATIO{ac_bus[22]}};
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assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[23]}};
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assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[25]}};
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end
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end
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endgenerate
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endmodule
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