43 lines
1.6 KiB
Verilog
43 lines
1.6 KiB
Verilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module rw_manager_datamux(datain, sel, dataout);
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parameter DATA_WIDTH = 8;
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parameter SELECT_WIDTH = 1;
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parameter NUMBER_OF_CHANNELS = 2;
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input [NUMBER_OF_CHANNELS * DATA_WIDTH - 1 : 0] datain;
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input [SELECT_WIDTH - 1 : 0] sel;
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output [DATA_WIDTH - 1 : 0] dataout;
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wire [DATA_WIDTH - 1 : 0] vectorized_data [0 : NUMBER_OF_CHANNELS - 1];
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assign dataout = vectorized_data[sel];
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genvar c;
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generate
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for(c = 0 ; c < NUMBER_OF_CHANNELS ; c = c + 1)
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begin : channel_iterator
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assign vectorized_data[c] = datain[(c + 1) * DATA_WIDTH - 1 : c * DATA_WIDTH];
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end
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endgenerate
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`ifdef ADD_UNIPHY_SIM_SVA
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assert property (@datain NUMBER_OF_CHANNELS == 2**SELECT_WIDTH) else
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$error("%t, [DATAMUX ASSERT] NUMBER_OF_CHANNELS PARAMETER is incorrect, NUMBER_OF_CHANNELS = %d, 2**SELECT_WIDTH = %d", $time, NUMBER_OF_CHANNELS, 2**SELECT_WIDTH);
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`endif
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endmodule
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