97 lines
3.2 KiB
Verilog
97 lines
3.2 KiB
Verilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module rw_manager_bitcheck(
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ck,
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reset_n,
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clear,
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enable,
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read_data,
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reference_data,
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mask,
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error_word
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);
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parameter DATA_WIDTH = "";
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parameter AFI_RATIO = "";
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localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
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localparam DATA_BUS_SIZE = DATA_WIDTH * NUMBER_OF_WORDS;
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input ck;
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input reset_n;
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input clear;
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input enable;
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input [DATA_BUS_SIZE - 1 : 0] read_data;
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input [DATA_BUS_SIZE - 1 : 0] reference_data;
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input [NUMBER_OF_WORDS - 1 : 0] mask;
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output [DATA_WIDTH - 1 : 0] error_word;
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reg [DATA_BUS_SIZE - 1 : 0] read_data_r;
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reg [DATA_WIDTH - 1 : 0] error_word;
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reg enable_r;
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wire [DATA_WIDTH - 1 : 0] error_compute;
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always @(posedge ck or negedge reset_n) begin
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if(~reset_n) begin
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error_word <= {DATA_WIDTH{1'b0}};
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read_data_r <= {DATA_BUS_SIZE{1'b0}};
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enable_r <= 1'b0;
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end
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else begin
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if(clear) begin
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error_word <= {DATA_WIDTH{1'b0}};
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end
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else if(enable_r) begin
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error_word <= error_word | error_compute;
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end
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read_data_r <= read_data;
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enable_r <= enable;
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end
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end
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genvar b;
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generate
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for(b = 0; b < DATA_WIDTH; b = b + 1)
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begin : bit_loop
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if (AFI_RATIO == 4) begin
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assign error_compute[b] =
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((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
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((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]) |
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((read_data_r[b + 2 * DATA_WIDTH] ^ reference_data[b + 2 * DATA_WIDTH]) & ~mask[2]) |
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((read_data_r[b + 3 * DATA_WIDTH] ^ reference_data[b + 3 * DATA_WIDTH]) & ~mask[3]) |
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((read_data_r[b + 4 * DATA_WIDTH] ^ reference_data[b + 4 * DATA_WIDTH]) & ~mask[4]) |
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((read_data_r[b + 5 * DATA_WIDTH] ^ reference_data[b + 5 * DATA_WIDTH]) & ~mask[5]) |
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((read_data_r[b + 6 * DATA_WIDTH] ^ reference_data[b + 6 * DATA_WIDTH]) & ~mask[6]) |
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((read_data_r[b + 7 * DATA_WIDTH] ^ reference_data[b + 7 * DATA_WIDTH]) & ~mask[7]);
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end
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else if (AFI_RATIO == 2) begin
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assign error_compute[b] =
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((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
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((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]) |
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((read_data_r[b + 2 * DATA_WIDTH] ^ reference_data[b + 2 * DATA_WIDTH]) & ~mask[2])|
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((read_data_r[b + 3 * DATA_WIDTH] ^ reference_data[b + 3 * DATA_WIDTH]) & ~mask[3]);
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end
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else begin
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assign error_compute[b] =
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((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
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((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]);
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end
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end
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endgenerate
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endmodule
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