70 lines
1.8 KiB
Systemverilog
70 lines
1.8 KiB
Systemverilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module max10emif_dcfifo #
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( parameter
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numwords = 8,
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width = 24,
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widthu = 3
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)
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(
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data,
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rdclk,
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rdreq,
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wrclk,
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wrreq,
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q,
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aclr
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);
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input [width-1:0] data;
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input rdclk;
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input rdreq;
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input wrclk;
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input wrreq;
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output [width-1:0] q;
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input aclr;
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logic [widthu-1:0] rdptr;
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logic [widthu-1:0] wrptr;
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always_ff @ (posedge wrclk or posedge aclr)
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begin
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if (aclr)
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wrptr <= 0;
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else
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wrptr <= wrptr + wrreq;
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end
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always_ff @ (posedge rdclk or posedge aclr)
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begin
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if (aclr)
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rdptr <= 0;
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else
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rdptr <= rdptr + rdreq;
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end
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logic [width-1:0] fifo [numwords-1:0];
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always_ff @ (posedge wrclk)
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fifo [wrptr] <= data;
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assign q = fifo[rdptr];
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endmodule
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