321 lines
9.4 KiB
Systemverilog
321 lines
9.4 KiB
Systemverilog
/*
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This data_interface get the data from the sensor, and provide the data after background subtraction and cluster locating signal to next step
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The BKG_FRAME has to be the power of 2, and it belongs to [2,65536]
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CLU_THRESHOLD and CLU_SIZE are for cluster_locate; CLU_SIZE belongs to [0,319]
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*/
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`timescale 100 ps / 100 ps
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module data_interface #(parameter BKG_FRAME = 4, CLU_THRESHOLD = 54, CLU_SIZE = 4)
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(
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//Clock/reset
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input wire clk_clk, // clk.clk
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input wire rst_reset, // connect to int_reset from sensor_interface, to reset frameID to 0;
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//avalon ST sink
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input logic unsigned[31:0] data_in_data, // data_in.data
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output wire data_in_ready, // .ready
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input wire data_in_valid, // .valid
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input wire [1:0] data_in_empty, // .empty
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input wire data_in_endofpacket, // .endofpacket
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input wire data_in_startofpacket, // .startofpacket
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//avalon ST source
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output wire [31:0] data_out_data, // data_out.data
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output wire [1:0] data_out_empty, // .empty
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output wire data_out_endofpacket, // .endofpacket
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output wire data_out_startofpacket, // .startofpacket
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input wire data_out_ready, // .ready the UDP is ready
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output wire data_out_valid, // .valid
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output wire[26:0] frameID, // for assign signal in tb simulation
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output wire bkg_sub_on,
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output wire rst_frame, // this is for after data_interface
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//data for sig after bkg subtraction
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input wire sig_rdclk, //the read port for sig_ram
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input wire[8:0] sig_rdaddress, //0~319 for data. 500~502 for the 3 words head
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output wire[31:0] sig_out,
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output reg sig_ram_last,
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//the output of cluster_locate
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output wire[8:0] sig_ch_left,
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output wire[8:0] sig_ch_right,
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output wire has_cluster,
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output wire no_cluster
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);
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/*******the reset logic********************************/
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//the rst signal for every frame
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wire rst_frame_after_sensor_interface;
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assign rst_frame_after_sensor_interface = data_in_startofpacket || rst_reset;
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assign rst_frame = data_in_endofpacket || rst_reset;
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/*
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This is a frame counter;
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frameID +1 at the rising edge of data_in_startofpacket
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wire[26:0] frameID;
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if frame increase at 10kHz, the 27-bit frameID can count 3.72 hour frame
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*/
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frame_counter framectr(
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.clk_clk(clk_clk),
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.rst_reset(rst_reset),
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.sig(data_in_startofpacket),
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.frame_Num(frameID)
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);
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// *********************** ST interface ***********************
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reg [4:0] state; //State of the state machine
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localparam STATE_IDLE = 5'd0; //waiting for SOP
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localparam STATE_WORD0 = 5'd1; //sending first word :
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localparam STATE_WORD1 = 5'd2; //sending second word:
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localparam STATE_WORD2 = 5'd3; //sending third word :
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localparam STATE_DATA_PRO = 5'd4; //blocking data do the calculation
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localparam STATE_DATA_NEXT = 5'd7; //sending data
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localparam STATE_LOC = 5'd5; //calculatebb
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//Helper stuff
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reg [7:0] tx_ctr; //counter of sent data words range: 0~255
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localparam WORDS_TO_SEND = 163;
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//the number of clocks for STATE_DATA_PRO
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reg [5:0] delay_ctr;
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localparam DELAY_CLOCKS = 6'd3;
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/************** bkg RAM ****************************/
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/*
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for prepare the bkg signal by two RAM;
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one for data_in_data[31:16]; the other for data_in_data[15:0]
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the signal after bkg subtraction is 16 bit signed; the LSM bit is dropped out; (it's not important with current noise level)
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*/
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wire[15:0] bkg_signal0;
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wire[15:0] bkg_signal1;
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wire[31:0] bkg_input_data;
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//signal after subtract background
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//got the background signal at the third clock in STATE_DATA_PRO
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//and subtract it to 16 bit by giving up the LSM, i.e. divide 2.
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reg [16:0] signal0_17bit;
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reg [16:0] signal1_17bit;
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wire[15:0] signal0;
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wire[15:0] signal1;
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assign signal0 = bkg_sub_on?signal0_17bit[16:1]:signal0_17bit[15:0];
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assign signal1 = bkg_sub_on?signal1_17bit[16:1]:signal1_17bit[15:0];
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bkg_ram #(.TOTAL_FRAME(BKG_FRAME)) bkg_but0(
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.clk_clk(clk_clk),
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.rst_reset(rst_reset),
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.frameID(frameID[26:0]),
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.address(tx_ctr),
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.data_in_data(bkg_input_data[31:16]),
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.bkg_signal(bkg_signal0),
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.bkg_sub_status(bkg_sub_on)
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);
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bkg_ram #(.TOTAL_FRAME(BKG_FRAME)) bkg_but1(
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.clk_clk(clk_clk),
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.rst_reset(rst_reset),
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.frameID(frameID[26:0]),
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.address(tx_ctr),
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.data_in_data(bkg_input_data[15:0]),
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.bkg_signal(bkg_signal1)
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);
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assign bkg_input_data = (state==STATE_DATA_NEXT)?~data_in_data:15'b0;
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//The state machine
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always @(posedge clk_clk or posedge rst_reset)
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begin
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if (rst_reset)
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begin
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state <= STATE_IDLE;
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end
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else
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case(state)
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STATE_IDLE:
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begin
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if (data_in_startofpacket)
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begin
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state <= STATE_WORD0;
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tx_ctr <= 0;
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end
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end
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STATE_WORD0:
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begin
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if (data_out_ready)
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begin
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state <= STATE_WORD1;
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tx_ctr <= tx_ctr+ 1'b1;
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end
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end
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STATE_WORD1:
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begin
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if (data_out_ready)
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begin
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state <= STATE_WORD2;
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tx_ctr <= tx_ctr +1'b1;
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end
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end
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STATE_WORD2:
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begin
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if (data_out_ready)
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begin
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state <= STATE_DATA_PRO;
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tx_ctr <= tx_ctr +1'b1;
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delay_ctr <= DELAY_CLOCKS -1'b1;
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end
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end
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STATE_DATA_PRO:
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begin
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delay_ctr <= delay_ctr -1'b1;
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if (delay_ctr == 0)
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begin
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state <= STATE_DATA_NEXT;
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delay_ctr <= DELAY_CLOCKS - 1'b1;
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signal0_17bit <= {1'b0,~data_in_data[31:16]}-{1'b0,bkg_signal0};
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signal1_17bit <= {1'b0,~data_in_data[15:0]}-{1'b0,bkg_signal1};
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end
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end
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STATE_DATA_NEXT:
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begin
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if (data_out_ready)
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begin
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tx_ctr <= tx_ctr+1'b1;
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if (tx_ctr == WORDS_TO_SEND -1) //last word, size matches
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state <= STATE_LOC;
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else
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state <= STATE_DATA_PRO;
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end
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end
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STATE_LOC:
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begin
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state <= STATE_IDLE;
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end
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default:
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begin
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state <= STATE_IDLE;
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end
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endcase
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end
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assign data_in_ready = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT)&&data_out_ready;
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assign data_out_valid = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2 || state == STATE_DATA_NEXT) ? 1'b1 : 1'b0;
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//the output data is be reversed....so during transfer without signal it's FFFFF, the software HIT-DAQ will reverse it again
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assign data_out_data = (state == STATE_WORD0 || state == STATE_WORD1 || state == STATE_WORD2)? data_in_data:
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(state == STATE_DATA_NEXT)? {~signal0,~signal1}: 0;
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assign data_out_startofpacket = data_in_startofpacket;
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assign data_out_endofpacket = (state == STATE_DATA_NEXT & tx_ctr == WORDS_TO_SEND-1) ? 1'b1 : 1'b0;
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assign data_out_empty = 0;
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/*********************Prepare the data to cluster_locate******************************************/
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/*
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it is built by the fact that regardless data_out_ready signal, the STATE_DATA_PRO will go to STATE_DATA_NEXT
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so the signal after bkg sub will continue at least two clocks
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*/
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//the signal indicate the signal after bkg sub is ready or not; it's ready on next clock
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wire sub_bkg_signal_ready;
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assign sub_bkg_signal_ready = (state == STATE_DATA_PRO && delay_ctr == 0)? 1'b1 :1'b0;
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reg[8:0] cl_address;
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wire[15:0] cl_data_in_data;
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wire cl_data_in_valid;
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cluster_locate #(.THRESHOLD(CLU_THRESHOLD), .SIZE(CLU_SIZE)) cl_but(
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.clk_clk(clk_clk),
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.rst_reset(rst_frame_after_sensor_interface),
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.address(cl_address),
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.last_data(sig_ram_last),
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.data_in_data(cl_data_in_data),
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.data_in_valid(cl_data_in_valid),
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.sig_ch_left(sig_ch_left),
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.sig_ch_right(sig_ch_right),
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.has_cluster(has_cluster),
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.no_cluster(no_cluster)
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);
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reg[2:0] state_clu;
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localparam STATE_CLU_IDLE = 3'b1;
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localparam STATE_CLU_FIRST = 3'b10;
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localparam STATE_CLU_SECOND = 3'b100;
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assign cl_data_in_data = (state_clu == STATE_CLU_FIRST)? signal0:
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(state_clu == STATE_CLU_SECOND)? signal1: 16'b0;
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assign cl_data_in_valid = (bkg_sub_on && (state_clu == STATE_CLU_FIRST || state_clu == STATE_CLU_SECOND))? 1'b1: 1'b0;
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always @ (posedge clk_clk or posedge rst_frame_after_sensor_interface)
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begin
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if (rst_frame_after_sensor_interface)
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begin
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state_clu <= STATE_CLU_IDLE;
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cl_address <= 9'b0;
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end
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else case(state_clu)
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STATE_CLU_IDLE:
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begin
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if (sub_bkg_signal_ready)
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state_clu <= STATE_CLU_FIRST;
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end
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STATE_CLU_FIRST:
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begin
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state_clu <= STATE_CLU_SECOND;
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cl_address <= cl_address + 1'b1;
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end
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STATE_CLU_SECOND:
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begin
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state_clu <= STATE_CLU_IDLE;
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cl_address <= cl_address + 1'b1;
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end
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default:
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state_clu <= STATE_CLU_IDLE;
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endcase
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end
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/*********************ram for data after background subtraction**************************/
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/*when bkg_sub is not on, store the original data
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store the signal after bkg_sub in ram
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output the sig_ram_last signal
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*/
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wire sig_ram_wren;
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wire[31:0] sig_ram_data;
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wire[8:0] sig_wraddress;
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ram4sig sig_ram (
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.data(sig_ram_data),
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.rdaddress(sig_rdaddress),
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.rdclock(clk_clk),
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.wraddress(sig_wraddress),
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.wrclock(clk_clk),
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.wren(sig_ram_wren),
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.q(sig_out)
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);
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assign sig_ram_wren = (state_clu == STATE_CLU_FIRST || state_clu == STATE_CLU_SECOND)? 1'b1: 1'b0;
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assign sig_wraddress = cl_address;
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assign sig_ram_data = {16'b0,cl_data_in_data};
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assign sig_ram_last = (state == STATE_LOC)? 1'b1: 1'b0;
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endmodule
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