332 lines
11 KiB
Verilog
332 lines
11 KiB
Verilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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////////////////////////////////////////////////////////////////////
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//
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// ALTERA_ONCHIP_FLASH
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//
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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//
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////////////////////////////////////////////////////////////////////
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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`timescale 1 ps / 1 ps
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module altera_onchip_flash (
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// To/From System
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clock,
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reset_n,
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// To/From Avalon_MM data slave interface
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avmm_data_read,
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avmm_data_write,
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avmm_data_addr,
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avmm_data_writedata,
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avmm_data_burstcount,
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avmm_data_waitrequest,
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avmm_data_readdatavalid,
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avmm_data_readdata,
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// To/From Avalon_MM csr slave interface
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avmm_csr_read,
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avmm_csr_write,
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avmm_csr_addr,
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avmm_csr_writedata,
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avmm_csr_readdata
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);
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parameter DEVICE_FAMILY = "MAX 10";
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parameter PART_NAME = "Unknown";
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parameter IS_DUAL_BOOT = "False";
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parameter IS_ERAM_SKIP = "False";
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parameter IS_COMPRESSED_IMAGE = "False";
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parameter INIT_FILENAME = "";
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// simulation only start
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parameter DEVICE_ID = "08";
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parameter INIT_FILENAME_SIM = "";
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// simulation only end
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parameter PARALLEL_MODE = 0;
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parameter READ_AND_WRITE_MODE = 0;
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parameter WRAPPING_BURST_MODE = 0;
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parameter AVMM_CSR_DATA_WIDTH = 32;
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parameter AVMM_DATA_DATA_WIDTH = 32;
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parameter AVMM_DATA_ADDR_WIDTH = 20;
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parameter AVMM_DATA_BURSTCOUNT_WIDTH = 13;
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parameter FLASH_DATA_WIDTH = 32;
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parameter FLASH_ADDR_WIDTH = 23;
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parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read. only need in parallel mode.
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parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read. only need in parallel mode.
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parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment. only need in parallel mode.
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parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
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parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (960ns)
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parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
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parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
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parameter MIN_VALID_ADDR = 1;
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parameter MAX_VALID_ADDR = 1;
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parameter MIN_UFM_VALID_ADDR = 1;
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parameter MAX_UFM_VALID_ADDR = 1;
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parameter SECTOR1_START_ADDR = 1;
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parameter SECTOR1_END_ADDR = 1;
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parameter SECTOR2_START_ADDR = 1;
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parameter SECTOR2_END_ADDR = 1;
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parameter SECTOR3_START_ADDR = 1;
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parameter SECTOR3_END_ADDR = 1;
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parameter SECTOR4_START_ADDR = 1;
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parameter SECTOR4_END_ADDR = 1;
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parameter SECTOR5_START_ADDR = 1;
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parameter SECTOR5_END_ADDR = 1;
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parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
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parameter SECTOR1_MAP = 1;
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parameter SECTOR2_MAP = 1;
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parameter SECTOR3_MAP = 1;
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parameter SECTOR4_MAP = 1;
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parameter SECTOR5_MAP = 1;
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parameter ADDR_RANGE1_END_ADDR = 1;
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parameter ADDR_RANGE2_END_ADDR = 1;
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parameter ADDR_RANGE1_OFFSET = 1;
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parameter ADDR_RANGE2_OFFSET = 1;
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parameter ADDR_RANGE3_OFFSET = 1;
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// To/From System
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input clock;
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input reset_n;
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// To/From Avalon_MM data slave interface
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input avmm_data_read;
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input avmm_data_write;
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input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_data_addr;
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input [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_writedata;
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input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_data_burstcount;
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output avmm_data_waitrequest;
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output avmm_data_readdatavalid;
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output [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata;
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// To/From Avalon_MM csr slave interface
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input avmm_csr_read;
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input avmm_csr_write;
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input avmm_csr_addr;
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input [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_writedata;
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output [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata;
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wire [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata_wire;
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wire [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata_wire;
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wire [31:0] csr_control_wire;
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wire [9:0] csr_status_wire;
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wire [FLASH_ADDR_WIDTH-1:0] flash_ardin_wire;
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wire [FLASH_DATA_WIDTH-1:0] flash_drdout_wire;
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wire flash_busy;
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wire flash_se_pass;
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wire flash_sp_pass;
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wire flash_osc;
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wire flash_xe_ye;
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wire flash_se;
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wire flash_arclk;
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wire flash_arshft;
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wire flash_drclk;
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wire flash_drshft;
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wire flash_drdin;
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wire flash_nprogram;
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wire flash_nerase;
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wire flash_par_en;
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wire flash_xe_ye_wire;
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wire flash_se_wire;
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assign avmm_data_readdata = avmm_data_readdata_wire;
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generate
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if (READ_AND_WRITE_MODE == 0) begin
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assign avmm_csr_readdata = 32'hffffffff;
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assign csr_control_wire = 32'h3fffffff;
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end
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else begin
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assign avmm_csr_readdata = avmm_csr_readdata_wire;
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end
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endgenerate
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generate
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if (DEVICE_ID == "02" || DEVICE_ID == "01") begin
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assign flash_par_en = 1'b1;
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assign flash_xe_ye = 1'b1;
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assign flash_se = 1'b1;
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end
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else begin
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assign flash_par_en = PARALLEL_MODE[0];
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assign flash_xe_ye = flash_xe_ye_wire;
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assign flash_se = flash_se_wire;
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end
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endgenerate
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generate
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if (READ_AND_WRITE_MODE) begin
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// -------------------------------------------------------------------
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// Instantiate a Avalon_MM csr slave controller
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// -------------------------------------------------------------------
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altera_onchip_flash_avmm_csr_controller avmm_csr_controller (
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// To/From System
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.clock(clock),
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.reset_n(reset_n),
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// To/From Avalon_MM csr slave interface
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.avmm_read(avmm_csr_read),
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.avmm_write(avmm_csr_write),
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.avmm_addr(avmm_csr_addr),
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.avmm_writedata(avmm_csr_writedata),
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.avmm_readdata(avmm_csr_readdata_wire),
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// To/From Avalon_MM data slave interface
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.csr_control(csr_control_wire),
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.csr_status(csr_status_wire)
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);
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end
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endgenerate
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// -------------------------------------------------------------------
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// Instantiate a Avalon_MM data slave controller
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// -------------------------------------------------------------------
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altera_onchip_flash_avmm_data_controller # (
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.READ_AND_WRITE_MODE (READ_AND_WRITE_MODE),
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.WRAPPING_BURST_MODE (WRAPPING_BURST_MODE),
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.AVMM_DATA_ADDR_WIDTH (AVMM_DATA_ADDR_WIDTH),
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.AVMM_DATA_BURSTCOUNT_WIDTH (AVMM_DATA_BURSTCOUNT_WIDTH),
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.FLASH_SEQ_READ_DATA_COUNT (FLASH_SEQ_READ_DATA_COUNT),
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.FLASH_READ_CYCLE_MAX_INDEX (FLASH_READ_CYCLE_MAX_INDEX),
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.FLASH_ADDR_ALIGNMENT_BITS (FLASH_ADDR_ALIGNMENT_BITS),
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.FLASH_RESET_CYCLE_MAX_INDEX (FLASH_RESET_CYCLE_MAX_INDEX),
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.FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX (FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX),
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.FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX),
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.FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX),
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.MIN_VALID_ADDR (MIN_VALID_ADDR),
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.MAX_VALID_ADDR (MAX_VALID_ADDR),
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.SECTOR1_START_ADDR (SECTOR1_START_ADDR),
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.SECTOR1_END_ADDR (SECTOR1_END_ADDR),
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.SECTOR2_START_ADDR (SECTOR2_START_ADDR),
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.SECTOR2_END_ADDR (SECTOR2_END_ADDR),
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.SECTOR3_START_ADDR (SECTOR3_START_ADDR),
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.SECTOR3_END_ADDR (SECTOR3_END_ADDR),
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.SECTOR4_START_ADDR (SECTOR4_START_ADDR),
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.SECTOR4_END_ADDR (SECTOR4_END_ADDR),
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.SECTOR5_START_ADDR (SECTOR5_START_ADDR),
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.SECTOR5_END_ADDR (SECTOR5_END_ADDR),
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.SECTOR_READ_PROTECTION_MODE (SECTOR_READ_PROTECTION_MODE),
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.SECTOR1_MAP (SECTOR1_MAP),
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.SECTOR2_MAP (SECTOR2_MAP),
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.SECTOR3_MAP (SECTOR3_MAP),
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.SECTOR4_MAP (SECTOR4_MAP),
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.SECTOR5_MAP (SECTOR5_MAP),
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.ADDR_RANGE1_END_ADDR (ADDR_RANGE1_END_ADDR),
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.ADDR_RANGE2_END_ADDR (ADDR_RANGE2_END_ADDR),
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.ADDR_RANGE1_OFFSET (ADDR_RANGE1_OFFSET),
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.ADDR_RANGE2_OFFSET (ADDR_RANGE2_OFFSET),
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.ADDR_RANGE3_OFFSET (ADDR_RANGE3_OFFSET)
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) avmm_data_controller (
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// To/From System
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.clock(clock),
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.reset_n(reset_n),
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// To/From Flash IP interface
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.flash_busy(flash_busy),
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.flash_se_pass(flash_se_pass),
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.flash_sp_pass(flash_sp_pass),
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.flash_osc(flash_osc),
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.flash_drdout(flash_drdout_wire),
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.flash_xe_ye(flash_xe_ye_wire),
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.flash_se(flash_se_wire),
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.flash_arclk(flash_arclk),
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.flash_arshft(flash_arshft),
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.flash_drclk(flash_drclk),
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.flash_drshft(flash_drshft),
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.flash_drdin(flash_drdin),
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.flash_nprogram(flash_nprogram),
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.flash_nerase(flash_nerase),
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.flash_ardin(flash_ardin_wire),
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// To/From Avalon_MM data slave interface
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.avmm_read(avmm_data_read),
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.avmm_write(avmm_data_write),
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.avmm_addr(avmm_data_addr),
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.avmm_writedata(avmm_data_writedata),
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.avmm_burstcount(avmm_data_burstcount),
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.avmm_waitrequest(avmm_data_waitrequest),
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.avmm_readdatavalid(avmm_data_readdatavalid),
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.avmm_readdata(avmm_data_readdata_wire),
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// To/From Avalon_MM csr slave interface
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.csr_control(csr_control_wire),
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.csr_status(csr_status_wire)
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);
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// -------------------------------------------------------------------
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// Instantiate wysiwyg for onchip flash block
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// -------------------------------------------------------------------
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altera_onchip_flash_block # (
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.DEVICE_FAMILY (DEVICE_FAMILY),
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.PART_NAME (PART_NAME),
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.IS_DUAL_BOOT (IS_DUAL_BOOT),
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.IS_ERAM_SKIP (IS_ERAM_SKIP),
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.IS_COMPRESSED_IMAGE (IS_COMPRESSED_IMAGE),
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.INIT_FILENAME (INIT_FILENAME),
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.MIN_VALID_ADDR (MIN_VALID_ADDR),
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.MAX_VALID_ADDR (MAX_VALID_ADDR),
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.MIN_UFM_VALID_ADDR (MIN_UFM_VALID_ADDR),
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.MAX_UFM_VALID_ADDR (MAX_UFM_VALID_ADDR),
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.ADDR_RANGE1_END_ADDR (ADDR_RANGE1_END_ADDR),
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.ADDR_RANGE2_END_ADDR (ADDR_RANGE2_END_ADDR),
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.ADDR_RANGE1_OFFSET (ADDR_RANGE1_OFFSET),
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.ADDR_RANGE2_OFFSET (ADDR_RANGE2_OFFSET),
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.ADDR_RANGE3_OFFSET (ADDR_RANGE3_OFFSET),
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// simulation only start
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.DEVICE_ID (DEVICE_ID),
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.INIT_FILENAME_SIM (INIT_FILENAME_SIM)
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// simulation only end
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) altera_onchip_flash_block (
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.xe_ye(flash_xe_ye),
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.se(flash_se),
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.arclk(flash_arclk),
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.arshft(flash_arshft),
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.ardin(flash_ardin_wire),
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.drclk(flash_drclk),
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.drshft(flash_drshft),
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.drdin(flash_drdin),
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.nprogram(flash_nprogram),
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.nerase(flash_nerase),
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.nosc_ena(1'b0),
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.par_en(flash_par_en),
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.drdout(flash_drdout_wire),
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.busy(flash_busy),
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.se_pass(flash_se_pass),
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.sp_pass(flash_sp_pass),
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.osc(flash_osc)
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);
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endmodule //altera_onchip_flash
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//VALID FILE
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