93 lines
2.9 KiB
Tcl
93 lines
2.9 KiB
Tcl
# (C) 2001-2019 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions and other
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# software and tools, and its AMPP partner logic functions, and any output
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# files from any of the foregoing (including device programming or simulation
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# files), and any associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License Subscription
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# Agreement, Intel FPGA IP License Agreement, or other applicable
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# license agreement, including, without limitation, that your use is for the
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# sole purpose of programming logic devices manufactured by Intel and sold by
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# Intel or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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#**************************************************************
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# Time Information
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#**************************************************************
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#**************************************************************
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# Create Clock
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#**************************************************************
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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set_false_path -to [get_registers {*|flash_busy_reg}]
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set_false_path -to [get_registers {*|flash_busy_clear_reg}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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