250 lines
10 KiB
Verilog
250 lines
10 KiB
Verilog
// (C) 2001-2019 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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module altera_msgdma_prefetcher #(
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parameter ENHANCED_FEATURES = 0,
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parameter ENABLE_READ_BURST = 0,
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parameter MAX_READ_BURST_COUNT = 4,
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parameter MAX_READ_BURST_COUNT_WIDTH = 3,
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parameter DATA_WIDTH = 32,
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parameter DATA_BYTEENABLE_WIDTH = 4,
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parameter DESCRIPTOR_WIDTH = 128,
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parameter ADDRESS_WIDTH = 32,
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parameter RESPONSE_FIFO_DEPTH = 256,
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parameter RESPONSE_FIFO_DEPTH_LOG2 = 7
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) (
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input clk,
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input reset,
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input [DATA_WIDTH-1:0] mm_read_readdata,
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input mm_read_waitrequest,
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input mm_read_readdatavalid,
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input st_src_descr_ready,
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input mm_write_waitrequest,
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input mm_write_writeresponsevalid,
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input [1:0] mm_write_response, // don't care the response status
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input st_snk_valid,
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input [255:0] st_snk_data,
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input [2:0] mm_csr_address,
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input mm_csr_write,
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input mm_csr_read,
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input [31:0] mm_csr_writedata,
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output [ADDRESS_WIDTH-1:0] mm_read_address,
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output mm_read_read,
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output [MAX_READ_BURST_COUNT_WIDTH-1:0] mm_read_burstcount,
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output st_src_descr_valid,
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output [DESCRIPTOR_WIDTH-1:0] st_src_descr_data,
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output [ADDRESS_WIDTH-1:0] mm_write_address,
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output mm_write_write,
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output [DATA_WIDTH-1:0] mm_write_writedata,
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output [DATA_BYTEENABLE_WIDTH-1:0] mm_write_byteenable,
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output st_snk_ready,
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output csr_irq,
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output [31:0] mm_csr_readdata
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);
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localparam RESPONSE_FIFO_WIDTH = (ENHANCED_FEATURES == 1) ? 96 : 64;
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wire run;
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wire reset_prefetcher;
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wire [31:0] nxt_desc_ptr_low;
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wire [31:0] nxt_desc_ptr_high;
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wire desc_poll_en;
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wire [15:0] desc_poll_freq;
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wire put_resp_fifo;
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wire [RESPONSE_FIFO_WIDTH-1:0] resp_fifo_wdata;
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wire clear_run;
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wire update_nxt_desc_ptr;
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wire [63:0] updated_ptr_desc;
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wire [RESPONSE_FIFO_WIDTH-1:0] resp_fifo_rdata;
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wire get_resp_fifo;
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wire park_mode;
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wire write_back_done;
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wire transfer_complete_irq_mask;
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wire [7:0] error_irq_mask;
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wire early_termination_irq_mask;
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wire [7:0] error;
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wire early_termination;
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wire clear_irq;
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wire global_interrupt_enable_mask;
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wire reset_complete_from_read;
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wire reset_complete_from_write_back;
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wire reset_complete;
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wire resp_fifo_full;
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altera_msgdma_prefetcher_read #(
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.ENHANCED_FEATURES (ENHANCED_FEATURES),
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.ENABLE_READ_BURST (ENABLE_READ_BURST),
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.MAX_READ_BURST_COUNT (MAX_READ_BURST_COUNT),
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.MAX_READ_BURST_COUNT_WIDTH (MAX_READ_BURST_COUNT_WIDTH),
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.DATA_WIDTH (DATA_WIDTH),
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.ADDRESS_WIDTH (ADDRESS_WIDTH),
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.DESCRIPTOR_WIDTH (DESCRIPTOR_WIDTH),
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.RESPONSE_FIFO_WIDTH (RESPONSE_FIFO_WIDTH)
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) u_prefetcher_read (
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// inputs
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.clk (clk),
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.reset (reset),
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.mm_read_readdata (mm_read_readdata),
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.mm_read_waitrequest (mm_read_waitrequest),
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.mm_read_readdatavalid (mm_read_readdatavalid),
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.st_src_descr_ready (st_src_descr_ready),
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.run (run),
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.reset_prefetcher (reset_prefetcher),
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.nxt_desc_ptr_low (nxt_desc_ptr_low),
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.nxt_desc_ptr_high (nxt_desc_ptr_high),
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.desc_poll_en (desc_poll_en),
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.desc_poll_freq (desc_poll_freq),
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.resp_fifo_full (resp_fifo_full),
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// outputs
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.mm_read_address (mm_read_address),
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.mm_read_read (mm_read_read),
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.mm_read_burstcount (mm_read_burstcount),
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.st_src_descr_valid (st_src_descr_valid),
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.st_src_descr_data (st_src_descr_data),
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.put_resp_fifo (put_resp_fifo),
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.resp_fifo_wdata (resp_fifo_wdata),
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.clear_run (clear_run),
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.update_nxt_desc_ptr (update_nxt_desc_ptr),
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.updated_ptr_desc (updated_ptr_desc),
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.reset_complete (reset_complete_from_read)
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);
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altera_msgdma_prefetcher_write_back #(
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.ENHANCED_FEATURES (ENHANCED_FEATURES),
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.DATA_WIDTH (DATA_WIDTH),
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.DATA_BYTEENABLE_WIDTH (DATA_BYTEENABLE_WIDTH),
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.ADDRESS_WIDTH (ADDRESS_WIDTH),
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.RESPONSE_FIFO_WIDTH (RESPONSE_FIFO_WIDTH)
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) u_prefetcher_write_back (
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// inputs
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.clk (clk),
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.reset (reset),
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.mm_write_waitrequest (mm_write_waitrequest),
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.mm_write_response (mm_write_response),
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.mm_write_writeresponsevalid (mm_write_writeresponsevalid),
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.st_snk_valid (st_snk_valid),
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.st_snk_data (st_snk_data),
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.resp_fifo_rdata (resp_fifo_rdata),
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.park_mode (park_mode),
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.run (run),
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.reset_prefetcher (reset_prefetcher),
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// outputs
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.mm_write_address (mm_write_address),
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.mm_write_write (mm_write_write),
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.mm_write_writedata (mm_write_writedata),
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.mm_write_byteenable (mm_write_byteenable),
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.st_snk_ready (st_snk_ready),
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.get_resp_fifo (get_resp_fifo),
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.write_back_done (write_back_done),
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.transfer_complete_irq_mask (transfer_complete_irq_mask),
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.error_irq_mask (error_irq_mask),
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.early_termination_irq_mask (early_termination_irq_mask),
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.error (error),
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.early_termination (early_termination),
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.reset_complete (reset_complete_from_write_back)
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);
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altera_msgdma_prefetcher_fifo #(
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.RESPONSE_FIFO_WIDTH (RESPONSE_FIFO_WIDTH),
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.RESPONSE_FIFO_DEPTH (RESPONSE_FIFO_DEPTH),
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.RESPONSE_FIFO_DEPTH_LOG2 (RESPONSE_FIFO_DEPTH_LOG2),
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.LATENCY (2)
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) u_prefetcher_fifo (
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// inputs
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.clk (clk),
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.areset (reset),
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.sreset (reset_complete),
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.wr_data (resp_fifo_wdata),
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.wrreq (put_resp_fifo),
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.rdreq (get_resp_fifo),
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// outputs
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.full (resp_fifo_full),
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.rd_data (resp_fifo_rdata)
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);
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altera_msgdma_prefetcher_csr u_prefetcher_csr (
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// inputs
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.clk (clk),
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.reset (reset),
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.mm_csr_address (mm_csr_address),
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.mm_csr_write (mm_csr_write),
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.mm_csr_read (mm_csr_read),
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.mm_csr_writedata (mm_csr_writedata),
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.clear_run (clear_run),
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.reset_complete (reset_complete),
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.irq (csr_irq),
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.update_nxt_desc_ptr (update_nxt_desc_ptr),
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.updated_ptr_desc (updated_ptr_desc),
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// outputs
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.mm_csr_readdata (mm_csr_readdata),
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.run (run),
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.reset_prefetcher (reset_prefetcher),
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.clear_irq (clear_irq),
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.nxt_desc_ptr_low (nxt_desc_ptr_low),
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.nxt_desc_ptr_high (nxt_desc_ptr_high),
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.desc_poll_en (desc_poll_en),
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.desc_poll_freq (desc_poll_freq),
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.global_interrupt_enable_mask (global_interrupt_enable_mask),
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.park_mode (park_mode)
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);
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altera_msgdma_prefetcher_interrupt u_prefetcher_interrupt (
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// inputs
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.clk (clk),
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.reset (reset),
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.write_back_done (write_back_done),
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.transfer_complete_irq_mask (transfer_complete_irq_mask),
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.error_irq_mask (error_irq_mask),
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.early_termination_irq_mask (early_termination_irq_mask),
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.error (error),
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.early_termination (early_termination),
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.clear_irq (clear_irq),
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.global_interrupt_enable_mask (global_interrupt_enable_mask),
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// outputs
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.irq (csr_irq)
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);
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assign reset_complete = reset_complete_from_read & reset_complete_from_write_back;
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endmodule
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