62 lines
2.1 KiB
Verilog
62 lines
2.1 KiB
Verilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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module altera_dual_boot
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(
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clk,
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nreset,
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avmm_rcv_address,
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avmm_rcv_writedata,
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avmm_rcv_write,
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avmm_rcv_read,
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avmm_rcv_readdata
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);
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parameter LPM_TYPE = "ALTERA_DUAL_BOOT";
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parameter INTENDED_DEVICE_FAMILY = "MAX 10 FPGA";
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parameter A_WIDTH = 3;
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parameter WD_WIDTH = 4;
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parameter RD_WIDTH = 17;
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parameter MAX_DATA_WIDTH = 32;
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parameter CONFIG_CYCLE = 28;
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parameter RESET_TIMER_CYCLE = 40;
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input clk;
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input nreset;
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input [A_WIDTH-1:0] avmm_rcv_address;
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input [MAX_DATA_WIDTH-1:0] avmm_rcv_writedata;
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input avmm_rcv_write;
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input avmm_rcv_read;
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output [MAX_DATA_WIDTH-1:0] avmm_rcv_readdata;
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alt_dual_boot_avmm alt_dual_boot_avmm_comp
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(
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.clk(clk),
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.nreset(nreset),
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.avmm_rcv_address(avmm_rcv_address),
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.avmm_rcv_writedata(avmm_rcv_writedata),
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.avmm_rcv_write(avmm_rcv_write),
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.avmm_rcv_read(avmm_rcv_read),
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.avmm_rcv_readdata(avmm_rcv_readdata)
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);
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defparam
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alt_dual_boot_avmm_comp.LPM_TYPE = LPM_TYPE,
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alt_dual_boot_avmm_comp.INTENDED_DEVICE_FAMILY = INTENDED_DEVICE_FAMILY,
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alt_dual_boot_avmm_comp.A_WIDTH = A_WIDTH,
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alt_dual_boot_avmm_comp.MAX_DATA_WIDTH = MAX_DATA_WIDTH,
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alt_dual_boot_avmm_comp.WD_WIDTH = WD_WIDTH,
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alt_dual_boot_avmm_comp.RD_WIDTH = RD_WIDTH,
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alt_dual_boot_avmm_comp.CONFIG_CYCLE = CONFIG_CYCLE,
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alt_dual_boot_avmm_comp.RESET_TIMER_CYCLE = RESET_TIMER_CYCLE;
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endmodule
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