135 lines
2.5 KiB
Verilog
135 lines
2.5 KiB
Verilog
//testbench for stl2sts: ST long 32-bit to ST short 16-bit
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`timescale 1 ns / 1 ns
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module st2mm_tb();
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localparam CLK_PERIOD = 20;
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reg clk;
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reg rst;
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//avalon ST(Streaming) sink: 0 readlatency and 0 readallowence
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reg [31:0] data_in_data;
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wire data_in_ready;
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wire data_in_valid;
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reg [1:0] data_in_empty;
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reg data_in_startofpacket;
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reg data_in_endofpacket;
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//avalon MM(Memory Mapped) source writelatency 0; readlatency 1 but no read logic here
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wire [8:0] mm_address;
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wire mm_chipselect; // only for write
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wire [31:0] mm_readdate; //do not read
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wire mm_write;
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wire [31:0] mm_writedata;
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reg mm_waitrequest_n;
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reg [1:0] state;
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localparam STATE_IDLE = 2'd0;
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localparam STATE_SEND = 2'd1;
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localparam STATE_LOC = 2'd3;
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st2mm #(.BITSIZE(32), .EMPTY_SIZE(2)) st2mm_dut(
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.clk (clk),
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.rst (rst),
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.data_in_data (data_in_data),
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.data_in_ready (data_in_ready),
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.data_in_valid (data_in_valid),
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.data_in_empty (data_in_empty),
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.data_in_startofpacket (data_in_startofpacket),
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.data_in_endofpacket (data_in_endofpacket),
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.mm_address (mm_address),
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.mm_chipselect (mm_chipselect),
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.mm_readdate (mm_readdate),
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.mm_write (mm_write),
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.mm_writedata (mm_writedata),
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.mm_waitrequest_n (mm_waitrequest_n)
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);
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initial begin
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clk = 1'b1;
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rst = 1'b1;
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data_in_data = 0;
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data_in_empty = 2'b0;
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data_in_startofpacket = 1'b0;
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data_in_endofpacket = 1'b0;
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mm_waitrequest_n = 1'b0;
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state = STATE_IDLE;
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#(CLK_PERIOD*2);
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rst = 1'b0;
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//the next sink is ready..
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#(CLK_PERIOD*20);
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mm_waitrequest_n = 1'b1;
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//start packet
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#(CLK_PERIOD*2+1);
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data_in_startofpacket = 1'b1;
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#(CLK_PERIOD*2);
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mm_waitrequest_n = 1'b0;
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#(CLK_PERIOD*2);
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mm_waitrequest_n = 1'b1;
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//end packet
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#(CLK_PERIOD*5);
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data_in_endofpacket = 1'b1;
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#(CLK_PERIOD*200); $stop;
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end
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//clk
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always #(CLK_PERIOD/2) clk = ~ clk;
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assign data_in_valid = (state == STATE_SEND || data_in_startofpacket || data_in_endofpacket)? 1'b1 : 1'b0;
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always @(posedge clk) begin
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case(state)
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STATE_IDLE:
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begin
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if (data_in_startofpacket && data_in_ready)
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begin
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state <= STATE_SEND;
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data_in_data <= data_in_data + 1;
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data_in_startofpacket <= 1'b0;
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end
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end
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STATE_SEND:
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begin
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if (data_in_ready)
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begin
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if (data_in_endofpacket) begin
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state <= STATE_LOC;
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data_in_data <= 0;
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data_in_endofpacket <= 1'b0;
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end else begin
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data_in_data <= data_in_data + 1;
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end
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end
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end
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STATE_LOC:
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begin
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state <= STATE_IDLE;
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end
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endcase
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end
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endmodule
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