queue size: 0 starting:cali_ram "cali_ram" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 1 modules, 0 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation cali_ram" reuses altera_avalon_onchip_memory2 "submodules/cali_ram_cali_ram"]]> queue size: 0 starting:altera_avalon_onchip_memory2 "submodules/cali_ram_cali_ram" Starting RTL generation for module 'cali_ram_cali_ram' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=cali_ram_cali_ram --dir=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen//cali_ram_cali_ram_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'cali_ram_cali_ram' cali_ram" instantiated altera_avalon_onchip_memory2 "cali_ram"]]> queue size: 0 starting:altera_avalon_onchip_memory2 "submodules/cali_ram_cali_ram" Starting RTL generation for module 'cali_ram_cali_ram' Generation command is [exec /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/linux64/perl/bin/perl -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin/europa -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/sopc_builder/bin -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /auto/work/qinliqing/intelFPGA_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=cali_ram_cali_ram --dir=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen/ --quartus_dir=/auto/work/qinliqing/intelFPGA_lite/19.1/quartus --verilog --config=/tmp/alt9906_933226990253683904.dir/0002_cali_ram_gen//cali_ram_cali_ram_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'cali_ram_cali_ram' cali_ram" instantiated altera_avalon_onchip_memory2 "cali_ram"]]>